JPH11212765A - Addition circuit and addition device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an addition circuit of a small-scale circuit capable of high-speed subtraction as well and an addition device provided with plural pieces of the addition circuits. SOLUTION: A partial sum generation part 21 receives input signals X and Y, carry input signals Ci and borrow input signals Bi, and generates '0' as a partial sum SM in the case that '1' of the values of the respective signals is an even number and generates '1' in the case of an odd number. A carry generation part 22 receives the input signals X and Y, the carry input signals Ci and the borrow input signals Bi, generates '1' as carry output signals Co in the case that two or more values of the respective signals are '1' and the borrow input signals Bi are '0' and generates '0' in the other case. A borrow generation part 23 receives the input signals X and Y and the borrow input signals Bi, generates '1' as borrow output signals Bo in the case that the input signals X and Y are '0' and the borrow input signals Bi are '1' and generates '0' in the other case.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder circuit capable of performing high-speed subtraction with a small-scale circuit by adding a borrow function to a normal adder circuit having a carry (carry) function. The present invention relates to an adding device having a plurality of adding circuits.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a conventional addition circuit. This adder circuit 10 receives input signals X and Y
A partial sum generation unit 11 that inputs the carry input signal Ci and outputs a partial sum SM, and a carry generation unit 12 that receives the input signals X and Y and the carry input signal Ci and outputs a carry output signal Co. It is configured. Partial sum generation unit 11
Has a two-input exclusive OR circuit (hereinafter, referred to as an EOR circuit) 11a for inputting input signals X and Y represented by one digit binary number. An output terminal of the EOR circuit 11a is connected to a first input terminal of a two-input EOR circuit 11b, and a carry input signal Ci indicating a lower carry is input to a second input terminal of the EOR circuit 11b. The partial sum SM of each signal is output from the output terminal of the EOR circuit 11b. Carry generation unit 12
Is a two-input OR circuit 12a for inputting the input signals X and Y
And a two-input OR circuit 12b for inputting the input signal X and the carry input signal Ci, and a two-input OR circuit 12c for receiving the input signal Y and the carry input signal Ci. The output terminal of each OR circuit 12a, 12b, 12c is 3
The input is connected to the input terminal of an AND circuit 12d,
A carry output signal Co indicating a carry to a higher order is output from an output terminal of the D circuit 12d.

FIG. 3 is a diagram for explaining the operation of FIG. As shown in FIG. 3, adder circuit 10 adds input signals X, Y and carry signal Ci to generate partial sum SM and carry output signal Co. FIG. 4 is a circuit diagram showing a configuration example of a conventional addition device. This adder includes a plurality of (n + 1) adder circuits 1 having the same configuration as the adder circuit 10 of FIG.
0 ₀ ,..., 10 _n . These adder circuits 10
_0, ..., 10 _n are connected in cascade to deliver a carry output signal to the upper and enter the lower carry input signal. Addition circuit 10 _0, ..., 10 an input signal of the multi-bit to the input terminals of the _n X _0, ..., X _n and the input signal Y _0, ...,
Each bit of Y _n is input, and a partial sum SM ₀ ,..., SM _{n of} each signal is output from each output terminal. The carry output signal Co is output from the carry output terminal of the adder circuit 10 _n . In this addition device, the addition circuit 10 _0, ..., in 10 _n, the input signal X _0, ..., each bit of X _n, the input signal Y _0, ..., each bit of Y _n, and carry input signal Ci,
C ₀ ,..., C _n−1 are added, and the partial sum SM
_0, ..., SM _n is generated. From the adder circuit 10 _n ,
Carry output signal Co is output. Lowest order addition circuit 1
0 ₀ carry input terminal of is opened, but the adding circuit 1
This is used, for example, when it is desired to add “1” to the addition result at 0 ₀ ,..., 10 _n .

[0004]

However, in the conventional adder circuit of FIG. 2 and the adder of FIG. 3, the two input signals X, Y or X ₀ ,..., X _n , Y _{0 ,.} Only "1" can be added to the addition result. Therefore, when subtracting "1" from the addition result, there is a problem that a separate subtractor needs to be added.

[0005]

According to a first aspect of the present invention, there is provided an adder circuit comprising: a first and a second digit represented by a single digit binary number; An input signal, a carry input signal indicating a lower carry, and a borrow input signal indicating a lower borrow, and when the number of the first logical value of the value indicated by each signal is even, Generating a second logical value obtained by inverting the first logical value as a partial sum;
A partial sum generator for generating the first logical value as the partial sum in the case of an odd number, the first input signal, the second input signal, the carry input signal, and the borrow input signal; Signal, a second input signal, and a carry input signal, two or more of the signals indicate the first logical value and the borrow input signal is the second logical value. A carry generation unit that generates the first logical value as a carry output signal to be indicated, and generates the second logical value in other cases; and inputs the first and second input signals and the borrow input signal. When the first and second input signals are the second logical value and the borrow input signal is the first logical value, the first and second input signals are used as the borrow output signals indicating a borrow to a higher order.
And a borrow generator that generates the second logical value in other cases.

By employing such a configuration, the first and second input signals, the carry input signal, and the borrow input signal are input to the partial sum generation unit, and the first sum of the value indicated by each signal is obtained.
When the number of logical values is an even number, a second logical value is generated as a partial sum, and when the number is an odd number, a first logical value is generated as the partial sum. The first and second input signals, the carry input signal, and the borrow input signal are input to the carry generation unit, and two or more of the first input signal, the second input signal, and the carry input signal are output. When the indicated value is the first logical value and the borrow input signal is the second logical value, the first logical value is generated as the carry output signal; otherwise, the second logical value is generated. The first and second input signals and the borrow input signal are input to a borrow generation unit, and the first and second input signals have a second logical value and the borrow input signal has a first logical value. In this case, a first logical value is generated as a borrow output signal, and in other cases, a second logical value is generated. According to a second aspect of the present invention, there is provided an adder including a plurality of the adder circuits of the first aspect, wherein each of the adder circuits converts a carry input signal indicating a lower carry and a borrow input signal indicating the lower borrow. A carry output signal indicating a carry to a higher order and a borrow output signal indicating a borrow to a higher order are sequentially connected so as to be output to the higher order. By employing such a configuration, the carry input signal and the borrow input signal are input from the lower adder circuit, and the carry output signal and the borrow output signal are output to the upper adder circuit.

According to a third aspect of the present invention, in the adder, first input data represented by an M-digit (where M is a positive integer) binary number is converted to a first control signal by a first control signal. In the case of the logic level, the data is output as the first output data as it is, and in the case where the first control signal is the second logic level complementary to the first logic level, all the digits of the first input data are output. A first inverting means for inverting a first logical value or a second logical value obtained by inverting the first logical value and outputting as the first output data, represented by an M-digit binary number The second input data is output as second output data as it is when the second control signal is at the first logic level, and is output as the second output data when the second control signal is at the second logic level. Inverts the first logical value or the second logical value of all the digits of the second input data to generate the second output data. A second inverting means for outputting as data, and an adding device according to the second invention, wherein the same digit values of the first and second output data are added by respective adding circuits in the adding device, When the carry input signal is the first logical value, a value obtained by adding "1" to the addition result is output as the third output data expressed by an M-digit or (M + 1) -digit binary number. An adder that outputs a value obtained by subtracting “1” from the addition result as the third output data when the signal has the first logical value; and a third control signal that outputs the third output data. In the case of the first logic level, the data is output as fourth output data as it is, and in the case where the third control signal is at the second logic level, the first logic of all the digits of the third output data is output. Inverts the value or the second logical value and outputs the inverted value as the fourth output data 3 of an inverting means, and.

By employing such a configuration, when the first control signal is at the first logical level, the first input data is output as it is as the first output data via the first inverting means. . When the first control signal is at the second logical level, the first input data is inverted by the first inverting means and output as first output data. When the second control signal is at the first logic level, the second input data is output as it is as the second output data via the second inversion means. If the second control signal is at a second logic level, the second
Is inverted by the second inverting means and output as second output data. The same digit value of the first and second output data is added by each adder circuit in the adder, and when the carry input signal is the first logical value, "1" is added to the addition result. The value is output as third output data, and when the borrow input signal is the first logical value, a value obtained by subtracting “1” from the addition result is output as the third output data. When the third control signal is at the first logic level,
The third output data is output as it is as the fourth output data via the third inverting means. When the third control signal is at the second logic level, the third output data is at the third logic level.
And output as fourth output data.

According to a fourth aspect of the present invention, there is provided an adder comprising a plurality of the adder circuits according to the first aspect, wherein each of the adder circuits is provided with a carry input signal indicating a lower carry and a borrow indicating the lower borrow. An adder configured to input the input signal from the lower order, and to sequentially connect a carry output signal indicating a carry to the upper order and a borrow output signal indicating a borrow to the upper order to the upper order, The partial sum output from the highest-order addition circuit of the addition circuits is input, and the borrow input signal of the first logic value is generated only when the partial sum is the first logic value, and And a borrow input signal generating means for supplying the borrow input signal to the lowest-order addition circuit, and a second sum obtained by inputting the partial sum output from the highest-order addition circuit, and the partial sum inverting the first logical value. Key of first logical value only for logical value A carry input signal generating means for generating and supplying a re input signal to the least significant adder circuit includes.

By adopting such a configuration, in each of the adding circuits in the adding section, each of the first input signal, each of the second input signals, each of the carry input signals, each of the carry output signals,
Each borrow input signal and each borrow output signal are added, and each of the addition circuits outputs each partial sum. When the result of addition of each of the first input signals and each of the second input signals is a positive number, the value of the highest partial sum of the partial sums becomes a second logical value, and the carry input A carry input signal of the first logical value is supplied from the signal generating means to the lowest one of the adders. When the addition result of each of the first input signals and each of the second input signals is a negative number, the value of the highest partial sum of the partial sums becomes a first logical value, and the borrow input signal A borrow input signal of a first logical value is supplied from the generation means to the least significant addition circuit. Therefore, in this adder, each of the first
When the addition result of the input signal of each of the above and each second input signal is a positive number, a value obtained by adding "1" to the addition result is calculated. When the addition result is a negative number, " The value obtained by subtracting 1 "is calculated.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a 1-bit addition circuit according to a first embodiment of the present invention. The adder circuit 20 receives the input signals X and Y, the carry input signal Ci and the borrow input signal Bi, and outputs a partial sum SM, and the input signals X and Y, the carry input signal Ci and the borrow input signal Bi. Carry generation unit 22 that receives input signal Bi and outputs carry output signal Co, and borrow generation unit 2 that receives input signals X and Y and borrow input signal Bi and outputs borrow output signal Bo.
3 is comprised. The partial sum generation unit 21 generates one digit 2
A two-input E for inputting input signals X and Y expressed in base notation
The circuit includes an OR circuit 21a and a two-input OR circuit 21b that inputs a carry input signal Ci and a borrow input signal Bi indicating lower-order borrowing. Each output terminal of the EOR circuit 21a and the OR circuit 21b is connected to each input terminal of the two-input EOR circuit 21c, and a partial sum SM of each signal is output from the output terminal of the EOR circuit 21c. I have. The carry generation section 22 includes a two-input OR circuit 22a for inputting the input signals X and Y, a two-input OR circuit 22b for receiving the input signal X and the carry input signal Ci, and a two-input OR circuit 22b for receiving the input signal Y and the carry input signal Ci. 2 input O to input
R circuit 22c. Each OR circuit 22a, 22
Output terminals b and 22c are connected to the positive-phase input terminal of a four-input AND circuit 22d, and a borrow input signal Bi is input to an inverting input terminal of the AND circuit 22d.
The carry output signal Co is output from the 2d output terminal. The borrow generating unit 23 receives the input signals X and Y from the two in-phase input terminals and receives the borrow input signal Bi from the inverting input terminal.
It has an OR circuit 23a. From the output terminal of the NOR circuit 23a, a borrow output signal Bo indicating a borrow to the higher order is output.

FIG. 5 is a diagram for explaining the operation of FIG. The operation of FIG. 1 will be described with reference to FIG. However, the borrow input signal Bi and the carry input signal Ci are not simultaneously set to “1”. The partial sum generation unit 21 receives the input signals X,
Y, the carry input signal Ci and the borrow input signal Bi, and input a first logical value (for example,
When the number of “1”) is even, a second logical value (for example, “0”) is generated as the partial sum SM of each signal, and when the number is odd, “1” is generated as the partial sum SM. . The carry generation unit 22 receives the input signals X and Y, the carry input signal Ci and the borrow input signal Bi, and outputs two or more of the input signal X, the second input signal Y and the carry input signal Ci. When the indicated value is “1” and the borrow input signal Bi is “0”, “1” is generated as the carry output signal Co, and otherwise “0” is generated. The borrow generating unit 23 receives the input signals X and Y and the borrow input signal Bi, and the input signals X and Y are “0” and the borrow input signal Bi is “1”.
In this case, "1" is generated as the borrow output signal Bo, and in other cases, "0" is generated. As described above, this first
In the embodiment, by setting the borrow input signal Bi to “1”, the addition circuit 20 can perform the calculation of X + Y−1 without adding a separate subtractor.

Second Embodiment FIG. 6 is a circuit diagram of a multi-bit adder according to a second embodiment of the present invention. This adder includes a plurality of (n + 1) adder circuits 2 having the same configuration as the adder circuit 20 of FIG.
0 _0, ..., and a 20 _n. These adder circuits 20
_0, ..., 20 _n are connected in cascade to deliver the carry output signal and borrow output signal to the upper and enter the lower carry input signal and the borrow input signal. Addition circuit 2
0 _0, ..., 20 _n input signals X ₀ of the multi-bit to the input terminals of, ..., X _n and the input signal Y _0, ..., each bit of Y _n are respectively input from the output terminals, each partial sum SM ₀ signal, ..., so that the SM _n is outputted.
The carry output terminal and the borrow output terminal of the adder circuit 20 _n output a carry output signal Co and a borrow output signal Bo, respectively.

[0014] In this addition device, the addition circuit 20 _0, ...,
In 20 _n, the input signal X _0, ..., each bit of X _n,
Each bit of input signals Y ₀ ,..., Y _n , carry input signal C
i, the carry output signal _{C 0, ..., C n-} 1, the borrow input signal Bi, and a borrow output signal B _0, ..., addition of B _n-1 is carried out respectively, the partial sum SM _0, ..., is SM _n Generated. The adder 20 _n outputs a carry output signal Co and a borrow output signal Bo. Lowest order addition circuit 10
_Although the carry input terminal of ₀ is open,
_This is used, for example, when it is desired to add “1” to the addition result at ₀ ,..., 10 _n . Further, the borrow input terminal of the adding circuit 10 _0, the addition circuit 10 _0, ..., used or when you want to subtract from the addition result of 10 _n, for example, "1".

As described above, in the second embodiment,
The borrow output signals B ₀ ,..., B _n−1 , Bo are added to the adder 2
0 _0, ..., in 20 _n, because each is generated in a single NOR circuit 23a, the carry output signal C _0, ..., C
_It can be generated faster than _n-1 and Co. These carry output signals C ₀ ,..., C _n−1 , Co and borrow output signal B ₀ ,
, B _n−1 , Bo can be transmitted independently, so that the calculation speed does not decrease by generating the borrow output signals B ₀ ,..., B _{n− 1} , Bo. Therefore, the calculation of X + Y-1 can be performed at a higher speed than the case where the subtractor subtracts "1" after performing the calculation of X + Y as in the conventional adder.

Third Embodiment FIG. 7 is a circuit diagram of a 4-bit adder according to a third embodiment of the present invention. The adder inverts input data X in accordance with the logic level of control signal SX and outputs output data S30 (eg, an inverting circuit).
30 and second inverting means (for example, an inverting circuit) 40 for inverting the input data Y in accordance with the logic level of the control signal SY and outputting the output data S40. The inverting circuit 30 receives the input data X represented by, for example, a 4-digit binary number.
From the input terminal group IN, and the control signal input terminal CTL
Output from the output terminal group OUT as it is as the output data S30 when the control signal SX inputted from the control signal SX is low level (hereinafter referred to as “L”), and when the control signal SX is high level (hereinafter referred to as “H”). Is a circuit for inverting "1" or "0" of all the digits of the input data X and outputting the inverted data as the output data S30. The inverting circuit 40 receives the input data Y represented by, for example, a 4-digit binary number from the input terminal group IN, and outputs the output terminal group as it is when the control signal SY input from the control signal input terminal CTL is “L”. OUT to output as output data S40, and the control signal SY is set to "H".
In the case of “1” or “0” of all digits of the input data Y
And outputs it as the output data S40. Each output terminal group of the inverting circuits 30 and 40 has an adder 5
0 are connected to the respective input terminal groups.

The adder 50 outputs the output data S30, S40
Are added, and when the carry input signal Ci is "1", a value obtained by adding "1" to the addition result is output as output data S50, and when the borrow input signal Bi is "1". Has a function of outputting a value obtained by subtracting "1" from the addition result as output data S50. The input terminal group IN of the third inversion means (for example, an inversion circuit) 60 is connected to the output terminal group of the adder 50. The inverting circuit 60 outputs the output data S50 as output data S60 when the control signal SW is "L", and outputs the output data S5 when the control signal SW is "H".
This is a circuit that inverts “1” or “0” of all digits of 0 and outputs the inverted data as the output data S60.

FIG. 8 is a circuit diagram showing a configuration example of the inverting circuit 30 in FIG. This inverting circuit 30 receives the input data X
Input circuits X ₀ , X ₁ , X ₂ , and X ₃ are input from respective inverting input terminals and a control signal SX is commonly input from respective positive-phase input terminals. AND circuits 31 ₀ , 31 ₁ , 31
₂ and 31 ₃ and a two-input AND circuit 3 for inputting the input signals X ₀ , X ₁ , X ₂ , and X ₃ from the respective positive-phase input terminals and commonly inputting the control signal SX from the respective inverted input terminals.
And a 2 _0, 32 _1, 32 _2, 32 _3. AND
Output terminals of the circuits 31 ₀ , 32 ₀ , AND circuits 31 ₁ ,
32 the output terminals of the _1, the AND circuit 31 _2, 32 ₂ of the output terminals, and the output terminals of the AND circuit 31 _3, 32 _3, 2 inputs of the OR circuit 33 _0, 33 _1, 33 _2, 33 ₃
Are connected to the respective input terminals. OR circuit 33
_0, from 33 _1, 33 _2, 33 ₃ the output terminals of the output signal x _0, x _1, x _2, x ₃ are outputted. The inverting circuit 40 has the same configuration as the inverting circuit 30, receives input signals Y ₀ , Y ₁ , Y ₂ , and Y ₃ of input data Y, and outputs an output signal y in accordance with the logic level of the control signal SY.
_0, y _1, and outputs a y _2, y _3.

FIG. 9 is a circuit diagram showing a configuration example of the adder 50 in FIG. The addition unit 50 is provided by the addition circuit 2 of FIG.
0, five adders 51 ₀ , 51 ₁ , 51
And a _2, 51 _3, 51 _4. These adder circuits 5
1 _0, 51 _1, 51 _2, 51 _3, 51 ₄ are connected in cascade to deliver the carry output signal and borrow output signal to the upper and enter the lower carry input signal and the borrow input signal. Adders 51 ₀ , 51 ₁ , 51 ₂ , 51
Each input terminal of the ₃ is input the output signal _{x 0, x 1, x 2} , x 3 and the output signal _{y 0, y 1, y 2} , y 3 , respectively, each input terminal of the adding circuit 51 ₄ " 0 "is input. Adder circuits 51 ₀ , 51 ₁ , 5
1 _2, 51 _3, 51 partial sum S51 ₀ of the signals from the output terminals of the _{4, S51 1, S51 2,} S51 3, S51 4
Is output.

FIG. 10 is a circuit diagram showing a configuration example of the inverting circuit 60 in FIG. This inverting circuit 60 includes a partial sum S5
_{1 0, S51 1, S51 2} , S51 3, S51 4 the second input of AND circuit 61 ₀ to be input to the common from the positive phase input terminal of the control signal SW with input from the inverting input terminal,
61 _1, 61 _2, 61 _3, 61 _4, said partial sum S5
_{1 0, S51 1, S51 2} , S51 3, S51 4 a 2 input for inputting the control signal SW with inputs from each of the positive-phase input terminal in common from each inverting input terminal AND circuit 6
And a 2 _0, 62 _1, 62 _2, 62 _3, 62 _4. Each output terminal of AND circuits 61 ₀ , 62 ₀ , each output terminal of AND circuits 61 ₁ , 62 ₁ , AND circuits 61 ₂ , 6
The output terminals of the 2 _2, the output terminals of the AND circuit 61 _3, 62 _3, and the output terminals of the AND circuit 61 _4, 62 _4,
Two-input OR circuits 63 ₀ , 63 ₁ , 63 ₂ , 63 ₃ , 6
It is connected to the 3 input terminals of _four. OR circuit 63 _0, 63 _1, 63 _2, 63 _3, 63 ₄ is from the output terminals of each output signal S60 ₀ of the output data S60, S6
_{0 1, S60 2, S60 3} , S60 4 is adapted to be outputted respectively.

Next, calculation examples (1) to (4) in the adder of FIG. 7 will be described. (1) Calculation of X + Y The control signal SX is set to “L”, the control signal SY is set to “L”, the control signal SW is set to “L”, the carry input signal Ci is set to “0”, and the borrow input signal Bi is set to “0”. Input data X and Y are input. Since the control signal SX is "L", the inversion circuit 30 outputs the input data X as it is as the output data S30. Further, since the control signal SY is "L", the inversion circuit 40 outputs the input data Y as it is as the output data S40. Since the carry input signal Ci and the borrow input signal Bi are both “0”, the adder 50 outputs the output data S30, S4
0, that is, the input data X and Y are added, and X + Y is output as output data S50. Since the control signal SW is “L”,
The inversion circuit 60 outputs the output data S50 as it is as the output data S60. That is, X + Y is output as the output data S60.

(2) Calculation of -X + Y The control signal SX is "H", the control signal SY is "L", the control signal SW is "L", the carry input signal Ci is "1", and the borrow input signal Bi is " Input data X and Y are set to "0". Since the control signal SX is “H”, the inverting circuit 30 outputs the inverted data Xb obtained by inverting the input data X to the output data S.
Output as 30. Further, since the control signal SY is "L", the inversion circuit 40 outputs the input data Y as it is as the output data S40. The adder 50 determines that the carry input signal Ci is “1” and the borrow input signal Bi is “0”,
The output data S30 and S40, that is, the inverted data Xb and the input data Y are added, and "1" is added to the addition result.
Therefore, Xb + Y + 1 is output as output data S50. Here, inverting all bits of a certain binary number and adding “1” means taking two's complement, which means inverting the sign. Therefore, Xb + Y + 1
Is -X + Y. Since the control signal SW is "L", the inversion circuit 60 outputs the output data S50 as it is to the output data S.
Output as 60. That is, as the output data S60,
X + Y is output.

(3) Calculation of -XY The control signal SX is "L", the control signal SY is "H", the control signal SW is "L", the carry input signal Ci is "1", and the borrow input signal Bi. Is set to "0" to input the input data X and Y. Since the control signal SX is "L", the inversion circuit 30 outputs the input data X as it is as the output data S30. Further, since the control signal SY is “H”, the inverting circuit 40 outputs the inverted data Yb obtained by inverting the input data Y to the output data S.
Output as 40. The adder 50 outputs the carry input signal C
Since i is "1" and the borrow input signal Bi is "0", the output data S30 and S40, that is, the input data X and the inverted data Yb are added, and "1" is added to the addition result. Therefore, X + Yb + 1 is output as output data S50.
This X + Yb + 1 is XY. Since the control signal SW is "L", the inversion circuit 60 outputs the output data S50 as it is as the output data S60. That is, XY is output as the output data S60.

(4) Calculation of -XY The control signal SX is "L", the control signal SY is "L", the control signal SW is "H", the carry input signal Ci is "0", and the borrow input signal Bi. Is set to "1" and input data X and Y are input. Since the control signal SX is "L", the inversion circuit 30 outputs the input data X as it is as the output data S30. Further, since the control signal SY is "L", the inversion circuit 40 outputs the input data Y as it is as the output data S40. Since the carry input signal Ci is “0” and the borrow input signal Bi is “1”, the adder 50 outputs the output data S30,
S40: Input data X and Y are added, and "-1" is added to the addition result. Therefore, X + Y-1 is output as output data S50. Since the control signal SW is “H”, the inversion circuit 60 inverts all the bits of the output data S50 and outputs the inverted data as the output data S60. That is, the output data S60 is obtained by inverting X + Y-1 (X + Y-1).
b. Here, subtracting "1" from a certain binary number and inverting all bits is also taking 2's complement, so that (X + Y-1) b is obtained by inverting the sign of X + Y. Therefore, -XY is output as the output data S60.

As described above, in the third embodiment,
By appropriately selecting the values of the control signals SX, SY, SW, the carry input signal Ci, and the borrow input signal Bi,
X + Y as input data X and Y as output data S60
-X + Y, XY, and -XY can be calculated with a small circuit. In particular, conventionally, -XY is generated by generating and adding -X, -Y from X, Y using another two or more addition circuits, or by inverting the sign after generating X + Y. However, if the adder according to the present embodiment is used, only one stage of addition is required, so that high-speed calculations can be performed with a small-scale circuit.

Fourth Embodiment FIG. 11 is a circuit diagram of a 4-bit adder according to a fourth embodiment of the present invention. Elements similar to those in FIG. 6 showing the second embodiment are the same as those in FIG. Are denoted by common symbols. This adder has an adder 20A for adding input data X, Y, carry input signal Ci and borrow input signal Bi,
The addition unit 20A adder circuit 20 _0, ..., a 20 _4. Each input terminal of the adding circuit 20 ₄ uppermost,
“0” is input. Adder circuit 20 ₄
The output terminal, the summing circuit 20 ₄ borrow input signal generation means for generating a borrow input signal Bi in response to the partial sum SM ₄ output from (e.g., delay flip-flop, hereinafter referred to this D-FF) 71 (This has become the positive-phase input terminal) of the data input terminal D with is connected, carry input signal generation means for generating a carry input signal Ci in accordance with the partial sum SM ₄ (e.g., D-FF ) 72
(Which is an inverting input terminal) is connected. The output terminal Q of the D-FF 71 borrow input terminal of the least significant adder circuit 20 ₀ is connected,
The output terminal Q of the D-FF 72 carry input terminal of the adding circuit 20 ₀ is connected. A clock ck is commonly input to clock input terminals CK of the D-FFs 71 and 72,
A reset signal RST is commonly input to the reset terminals R of the D-FFs 71 and 72. Others
This is the same configuration as FIG.

[0027] In this addition device, the addition circuit 20 _0, ...,
In 20 _4, each bit of the input data X (i.e., the input signal X _0, ..., X _3, and "0"), each bit of the input data Y (i.e., the input signal Y _0, ..., Y _3, and " 0 ″), carry input signal Ci, carry output signal C ₀ ,
.., C ₃ , borrow input signal Bi, and borrow output signal B
₀ ,..., B ₃ are added, and the addition circuit 2
0 _1, ..., partial sum SM ₁ from 20 _4, ..., SM ₄ is output. When the addition result of the input data X and Y becomes a positive number, the value of the partial sum SM ₄ of the most significant bit becomes “0”,
Output signal of D-FF 72 (that is, carry input signal) Ci
Becomes "1" in synchronization with the clock ck. The carry input signal Ci is input to the carry input terminal of the adding circuit 20 ₀ in the least significant bit. If the result of adding the input data X and Y is a negative number, the value of the partial sum SM ₄ becomes “1” and D
-The output signal Bi of the FF 71 (that is, the borrow input signal) becomes "1" in synchronization with the clock ck. The borrow input signal Bi is input to borrow input terminal of the adding circuit 20 _0. Therefore, in this adder, X + Y + 1 is calculated when X + Y is a positive number, and X + Y is calculated when X + Y is a negative number.
-1 is calculated.

Here, when the input data X and Y are added and the result of the addition is rounded off to the Nth digit (N: integer) from the lowest order, if the addition result is a positive number, the N digits are added. It is sufficient to add +1 to the first digit to make the digit below the Nth digit "0", and if the result of the addition is a negative number, add -1 to the Nth digit and make the digit after the Nth digit "0". In the adder of FIG. 11, input data X, Y
Are added, and the result of dividing this addition result by 2 is rounded off to the nearest whole number to obtain the result of the partial sums SM ₁ ,..., SM ₄ . As described above, in the fourth embodiment, the D-FFs 71 and 72 are connected to the addition unit 20A, and the addition result of the input data X and Y is rounded off by one addition device. The circuit scale can be reduced as compared with the usual rounding method in which two or more adders are required.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) The addition circuit 20 is, for example, an OR circuit 22a, 22
2b and 22c are replaced by AND circuits and AND circuit 22
By replacing d with an OR circuit, another circuit configuration having a similar function may be adopted. (B) Inverting circuits 30, 40, and 60 control signals SX,
Based on SY and SW, input data X and Y and partial sum S5
1 _0, ..., S51 ₄ a may be the circuit configuration that outputs via a buffer or inverter.

[0030]

As described above in detail, according to the first aspect of the present invention, by setting the borrow input signal to the first logical value, the addition circuit can perform the subtraction without adding a separate subtractor. It can be performed. According to the second aspect of the present invention, the borrow output signal of each adder circuit is generated by, for example, one NOR circuit in each adder circuit, so that it can be generated faster than each carry output signal. Since each carry output signal and each borrow output signal can be transmitted independently, generation of each borrow output signal does not reduce the operation speed. Therefore, it is possible to perform the subtraction at a higher speed than when adding the first and second input data and then subtracting "1" by the subtractor as in the conventional adder.

According to the third aspect of the present invention, by appropriately selecting the values of the first, second and third control signals, the carry input signal and the borrow input signal, the first and second input signals are selected. Data addition and subtraction can be calculated at high speed with a small circuit. According to the fourth aspect of the present invention, the borrow input signal generating means and the carry input signal generating means are connected to the adding section, and the addition result of the first and second input data is rounded off to one adding apparatus. Therefore, the circuit scale can be reduced as compared with the usual rounding, which requires two or more adders.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an addition circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional addition circuit.

FIG. 3 is an operation explanatory diagram of FIG. 2;

FIG. 4 is a circuit diagram of a conventional addition device.

FIG. 5 is an operation explanatory diagram of FIG. 1;

FIG. 6 is a circuit diagram of an adding device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of an adding device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of the inverting circuit 30 in FIG. 7;

FIG. 9 is a circuit diagram of an adding unit 50 in FIG. 7;

FIG. 10 is a circuit diagram of the inverting circuit 60 in FIG. 7;

FIG. 11 is a circuit diagram of an adding device according to a fourth embodiment of the present invention.

[Explanation of symbols]

20, 20 _{0 to} 20 _n addition circuit 20A, 50 addition unit 21 partial sum generation unit 22 carry generation unit 23 borrow generation unit 30, 40, 60 inversion circuit 71, 72 D-FF

Claims (4)

[Claims] A first input signal and a second input signal each represented by a single-digit binary number, a carry input signal indicating a lower carry, and a borrow input signal indicating a lower borrow are input. When the number of the first logical value of the value indicated by the signal is even, a second logical value obtained by inverting the first logical value is generated as a partial sum of the signals, and when the number is odd, the partial logical sum is generated as the partial sum. A partial sum generation unit that generates the first logical value, and inputs the first and second input signals, the carry input signal, and the borrow input signal, and outputs the first input signal, the second input signal, When the value indicated by two or more of the carry input signals is the first logical value and the borrow input signal is the second logical value, the carry output signal indicates a carry to a higher order. And a carry generation unit that generates the second logical value in other cases, , A second input signal, and a borrow input signal, and when the first and second input signals are the second logical value and the borrow input signal is the first logical value, A borrow generator that generates the first logical value as a borrow output signal indicating borrowing, and otherwise generates the second logical value. 2. It has a plurality of addition circuits according to claim 1,
Each of the adder circuits receives a carry input signal indicating a lower carry and a borrow input signal indicating the lower borrow from the lower, and indicates a carry output signal indicating a carry for the upper and a borrow for the upper. An adder, wherein the borrow output signals are sequentially connected so as to be output to the higher order. 3. A method according to claim 1, wherein the first control signal is a first input signal represented by M digits (where M is a positive integer) represented by a binary number.
Is output as it is as the first output data in the case of the first logic level, and when the first control signal is in the second logic level complementary to the first logic level, all of the first input data are output. First inverting means for inverting a first logical value of a digit or a second logical value obtained by inverting the first logical value and outputting the inverted value as the first output data, represented by an M-digit binary number When the second control signal is at the first logic level, the second input data
And when the second control signal is at the second logical level, inverts the first logical value or the second logical value of all the digits of the second input data. And a second inverting means for outputting the first and second output data as the second output data.
Are added by respective adders in the adder, and when the carry input signal is the first logical value, a value obtained by adding "1" to the addition result is M digits or (M
+1) is output as third output data represented by a binary number, and when the borrow input signal is a first logical value, a value obtained by subtracting "1" from the addition result is used as the third output data. An adding unit that outputs the third output data as the fourth output data as it is when the third control signal is at the first logic level, and the third control signal is the fourth output data. Third inverting means for inverting the first logical value or the second logical value of all the digits of the third output data in the case of a logical level of 2, and outputting the inverted value as the fourth output data; An addition device comprising: 4. It has a plurality of addition circuits according to claim 1,
Each of the adder circuits receives a carry input signal indicating a lower carry and a borrow input signal indicating the lower borrow from the lower, and indicates a carry output signal indicating a carry for the upper and a borrow for the upper. An adder configured by sequentially connecting borrow output signals to the higher order, and a partial sum output from the highest-order adder circuit of the adder circuits, wherein the partial sum is the first A borrow input signal generating means for generating a borrow input signal of the first logical value and supplying the borrow input signal of the first logical value only to the lowest one of the adding circuits; Enter the partial sum
Carry input signal generating means for generating a carry input signal of a first logical value and supplying the carry input signal to the least significant adder only when the partial sum is a second logical value obtained by inverting the first logical value; An addition device comprising: