JPH11204830A - Manufacture of semiconductor light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen bonding defect and short circuit failure between electrodes in a light emitting diode having a pair of positive and negative electrodes on the same plane, and improve an emitted light intensity. SOLUTION: A light emitting diode 10 has a pair of positive and negative electrodes i.e., electrode 7 of an i-layer 5 and electrode 8 of a high-carrier-concn. n<+> layer 3, an SiO2 insulation layer 9 is formed on a part of the electrode 7 and the entire i-layer 5, so that the exposed areas of the electrodes 7, 8 are approximately equal to thereby approximately equalize the heights of solder bumps 17, 18 formed on the electrodes 7, 8 and lessen the bonding defect of a lead frame 20 of the light emitting diode 10 to lead members 21, 22. By covering near parts of the electrode face to the electrode 8 with the insulation layer 9, the electrode 7 is separated from the electrode 8 to lessen the short circuit failure, the area of the electrode 7 can be possibly large, and hence the light emitting diode 10 can improve the emitted light intensity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor light emitting device having a pair of positive and negative electrodes formed on the same surface.

[0002]

2. Description of the Related Art Heretofore, there has been known a blue light-emitting diode having a pair of positive and negative electrodes on the same surface side using a GaN-based compound semiconductor. The GaN-based compound semiconductor has attracted attention because of its direct transition, which has high luminous efficiency, and that blue, one of the three primary colors of light, is used as the luminescent color. In such a light emitting diode using a GaN-based compound semiconductor, an n-type GaN-based compound semiconductor is grown on a sapphire substrate directly or with a buffer layer made of aluminum nitride interposed therebetween.
A structure in which an i-layer made of an i-type GaN-based compound semiconductor is grown on the n-layer by adding a p-type impurity (Japanese Patent Laid-Open Nos. 62-119196 and 63-1).
88977).

[0003]

Here, it is known that the light emission intensity of the above-described light emitting diode can be improved by increasing the electrode area of the electrode portion of the i layer as much as possible. On the other hand, the electrode portion of the n-layer of the light emitting diode is formed by utilizing the inside of a hole provided in a part of the i-layer, and therefore cannot be as large as the electrode portion of the i-layer. Therefore,
The electrode areas of the i-layer electrode portion and the n-layer electrode portion are formed differently. The height of the solder bumps formed on the pair of positive and negative electrodes had a difference of about several tens of μm. Then, as shown in FIG.
0 is bonded to the lead members 71 and 72 of the lead frame 70, the electrode 68 on the n-layer side
A defect of not being bonded to 0 occurred. Also, even if the light emitting diode 60 is connected to the lead member 7
There is a problem that the optical axis of the light emitting diode 60 is inclined with respect to the lead frame 70 even if the light emitting diode 60 is bonded to the lead frame 70.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. It is an object of the present invention to reduce bonding defects and short-circuit defects between electrodes at the same time, and An object of the present invention is to provide a method for manufacturing a light-emitting diode having extremely high productivity, which is effective for improving the light emission intensity.

[0005]

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor light emitting device having a pair of positive and negative electrodes formed on the same surface, wherein the exposed area of the pair of positive and negative electrodes is reduced. An insulating layer covering the electrode side except for those portions is formed so as to be substantially the same.

[0006]

According to the present invention, an insulating layer is provided so as to cover the electrode side except for those portions so that the exposed areas of the pair of positive and negative electrodes formed on the same surface side are substantially the same.
The apparent area of the pair of positive and negative electrodes of the light emitting diode could be made the same. Thereby, the height of the solder bumps formed on the pair of positive and negative electrodes of the light emitting diode can be made substantially equal. That is, in the light emitting diode, bonding failure in bonding was reduced. Further, the interval between the exposed electrodes of the pair of positive and negative electrodes can be separated by the insulating layer. That is, in the light emitting diode, short-circuit failure between the electrodes at the time of bonding or the like due to adjacent electrodes is reduced. In addition, since the insulating layer exists between the pair of positive and negative electrodes, the electrode area of the electrode related to light emission of the light emitting diode can be increased as much as possible. That is, the light emitting diode was able to improve the light emission intensity.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on specific embodiments.
I will tell. FIG. 1 shows a light emitting diode 10 according to the present invention.
1 (a) is a longitudinal sectional view, and FIG. 1 (b) is a flat view from the electrode side.
FIG. In FIG. 1A, a light emitting diode 10 is shown.
Has a sapphire substrate 1 and a sapphire substrate
A buffer layer 2 of 500 .ANG. AlN is formed on a plate 1.
You. Below the buffer layer 2, a 2.2 μm-thick
High carrier concentration n of GaN ⁺Layer 3 and thickness 1.5μm
Is formed with a low carrier concentration n layer 4 of GaN.
Further, a 0.1 μm-thick
An i layer 5 made of GaN is formed. And i-layer
The electrode 7 made of aluminum connected to the
Rear density n⁺Formed of aluminum connecting to layer 3
An electrode 8 is formed. Further, a part of the electrode 7 and
The entire surface of the i-layer 5 is made of SiO._TwoThe insulating layer 9 made of
I have. After the formation of the insulating layer 9, FIG.
As shown in (b), the positive electrode 7 and the negative electrode 8 are almost the same.
The same area is exposed.

Next, a manufacturing process of the light emitting diode 10 having this structure will be described with reference to FIGS. 2, 3 and 4. FIG. The light emitting diode 10 was manufactured by vapor phase growth using a metal organic compound vapor phase epitaxy method (hereinafter referred to as MOVPE). The gases used were NH ₃ , carrier gas H ₂ and trimethylgallium (Ga (CH ₃ ) ₃ ) (hereinafter referred to as TM
G) and trimethylaluminum (Al (CH ₃ ) ₃ )
(Hereinafter referred to as TMA), silane (SiH ₄ ), and diethylzinc (hereinafter referred to as DEZ). First, a single-crystal sapphire substrate 1 having an a-plane as a main surface cleaned by organic cleaning and heat treatment is mounted on a susceptor placed in a reaction chamber of a MOVPE apparatus. Next, the sapphire substrate 1 was subjected to gas phase etching at a temperature of 1100 ° C. while flowing H ₂ into the reaction chamber at a flow rate of 2 l / min at normal pressure. Next, the temperature was lowered to 400 ° C., H ₂ was 20 l / min, NH ₃ was 10 l / min, and TMA was 1.8 l / min.
A buffer layer 2 made of AlN having a thickness of 500 ° was formed by supplying at a rate of × 10 ^-5 mol / min. Next, the temperature of the sapphire substrate 1 was maintained at 1150 ° C., H ₂ was 20 l / min, and NH ₃ was 10 l / min.
/ Min, 1.7 × 10 ^-4 mol / min of TMG and silane (SiH ₄ ) diluted to 0.86 ppm with H ₂ at a rate of 200 ml / min for 30 minutes to give a film thickness of 2.2 μm and a carrier concentration of 1.5 × 10 ¹⁸ /cm
^A high carrier concentration n.sup. ⁺ Layer 3 of ³ GaN was formed. Subsequently, the temperature of the sapphire substrate 1 was maintained at 1150 ° C., H ₂ was 20 l / min, NH ₃ was 10 l / min, and TMG was 1.7 l / min.
X 10 ^-4 mol / min at a rate of 20 minutes to give
A low carrier concentration n layer 4 made of GaN having a carrier concentration of 1 × 10 ¹⁵ / cm ³ was formed. Next, sapphire substrate 1
H ₂ O, 20 l / min, NH ₃ 10 l / min, TM
G was supplied at a rate of 1.7 × 10 ^-4 mol / min and DEZ was supplied at a rate of 1.5 × 10 ^-4 mol / min for 1 minute to form a 0.1 μm-thick GaN layer i. Thus, a multilayer structure as shown in FIG. 2A was obtained. Next, as shown in FIG. 2B, the SiO ₂ layer 11 is formed on the i-layer 5 by sputtering.
Was formed to a thickness of 2000 mm. Next, a photoresist 12 is applied on the SiO ₂ layer 11, and the photoresist 12 is subjected to high carrier concentration n ⁺ by photolithography.
The pattern was formed by removing the photoresist at the electrode formation site for layer 3. Next, as shown in FIG. 2C, the SiO ₂ layer 11 not covered with the photoresist 12 is formed.
Was removed with a hydrofluoric acid-based etchant.

Next, as shown in FIG. 3 (d), the i-layer 5 at a portion not covered by the photoresist 12 and the SiO ₂ layer 11, the low carrier concentration n-layer 4 thereunder and the high carrier concentration n ⁺ A part of the upper surface of the layer 3 was dry-etched by supplying a BCl ₃ gas at a rate of 10 ml / min with a vacuum degree of 0.04 Torr, high-frequency power of 0.44 W / cm ² , and then dry etching with Ar.
Next, as shown in FIG.
The SiO ₂ layer 11 was removed with hydrofluoric acid. Next, as shown in FIG. 3 (f), an Al layer 13 was deposited on the entire surface of the sample by evaporation to a thickness of 0.3 mm.
It was formed to a thickness of μm. Then, a photoresist 14 is applied on the Al layer 13, and the photoresist 14 is patterned into a predetermined shape by photolithography such that the electrode portions for the high carrier concentration n ⁺ layer 3 and the i layer 5 remain. did.

Next, as shown in FIG. 4 (g), the exposed portion of the lower Al layer 13 is etched with a nitric acid-based etchant using the photoresist 14 as a mask.
Was removed with acetone to form an electrode 8 of the high carrier concentration n ⁺ layer 3 and an electrode 7 of the i layer 5. Next, as shown in FIG. 4 (h), on the entire surface of the sample, SiO ₂ by a sputtering
Layer 15 was formed to a thickness of 200 °. Next, as shown in FIG. 4 (i), a photoresist 16 is applied on the SiO ₂ layer 15 and the photoresist 16 is applied by photolithography to the electrode 8 of the high carrier concentration n ⁺ layer 3 and the i layer 5. The electrode 7 was formed in a pattern in which the photoresist at the electrode formation site for a part of the electrode 7 was removed. It should be noted that the electrode areas of the electrode 8 of the high carrier concentration n ⁺ layer 3 and the electrode 7 of the i layer 5 in FIGS.

After the above manufacturing steps, the photoresist 16
The SiO ₂ layer 15 that is not covered with the SiO ₂ layer is removed with a hydrofluoric acid-based etchant, and a portion of the electrode 7 and the SiO ₂ layer
The insulating layer 9 made of was formed. Thus, the gallium nitride-based light emitting device having the MIS (Metal Insulator Semiconductor) structure shown in FIG. 1 can be manufactured.
In addition, as an insulating material for forming the insulating layer 9,
In addition to SiO _2, an insulating material made of Al ₂ O ₃ , Si ₃ N ₄ or TiN may be selected.

The solder bumps 17 and 18 are formed on the electrodes 7 and 8 of the light emitting diode 10 manufactured as described above. Then, since the exposed areas of the electrodes 7 and 8 are substantially the same, the solder bumps 17 and 18 have substantially the same solder bump height. Therefore, the electrodes 7 and 8 of the light emitting diode 10 are connected to the solder bumps 17 and 18 as shown in FIG.
To the lead members 21 and 22 of the lead frame 20 via the same conditions. That is, it is possible to eliminate a bonding defect such that one of the electrodes 7 and 8 of the light emitting diode 10 is not bonded to the lead members 21 and 22 of the lead frame 20 due to a difference in solder bump height. Further, as described above, even if the electrode area of the i-layer 5 of the light emitting diode 10 on the electrode 7 side is made as large as possible, the portion of the electrode 7 close to the electrode 8 is covered with the insulating layer 9 as shown in FIG. Thus, the exposed surfaces of the electrode 7 and the electrode 8 can be separated. That is, the solder bumps 17 and 18 of the electrodes 7 and 8 can be formed as far apart as possible. Therefore, a short circuit between the electrode 7 of the i layer 5 of the light emitting diode 10 and the electrode 8 of the high carrier concentration n ⁺ layer 3 can be eliminated. Furthermore, the electrode 7 of the i layer 5 of the light emitting diode 10 and the electrode 8 of the high carrier concentration n ⁺ layer 3 are insulated by the insulating layer 9, and the electrode area on the electrode 7 side of the i layer 5 should be as large as possible. Therefore, the light emission intensity of the light emitting diode 10 can be improved. As described above, in the light emitting diode of the present invention, a reduction in the defective rate and an increase in performance are achieved, and the productivity is dramatically improved.

[Brief description of the drawings]

FIG. 1 is a schematic view illustrating a light emitting diode manufactured according to one embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing a manufacturing process of the light emitting diode according to the embodiment.

FIG. 3 is a vertical sectional view showing a manufacturing step of the light emitting diode according to the embodiment, following FIG. 2;

FIG. 4 is a longitudinal sectional view showing a manufacturing process of the light emitting diode according to the embodiment, following FIG. 3;

FIG. 5 is a partial longitudinal sectional view showing a joint state between the light emitting diode and the lead frame according to the embodiment.

FIG. 6 is a partial vertical cross-sectional view showing a state of joining a conventional light emitting diode and a lead frame.

[Description of Signs] 1-Sapphire substrate 2-Buffer layer 3-High carrier concentration n ⁺ layer 4-Low carrier concentration n-layer 5-i layer 7,8-electrode 10-Light emitting diode

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor light emitting device in which a pair of positive and negative electrodes are formed on the same surface side, wherein the pair of positive and negative electrodes has an exposed area except for those portions so that the exposed areas thereof are substantially the same. A method for manufacturing a semiconductor light emitting device, comprising forming an insulating layer to cover.