JPH11204571A - Mounting structure of functional element and manufacture thereof - Google Patents

Mounting structure of functional element and manufacture thereof

Info

Publication number
JPH11204571A
JPH11204571A JP10002964A JP296498A JPH11204571A JP H11204571 A JPH11204571 A JP H11204571A JP 10002964 A JP10002964 A JP 10002964A JP 296498 A JP296498 A JP 296498A JP H11204571 A JPH11204571 A JP H11204571A
Authority
JP
Japan
Prior art keywords
resin
circuit board
mounting structure
sealing resin
electrode forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10002964A
Other languages
Japanese (ja)
Other versions
JP3273556B2 (en
Inventor
Kazuyoshi Amami
和由 天見
Tsukasa Shiraishi
司 白石
Yoshihiro Bessho
芳宏 別所
Yoshitake Hayashi
林  祥剛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP00296498A priority Critical patent/JP3273556B2/en
Publication of JPH11204571A publication Critical patent/JPH11204571A/en
Application granted granted Critical
Publication of JP3273556B2 publication Critical patent/JP3273556B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • H01L2224/29007Layer connector smaller than the underlying bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting and manufacturing method dealing with warpage deformation of a circuit board regarding a mounting structure which is composed of a semiconductor device mounted on the circuit board. SOLUTION: In a gap between a semiconductor device and circuit board 3 on a part of its planar region, a hardening-shrinkable resin 5 which has a high shrinkage at hardening and is different from an encapsulating resin 4 in rapid hardening property is applied as spots, and the encapsulating resin 4 is filled in the gap to form a mounting structure. If the circuit board warps, connections between all electrodes on both electrode forming planes are ensured and by the shrinkage of the hardening-shrinkable resin 5 and integrated by the encapsulating resin 4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、集積回路チップ等
の半導体装置、その他の機能素子を回路基板にフリップ
チップ実装した実装構造体とその製造方法に関するもの
である。
[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device such as an integrated circuit chip, and a mounting structure in which other functional elements are flip-chip mounted on a circuit board, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来、機能素子、特に集積回路チップ等
素子基板上に集積回路等の機能部を一体に形成したよう
な半導体装置は、別体の回路基板上に配設して、半導体
装置の素子基板と回路基板との双方の電極形成面に形成
された入出力端子電極同士を接続して、半導体装置の実
装構造体として使用に供されるが、この実装法では、従
来から、電極同士のはんだ付けを用いたワイヤボンディ
ング方法がよく利用されてきた。 しかし、 近年に至り、
半導体装置を含む実装体即ちパッケージ全体の小型化と
接続端子数の増加が要求され、これに伴い、接続端子電
極の相互の間隔が非常に狭くなり、 従来のはんだ付け技
術では対処することが次第に困難になってきた。
2. Description of the Related Art Conventionally, a semiconductor device in which a functional element, in particular, a functional portion such as an integrated circuit is integrally formed on an element substrate such as an integrated circuit chip, is arranged on a separate circuit board, and The input / output terminal electrodes formed on both the electrode forming surfaces of the element substrate and the circuit board are connected to each other to be used as a mounting structure of a semiconductor device. A wire bonding method using soldering has been widely used. However, in recent years,
It is required to reduce the size of the package including the semiconductor device, that is, the entire package, and increase the number of connection terminals. With this, the interval between the connection terminal electrodes becomes very narrow, and it is increasingly difficult to deal with the conventional soldering technology. It has become difficult.

【0003】そこで、 最近では集積回路チップ等の半導
体装置を回路基板の入出力端子電極上に直接に接続する
ことにより、 電極形成面積を小型化して効率的使用を図
ろうとする方法が提案されてきた。 なかでも、半導体装置を回路基板にフェイスダウン状態
でフリップチップ実装する方法は、半導体装置と回路基
板との電気的接続が一括してできること、および接続後
の機械的強度が強いことから有用な方法であるとされて
いる。
Accordingly, recently, a method has been proposed in which a semiconductor device such as an integrated circuit chip is directly connected to input / output terminal electrodes of a circuit board to reduce the area for forming electrodes and achieve efficient use. Was. Among them, a method of flip-chip mounting a semiconductor device on a circuit board in a face-down state is a useful method because the electrical connection between the semiconductor device and the circuit board can be made at once and the mechanical strength after connection is strong. It is supposed to be.

【0004】フリップチップ実装法には、例えば、日本
マイクロエレクトロニクス協会編、「IC化実装技術」
(工業調査会、1980年1 月15日発行)には、はんだメッ
キ法を用いた実装方法が開示されている。この実装方法
を以下に説明すると、図3(A)は従来の半導体装置の
はんだバンプの概略断面図を、図3(B)は、半導体装
置の実装構造体の概略断面図を、それぞれ示すが、この
図において、素子基板であるIC基板1の電極パッド8
を、図3に示す回路基板3の入出力端子電極7に接続す
る場合に、まずIC基板1の電極パッド8上に密着金属
膜9および拡散防止金属膜10を蒸着法によって形成
し、さらにこの上に、はんだ合金からなる電気的接続接
点(以下、はんだバンプという)22をメッキ法により
形成する。次に、このようにして形成された半導体装置
を、図3に示されるようにフェイスダウン状態で、はん
だバンプ22が入出力端子電極7上に当接するように位
置合わせを行い、回路基板3上に載置する。その後、こ
の半導体装置の実装構造体を、はんだ溶融温度以上に加
熱することにより、はんだバンプ22を回路基板3の入
出力端子電極7に融着していた。
[0004] Flip chip mounting methods include, for example, “IC mounting technology” edited by the Japan Microelectronics Association.
(Industry Research Council, published on January 15, 1980) discloses a mounting method using a solder plating method. This mounting method will be described below. FIG. 3A is a schematic cross-sectional view of a solder bump of a conventional semiconductor device, and FIG. 3B is a schematic cross-sectional view of a mounting structure of the semiconductor device. In this figure, an electrode pad 8 of an IC substrate 1 which is an element substrate
Is connected to the input / output terminal electrodes 7 of the circuit board 3 shown in FIG. 3, first, an adhesion metal film 9 and a diffusion prevention metal film 10 are formed on the electrode pads 8 of the IC substrate 1 by a vapor deposition method. An electrical connection contact (hereinafter, referred to as a solder bump) 22 made of a solder alloy is formed thereon by a plating method. Next, the semiconductor device thus formed is positioned in a face-down state as shown in FIG. 3 such that the solder bumps 22 are in contact with the input / output terminal electrodes 7 and the semiconductor device is positioned on the circuit board 3. Place on. Thereafter, the mounting structure of the semiconductor device was heated to a temperature equal to or higher than the solder melting temperature, so that the solder bumps 22 were fused to the input / output terminal electrodes 7 of the circuit board 3.

【0005】また、最近のフリップチップ実装法には、
図4に導電性接着剤を用いた実装構造体の概略断面図に
示すように、IC基板1の電極パッド8上にワイヤボン
ディング法またはメッキ法により電気的接続接点(Au
バンプ)23を形成し、このAuバンプ23を導電性接
着剤(接合層)6を介して回路基板3の入出力端子電極
7に接続するような半導体装置の実装構造体も提案され
ている。このような半導体装置の実装構造体において
は、IC基板1のAuバンプ23に導電性接着剤6を転
写してから、回路基板3の入出力端子電極7にAuバン
プ23が当接するように位置合わせをし、導電性接着剤
6を硬化させて電気的接続を得ていた。
[0005] Recent flip chip mounting methods include:
As shown in a schematic cross-sectional view of the mounting structure using the conductive adhesive in FIG. 4, an electrical connection contact (Au) is formed on the electrode pad 8 of the IC substrate 1 by a wire bonding method or a plating method.
A mounting structure of a semiconductor device in which a bump (bump) 23 is formed and the Au bump 23 is connected to the input / output terminal electrode 7 of the circuit board 3 via a conductive adhesive (bonding layer) 6 has also been proposed. In such a mounting structure of a semiconductor device, the conductive adhesive 6 is transferred to the Au bumps 23 of the IC substrate 1 and then the Au bumps 23 are brought into contact with the input / output terminal electrodes 7 of the circuit board 3. After the alignment, the conductive adhesive 6 was cured to obtain an electrical connection.

【0006】さらに、電極間の導電性接着剤6の電気的
接続をさらに補強するために、IC基板1と回路基板3
との間隙を封止樹脂4で封止して接着した半導体装置の
実装構造体9も提案されている。この実装構造体の製造
方法においては、電極7、8間の接続に加えて、さらに
封止樹脂4による間隙31の充填封止とその硬化の工程
が設けられていた。
Further, in order to further reinforce the electrical connection of the conductive adhesive 6 between the electrodes, the IC substrate 1 and the circuit substrate 3
There is also proposed a semiconductor device mounting structure 9 in which a gap between the semiconductor device and the semiconductor device is sealed with a sealing resin 4 and bonded. In the method of manufacturing the mounting structure, in addition to the connection between the electrodes 7 and 8, a process of filling and sealing the gap 31 with the sealing resin 4 and curing the same is provided.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、半導体
装置を回路基板にフェイスダウン状態で行う上記従来の
のフリップチップ実装方法においては、半導体装置実装
前の回路基板に反り等の変形があって平坦度が得られな
いと、半導体装置を回路基板との電極の一部に接触不良
を生じ易く、さらに回路基板に合成樹脂成形体を利用す
る場合には、基板に反りが発生ないし残留することは避
けられず、半導体部品に電極間導通不良による不良品が
発生することがあった。このような回路基板の反りに伴
う電極間導通不良は、電極密度の上昇に伴い特に発生頻
度が高くなっていた。
However, in the above-described conventional flip-chip mounting method of mounting a semiconductor device on a circuit board in a face-down state, the flatness of the circuit board before mounting the semiconductor device due to deformation such as warpage. If the semiconductor device is not obtained, it is easy for the semiconductor device to have poor contact with some of the electrodes with the circuit board, and when using a synthetic resin molded body for the circuit board, it is necessary to avoid warping or remaining of the board. In some cases, defective products due to poor inter-electrode continuity occur in semiconductor components. Such inter-electrode conduction failure due to the warpage of the circuit board has been particularly frequent with an increase in electrode density.

【0008】さらに、電極間の電気的接続を確実に確保
するためには、さらに、封止樹脂が、電極形成面の間隙
に完全に充足して強固に接合する必要があり、電極形成
面の間隙への浸透充填は、表面張力を利用したものであ
り、この点で、封止樹脂の流動性を確保すること、従っ
て、樹脂の粘度を狭い範囲に調製することなど、封止樹
脂の材料特性を厳密に管理しなければならないといった
問題もあった。
Furthermore, in order to ensure the electrical connection between the electrodes, it is necessary that the sealing resin completely fills the gap between the electrode forming surfaces and is firmly joined. Infiltration filling into the gaps utilizes surface tension, and in this regard, it is necessary to secure the fluidity of the sealing resin, and therefore, to adjust the viscosity of the resin to a narrow range, for example. There was also a problem that characteristics had to be strictly managed.

【0009】本発明は、上記問題に鑑み、回路基板の反
りの存在に起因した電極間導通不良を完全に防止するた
めの実装方法を提供しようとするものである。本発明
は、また、回路基板に反り変形があってもこれに充分対
処し得る実装構造体を提供するものである。本発明は、
さらに、封止樹脂の充填に必要な粘度範囲を広げてフリ
ップチップ実装構造体を製造するに際して使用する材料
特性の管理を緩和ないし軽減することを目的とするもの
である。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a mounting method for completely preventing a failure in conduction between electrodes due to the presence of warpage of a circuit board. Another object of the present invention is to provide a mounting structure capable of sufficiently coping with a warp deformation of a circuit board. The present invention
It is still another object of the present invention to widen the range of viscosity required for filling the sealing resin and to ease or reduce the management of material properties used in manufacturing a flip chip mounting structure.

【0010】[0010]

【課題を解決するための手段】本発明の機能素子の実装
構造体は、素子基板を含む機能素子を回路基板にフリッ
プチップ実装して成るものであって、上記機能素子の素
子基板と上記回路基板間との相対向する電極形成面間の
間隙に、電極形成面の面域の一部を接合する硬化収縮性
樹脂と、該面域の残部の間隙に充填する封止樹脂とを有
するものである。
According to the present invention, there is provided a mounting structure for a functional element, wherein a functional element including an element substrate is flip-chip mounted on a circuit board. In a gap between the electrode forming surfaces opposed to each other between the substrates, a curing shrinkable resin that joins a part of the surface area of the electrode forming surface, and a sealing resin that fills a gap in the remaining part of the surface area. It is.

【0011】本発明の実装構造体の製造方法は、実装構
造体に形成する機能素子の素子基板と回路基板との電極
形成面同士を、封止樹脂によって充填するに先立って、
硬化収縮性樹脂により電極形成面の面域の一部について
だけ接着硬化させ、次いで、電極形成面の残部の面域に
つき封止樹脂により電極形成面間隙に充填して硬化させ
るものである。
In the method of manufacturing a mounting structure according to the present invention, before filling the electrode forming surfaces of the element substrate and the circuit board of the functional element formed on the mounting structure with a sealing resin,
The adhesive shrinkable resin is used to bond and cure only a part of the surface area of the electrode forming surface, and then the remaining surface area of the electrode forming surface is filled with the sealing resin into the electrode forming surface gap and cured.

【0012】本発明において、硬化収縮性樹脂により部
分的に電極形成面同士を接着させると、硬化収縮性樹脂
の硬化の過程で樹脂の収縮が生じ、これにより接着され
た電極形成面間に引張応力を発生させるので、回路基板
に反りがあっても、半導体装置と回路基板との両電極形
成面の全ての電極を接触させるのである。これにより、
電極の接続は、導電性接着剤による接着、又は、はんだ
バンプによる接着いずれも容易確実となる。
In the present invention, when the electrode forming surfaces are partially adhered to each other by the curing shrinkable resin, the resin shrinks in the course of curing of the curing shrinkable resin, whereby a tensile force is applied between the bonded electrode forming surfaces. Since the stress is generated, even if the circuit board is warped, all the electrodes on both the electrode forming surfaces of the semiconductor device and the circuit board are brought into contact. This allows
The connection of the electrodes can be easily and surely performed by bonding using a conductive adhesive or bonding using solder bumps.

【0013】このように、硬化収縮性樹脂により電極同
士の接触状態を保持して、後に充填した封止樹脂の硬化
により半導体装置と回路基板とが完全に固定される。こ
れにより、半導体装置実装前の回路基板に反りがあって
も電極間の導通を完全に確保する。
In this manner, the contact state between the electrodes is maintained by the curing shrinkable resin, and the semiconductor device and the circuit board are completely fixed by the curing of the sealing resin filled later. Thereby, even if the circuit board before mounting the semiconductor device is warped, conduction between the electrodes is completely ensured.

【0014】本発明は、硬化収縮性樹脂の硬化収縮作用
を利用するので、回路基板は、その反りないしは平坦度
の許容範囲を広くすることができ、回路基板の管理条件
を緩和でき、さらに、封止樹脂の充填面域も減ずるので
その間隙への樹脂の充足が容易であり、封止樹脂の粘度
特性ないし充填性等の材料特性に関する管理条件を緩和
することを可能とする。
Since the present invention utilizes the curing shrinkage effect of the curing shrinkable resin, the circuit board can have a wide allowable range of warpage or flatness, can ease the management conditions of the circuit board, and Since the filling surface area of the sealing resin is also reduced, it is easy to fill the gap with the resin, and it is possible to relax the management conditions relating to the material properties such as the viscosity property and the filling property of the sealing resin.

【0015】また、本発明の実装構造体の製造方法は、
封止樹脂を充填する際に、半導体装置と回路基板間の封
止樹脂の充填された隙間内部と封止樹脂の外部との間に
気圧差を設けることにより、外圧によって封止樹脂の隙
間内部への浸透を促進して充足を完全にするものであ
る。これにより、使用する封止樹脂は充足容易となる粘
度範囲を大きくすることができるので、封止樹脂の許容
粘度に関する管理条件を緩和することを可能とする。
Further, a method for manufacturing a mounting structure according to the present invention includes:
When filling the sealing resin, by providing a pressure difference between the inside of the gap filled with the sealing resin between the semiconductor device and the circuit board and the outside of the sealing resin, the inside of the gap of the sealing resin due to external pressure It promotes infiltration and completes sufficiency. Thereby, the viscosity range in which the sealing resin to be used can easily be satisfied can be widened, so that the management condition regarding the allowable viscosity of the sealing resin can be relaxed.

【0016】上記機能素子には、半導体装置、振動素
子、弾性表面波振動素子などを含み、素子基板と該素子
基板上に形成された機能部と、該基板の機能部側の表面
ないし反対面に形成された多数の電極を有するような素
子に広く適用することができ、上記半導体装置には、半
導体集積回路素子や、混成集積回路を広く含むことがで
きる。
The functional element includes a semiconductor device, a vibrating element, a surface acoustic wave vibrating element, and the like, and includes an element substrate, a functional portion formed on the element substrate, and a surface of the substrate on the functional portion side or an opposite surface. The present invention can be widely applied to an element having a large number of electrodes formed in a semiconductor device, and the semiconductor device can widely include a semiconductor integrated circuit element and a hybrid integrated circuit.

【0017】[0017]

【発明の実施形態】本発明の実施形態では、機能素子と
して半導体集積回路の半導体装置を使用して、回路基板
として合成樹脂基板を使用した例について、図面を用い
て以下に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiments of the present invention, an example in which a semiconductor device of a semiconductor integrated circuit is used as a functional element and a synthetic resin substrate is used as a circuit board will be described below with reference to the drawings.

【0018】図1(A)は、本発明の一実施形態である
半導体装置の素子基板1と回路基板3との電極形成面1
0、30の間隙を封止樹脂4と硬化収縮性樹脂5とによ
り接続し実装構造体9の概略断面図を示す。
FIG. 1A shows an electrode forming surface 1 of an element substrate 1 and a circuit substrate 3 of a semiconductor device according to an embodiment of the present invention.
A schematic cross-sectional view of a mounting structure 9 in which gaps 0 and 30 are connected by a sealing resin 4 and a curing shrinkable resin 5 is shown.

【0019】半導体装置には、その素子基板、即ちIC
基板(チップ)1には、その電極形成面10の端子電極
8上に公知の方法により電気的接続点(バンプ電極)2
が形成されており、上記半導体装置が搭載される回路基
板3にも、その電極形成面30に、チップ側の端子電極
8に対応した端子電極7が形成されている。
In a semiconductor device, its element substrate, ie, IC
The substrate (chip) 1 has an electrical connection point (bump electrode) 2 on the terminal electrode 8 on the electrode forming surface 10 by a known method.
The terminal electrodes 7 corresponding to the chip-side terminal electrodes 8 are also formed on the electrode forming surface 30 of the circuit board 3 on which the semiconductor device is mounted.

【0020】回路基板3上に搭載した半導体装置は、両
電極形成面10、30を対面させて、半導体装置の素子
基板1のバンプ電極2の先端が、回路基板3の端子電極
7面に導電性接着剤により接着され、対面した電極形成
面間の間隙31には、いずれも絶縁性である硬化収縮性
樹脂と封止樹脂とが充填されて電極形成面間を接合して
いる。
In the semiconductor device mounted on the circuit board 3, the front ends of the bump electrodes 2 of the element substrate 1 of the semiconductor device are electrically connected to the terminal electrodes 7 of the circuit board 3 with both electrode forming surfaces 10 and 30 facing each other. The gaps 31 between the electrode forming surfaces which are adhered and face each other with a conductive adhesive are filled with a hardening / shrinkable resin and a sealing resin, both of which are insulative, thereby joining the electrode forming surfaces.

【0021】具体的に、図1(B)に示すように、硬化
収縮性樹脂5は、両電極形成面10、30のいずれか、
例えば、回路基板3の電極形成面30の面域内にスポッ
ト状に盛り付けられて、次いで、半導体装置と回路基板
とを各電極7、8が対応するように位置づけして、両電
極形成面10、30間をその硬化収縮性樹脂5により接
合する。回路基板に反りがあって、未接触の電極7a、
8aがあっても(図1(B))も、硬化収縮性樹脂5の
硬化収縮過程で、電極7a、8aは接触し、次いで導電
性接着剤6の硬化により、確実に接続される。封止樹脂
4は、両電極形成面の面域内の硬化収縮性樹脂以外の全
領域の間隙31に充填されて緻密な硬化体を形成して一
体化され、実装構造体にされる。
More specifically, as shown in FIG. 1 (B), the curable shrinkable resin 5 is provided on one of the electrode forming surfaces 10 and 30,
For example, the semiconductor device and the circuit board are positioned so that the electrodes 7 and 8 correspond to each other in a spot shape within the surface area of the electrode forming surface 30 of the circuit board 3. 30 are joined by the curing shrinkable resin 5. A non-contact electrode 7a having a warped circuit board;
Even if there is 8a (FIG. 1 (B)), the electrodes 7a and 8a come into contact during the curing and shrinking process of the curing and shrinkable resin 5, and then the conductive adhesive 6 is hardened to be surely connected. The sealing resin 4 is filled in the gaps 31 in the entire area other than the hardening and shrinkable resin in the surface area of both electrode forming surfaces, forms a dense cured body, and is integrated to form a mounting structure.

【0022】本発明で使用される硬化収縮性樹脂と封止
樹脂とは、いずれも熱硬化性樹脂であるが、硬化収縮性
樹脂5は封止樹脂6に対して、液状から硬化し硬化が進
行する際の体積収縮率の大きい樹脂が使用される。硬化
収縮性樹脂は、硬化の際の収縮により、素子基板と回路
基板とを引っ張る作用を付与する。さらに、硬化収縮性
樹脂5は、いずれかの電極形成面10、30上にスポッ
ト状に盛り付けてそのまま自立姿勢が保持できるよう
に、高い粘度でチクソトロピー性の大きい特性が好まし
い。自立性があるので、一方の基板への盛り付けによ
り、素子基板と回路基板との両方を接着することができ
る。硬化収縮性樹脂は、また、速硬性があるのが好まし
い。
Although the curing shrinkable resin and the sealing resin used in the present invention are both thermosetting resins, the curing shrinkable resin 5 is cured from the liquid state with respect to the sealing resin 6 by curing. A resin having a large volume shrinkage ratio when the resin is advanced is used. The curing shrinkable resin imparts an action of pulling the element substrate and the circuit board by contraction at the time of curing. Further, the curing shrinkable resin 5 preferably has characteristics of high viscosity and high thixotropy so that the curing shrinkable resin 5 can be mounted on any one of the electrode forming surfaces 10 and 30 in a spot shape and can maintain a self-standing posture. Since it is self-supporting, it is possible to bond both the element substrate and the circuit substrate by laying it on one substrate. It is preferable that the curing shrinkable resin also has fast curing properties.

【0023】他方の封止樹脂は、収縮率の比較的小さい
樹脂から選ばれる。さらに、封止樹脂は、半導体装置と
回路基板との両電極形成面10、30の間の狭い間隙3
1に表面張力により速やかに浸透して充足し得る程度に
低粘度であって且つ流動性が高く、回路基板や素子基板
に対して濡れ性の大きい樹脂が好ましい。
The other sealing resin is selected from resins having a relatively small shrinkage. Further, the sealing resin forms a narrow gap 3 between the electrode forming surfaces 10 and 30 of the semiconductor device and the circuit board.
It is preferable to use a resin which has a low viscosity and high fluidity to the extent that it can be quickly penetrated by the surface tension to be satisfied, and has a high wettability to a circuit board or an element substrate.

【0024】尤も、その他の点では、硬化収縮性樹脂と
封止樹脂とは共通の特性を有するものが好ましい。即
ち、いずれの樹脂も、電気的高絶縁性で高周波特性がよ
く、接着強度が大きく、好ましくは熱伝導度が大きく、
硬化体の熱膨張係数が小さい特性を有するものから選ば
れる。
However, in other respects, it is preferable that the curing shrinkable resin and the sealing resin have common characteristics. That is, any resin has high electrical insulating properties and good high-frequency characteristics, high adhesive strength, preferably high thermal conductivity,
It is selected from those having the characteristic that the thermal expansion coefficient of the cured product is small.

【0025】このような硬化収縮性樹脂には、エポキシ
系、アクリル系又はフェノール系の熱硬化性樹脂や紫外
線硬化性樹脂等が利用可能である。他方の封止樹脂に
は、エポキシ系又はフェノール系樹脂等が利用可能であ
る。
As such a curing shrinkable resin, an epoxy-based, acrylic-based or phenol-based thermosetting resin, an ultraviolet-setting resin, or the like can be used. As the other sealing resin, an epoxy-based resin or a phenol-based resin can be used.

【0026】硬化収縮性樹脂は、例えば、封止樹脂と同
様のエポキシ系接着剤組成物から選ぶこともでき、これ
により硬化収縮性樹脂と封止樹脂との相互結合が確実に
なる。
The curing shrinkable resin can be selected, for example, from the same epoxy-based adhesive composition as the sealing resin, whereby the mutual bonding between the curing shrinkable resin and the sealing resin is ensured.

【0027】また、図2に示すように、上記硬化収縮性
樹脂5による接続領域を少なくとも電極形成面10、3
0の面域上に少なくとも2個所設けることにより、封止
樹脂の充填後に硬化させる際には既に硬化物になってい
る硬化収縮性樹脂に発生する応力を分散することが可能
となり、応力を分散させることは、素子基板や回路基板
への応力集中を防ぐと言う利点がある。
As shown in FIG. 2, the connection region formed by the curing and shrinkable resin 5 is formed at least on the electrode forming surfaces 10 and 3.
By providing at least two portions on the surface area of 0, when curing after filling the sealing resin, it is possible to disperse the stress generated in the cured shrinkable resin which has already been cured, thereby dispersing the stress. This has the advantage of preventing stress concentration on the element substrate and the circuit board.

【0028】さらに、本発明は、上記硬化収縮性樹脂の
ガラス転移点を封止樹脂のガラス転移点よりも低く設定
することが好ましい。硬化収縮性樹脂のガラス転移点を
低くすることにより、封止樹脂の充填後硬化させる際に
加熱して硬化させた後の降温時にその硬化収縮性樹脂中
の残留応力を緩和することが可能となる。応力の緩和
は、硬化収縮性樹脂とこれを取り巻く封止樹脂との間の
相互接着を確実にすることができる効果がある。硬化収
縮性樹脂のガラス転移点は、封止樹脂のガラス転移点よ
り5〜50℃程度低いのが好ましい。このようなガラス
転移点の異なる硬化収縮性樹脂と封止樹脂とは、樹脂を
選定することにより、入手される。
Further, in the present invention, it is preferable that the glass transition point of the curing shrinkable resin is set lower than the glass transition point of the sealing resin. By lowering the glass transition point of the curing shrinkable resin, it is possible to relax the residual stress in the curing shrinkable resin at the time of cooling after heating and curing when filling and curing the sealing resin. Become. Relaxation of the stress has the effect of ensuring mutual adhesion between the cured shrinkable resin and the sealing resin surrounding it. The glass transition point of the curing shrinkable resin is preferably lower by about 5 to 50 ° C. than the glass transition point of the sealing resin. Such a curing shrinkable resin and a sealing resin having different glass transition points are obtained by selecting a resin.

【0029】さらに、本発明は、素子基板を含む機能素
子を回路基板の電極形成面にフリップチップ実装して実
装構造体の製造方法において、上記機能素子の素子基板
と回路基板との間の間隙に充填した封止樹脂が減圧下で
保持し、次いで硬化させる方法も採用される。
Further, the present invention provides a method of manufacturing a mounting structure by mounting a functional element including an element substrate on an electrode forming surface of a circuit board by flip-chip bonding, wherein a gap between the element substrate of the functional element and the circuit board is provided. A method is also employed in which the sealing resin filled in is kept under reduced pressure and then cured.

【0030】この封止樹脂充填の際に、好ましくは、減
圧下で上記電極形成面の間隙に充填する方法が利用でき
る。減圧下での充填は、気泡が生じにくいので、該間隙
への充足が容易である。
In filling the sealing resin, preferably, a method of filling the gap between the electrode forming surfaces under reduced pressure can be used. Filling under reduced pressure makes it easier to fill the gap because bubbles are less likely to be generated.

【0031】封止樹脂を充填して減圧下に保持した後、
復圧し、封止樹脂の硬化の際に、硬化を大気中雰囲気で
行う方法も好ましく利用される。減圧下で液状であった
封止樹脂を復圧することにより、封止樹脂は外圧を受け
て電極形成面の間の間隙へ完全に充足させることができ
る。復圧は大気圧まで行うことが好ましい。しかもその
後は、大気中での加熱が容易になるので、硬化を確実に
することができる。
After filling the sealing resin and keeping it under reduced pressure,
When the pressure is restored and the sealing resin is cured, a method in which the curing is performed in an air atmosphere is also preferably used. By returning the pressure of the sealing resin which has been in a liquid state under reduced pressure, the sealing resin receives the external pressure and can completely fill the gap between the electrode forming surfaces. It is preferable that the decompression is performed up to the atmospheric pressure. Moreover, thereafter, heating in the atmosphere is facilitated, so that curing can be ensured.

【0032】機能素子と回路基板との電極形成面の間の
間隙は、通常は、0.03〜0.20mm程度であり、
この間を浸透充填させるには、封止樹脂の粘度は、20
Pasの程度が良い。この実施の形態は、この間隙を充
填した樹脂に減圧と加圧を行うので、粘度は、さらに大
きな範囲で充分に充足可能となる。
The gap between the electrode forming surface of the functional element and the circuit board is usually about 0.03 to 0.20 mm,
In order to infiltrate and fill during this period, the viscosity of the sealing resin is set at 20.
Pas is good. In this embodiment, the resin filled in the gap is decompressed and pressurized, so that the viscosity can be sufficiently satisfied in a larger range.

【0033】充填した封止樹脂を減圧下で保持するこの
製造方法は、従来の公知の実装構造体の製造方法におい
ても広く適用されるが、さらに、上述の如く、封止樹脂
の充填に先立って、硬化膨張性樹脂により電極形成面の
一部の面域を接合する本発明の製造方法と組み合わせて
適用することもできる。
This manufacturing method of holding the filled sealing resin under reduced pressure is widely applied to a conventionally known method of manufacturing a mounting structure, and further, as described above, prior to filling the sealing resin. In addition, the present invention can be applied in combination with the manufacturing method of the present invention in which a part of the surface area of the electrode forming surface is joined by the hardening and expanding resin.

【0034】(実施形態1)次の本発明の実装構造体の
製造方法の具体例を述べると、回路基板3または半導体
装置の素子基板の何れかの電極形成面上に、上記特性の
硬化収縮性樹脂の液又はペーストをスポット状に盛りつ
ける。硬化収縮性樹脂の盛りつけは、バンプ電極を含ま
ないでバンプ電極列の内側又は外側の領域になされる。
この盛りつけに前後して、導電性接着剤を半導体装置の
多数のバンプ電極に塗着しておく。
(Embodiment 1) A specific example of a method of manufacturing a mounting structure according to the present invention will be described below. Curing shrinkage having the above characteristics is formed on an electrode forming surface of either the circuit board 3 or the element substrate of a semiconductor device. A liquid or paste of a conductive resin in a spot form. The setting of the curing shrinkable resin is performed in a region inside or outside the bump electrode row without including the bump electrode.
Before and after this arrangement, a conductive adhesive is applied to many bump electrodes of the semiconductor device.

【0035】硬化収縮性樹脂5は、上記半導体装置実装
前の回路基板3上の予め予測される反り変形量を収縮さ
せるに必要な盛り上げ量で上記電極形成面の適切な位置
に塗着しておく。スポット塗着の方法は、ディスペンサ
ーによる塗着法(押出法)が利用できる。
The curable shrinkable resin 5 is applied to an appropriate position on the electrode forming surface with an amount of swelling necessary to shrink the amount of warpage predicted on the circuit board 3 before mounting the semiconductor device. deep. A spot coating method (extrusion method) using a dispenser can be used as the spot coating method.

【0036】硬化収縮性樹脂には、上記の樹脂の液また
はペーストに代えて、軟質フイルム状の熱硬化性樹脂を
用いてその切片を、電極形成面の何れかに貼着する方法
を用いることもできる。
As the curing shrinkable resin, a method in which a soft film-like thermosetting resin is used in place of the above resin liquid or paste and a section thereof is attached to any of the electrode forming surfaces is used. Can also.

【0037】回路基板3と半導体装置とを両電極形成面
を対面させて両電極形成面が、盛り付けた硬化収縮性樹
脂に接触するように配置する。この配置の際に、半導体
装置側のバンプ電極2の先端が、回路基板3の端子電極
面に導電性接着剤により接合するように位置付けられ
る。
The circuit board 3 and the semiconductor device are arranged so that the two electrode forming surfaces face each other so that the two electrode forming surfaces are in contact with the hardened and shrinkable resin that has been provided. In this arrangement, the tip of the bump electrode 2 on the semiconductor device side is positioned so as to be joined to the terminal electrode surface of the circuit board 3 by a conductive adhesive.

【0038】回路基板3と半導体装置との配置後に硬化
収縮性樹脂を硬化させる。このとき回路基板に反りがあ
って、バンプ電極2の先端と回路基板3の一部の端子電
極面とが離れていても、硬化の過程で硬化収縮性樹脂が
収縮して回路基板3と半導体装置とを引っ張るので、バ
ンプ電極先端と端子電極面とは、相近接してバンプ電極
2の先端と回路基板3の端子電極面とが導電性接着剤に
より確実に接着して電気的導通がなされる。
After the arrangement of the circuit board 3 and the semiconductor device, the curing shrinkable resin is cured. At this time, even if the circuit board is warped and the tip of the bump electrode 2 and a part of the terminal electrode surface of the circuit board 3 are separated from each other, the curing shrinkable resin shrinks during the curing process and the circuit board 3 and the semiconductor Since the device is pulled, the tip of the bump electrode and the terminal electrode surface are close to each other, and the tip of the bump electrode 2 and the terminal electrode surface of the circuit board 3 are securely adhered to each other with a conductive adhesive, thereby achieving electrical conduction. .

【0039】次の段階は、硬化収縮性樹脂で仮止めされ
た回路基板3と半導体装置との両電極形成面の間隙に、
封止樹脂を充填して浸透させ、そのまま硬化させて、硬
化収縮性樹脂と封止樹脂とが一体化した実装構造体とす
る。
The next step is to fill the gap between the two electrode forming surfaces of the circuit board 3 and the semiconductor device, which are temporarily fixed with the curing shrinkable resin,
The sealing resin is filled, penetrated, and cured as it is to obtain a mounting structure in which the cured shrinkable resin and the sealing resin are integrated.

【0040】上例は、半導体装置と回路基板との電気的
接続を導電性接着剤6を用いるものであるが、本発明の
方法は、はんだバンプを用いた半導体装置に適用するこ
ともできる。
Although the above example uses the conductive adhesive 6 for electrical connection between the semiconductor device and the circuit board, the method of the present invention can also be applied to a semiconductor device using solder bumps.

【0041】このようにして、この例の実装構造体にお
いては、半導体装置を回路基板3上へフェイスダウン状
態でフリップチップ実装する際に、仮に回路基板3の反
りにより上記半導体装置の電気的接続点2と回路基板3
の入出力端子電極7とが電気的に接続できない箇所が予
測されるような場合でも(図1(B)参照)、前もって
塗着された硬化収縮性樹脂5により半導体装置と回路基
板3が接続されていると上記硬化収縮性樹脂5を硬化す
ることにより硬化体の収縮が起こり、半導体装置と回路
基板3とが互いに引張りあうので、全ての電気的接続点
の端子電極に対する電気的接続を確実に補償することが
できるのである。
As described above, in the mounting structure of this example, when the semiconductor device is flip-chip mounted face down on the circuit board 3, if the circuit board 3 is warped, the semiconductor device is electrically connected. Point 2 and circuit board 3
(See FIG. 1 (B)), the semiconductor device and the circuit board 3 are connected by the previously applied hardening / shrinkable resin 5 even when a portion where the input / output terminal electrode 7 cannot be electrically connected is predicted. In this case, the hardening of the cured shrinkable resin 5 causes the cured body to shrink, and the semiconductor device and the circuit board 3 are pulled toward each other, so that all the electrical connection points are securely connected to the terminal electrodes. Can be compensated for.

【0042】また、硬化収縮性樹脂5の硬化後に封止樹
脂4を供給するため、ICチップ1上の電気的接続点2
と回路基板3上の入出力電極7間への封止樹脂4の流れ
込みを防ぐことができる。ゆえに、回路基板の反りに関
する管理条件を緩和することが可能となる。さらに、硬
化収縮性樹脂5を封止樹脂4とは異なる樹脂を用いるこ
とにより吸水率、熱膨張係数等の条件を懸念する必要が
なく硬化時間の短い樹脂を選定することが可能となり生
産性が向上する。
In order to supply the sealing resin 4 after the curing and shrinking resin 5 is cured, the electric connection points 2 on the IC chip 1
And the inflow of the sealing resin 4 between the input / output electrodes 7 on the circuit board 3 can be prevented. Therefore, it is possible to ease the management condition regarding the warpage of the circuit board. Further, by using a resin different from the sealing resin 4 as the curing shrinkable resin 5, it is not necessary to worry about the conditions such as the water absorption coefficient and the coefficient of thermal expansion, and it is possible to select a resin having a short curing time, thereby improving productivity. improves.

【0043】(実施形態2)図2は、半導体装置と回路
基板間に硬化収縮性樹脂にて少なくとも2箇所以上接続
する領域を有する実装構造体を示す。IC基板1に公知
の方法により電気的接続点(バンプ電極)2を形成し半
導体装置とする。上記半導体装置と回路基板3の少なく
とも一方へ硬化収縮性樹脂5を上記半導体装置実装前に
2箇所以上スポット状に盛り付け塗着してから、実施形
態1と同様にして、回路基板上に半導体装置を搭載す
る。
(Embodiment 2) FIG. 2 shows a mounting structure having at least two or more regions connected between a semiconductor device and a circuit board with a curing shrinkable resin. An electrical connection point (bump electrode) 2 is formed on the IC substrate 1 by a known method to obtain a semiconductor device. At least one of the semiconductor device and the circuit board 3 is hardened and shrinkable resin 5 is applied at two or more spots before the semiconductor device is mounted, and then the semiconductor device is mounted on the circuit board in the same manner as in the first embodiment. With.

【0044】本実施形態2の実装構造体においては、半
導体装置と回路基板3間の硬化収縮性樹脂5の接続領域
を少なくとも2箇所以上にすることにより、封止樹脂硬
化時に封止樹脂と硬化後の硬化収縮性樹脂5との境界部
に発生する応力を分散することができ生産性を向上させ
ることが可能となる。
In the mounting structure of the second embodiment, the number of connection regions of the hardening / shrinkable resin 5 between the semiconductor device and the circuit board 3 is at least two or more so that the hardening resin and the hardening resin are hardened when the hardening resin is hardened. It is possible to disperse the stress generated at the boundary with the cured shrinkable resin 5 later, thereby improving the productivity.

【0045】(実施形態3)IC基板に公知の方法によ
り電気的接続点(バンプ電極)を形成し半導体装置を利
用して、半導体装置と回路基板の少なくとも一方へ封止
樹脂のガラス転移点より低い特性を有する硬化収縮性樹
脂を上記半導体装置又は回路基板の電極形成面に盛り付
け塗着する。続いて上述のように上記半導体装置を上記
回路基板上へフリップチップ実装を行い、後に硬化収縮
性樹脂の硬化を行う。硬化収縮性樹脂の硬化後に、半導
体装置のIC基板と回路基板との間隙に封止樹脂を浸透
充填し、加温して硬化させる。
(Embodiment 3) An electrical connection point (bump electrode) is formed on an IC substrate by a known method, and a semiconductor device is used to connect at least one of the semiconductor device and the circuit board from the glass transition point of the sealing resin. A hardening / shrinkable resin having low characteristics is applied and applied to the electrode forming surface of the semiconductor device or the circuit board. Subsequently, as described above, the semiconductor device is flip-chip mounted on the circuit board, and thereafter, the curing shrinkable resin is cured. After the curing shrinkable resin is cured, the gap between the IC substrate and the circuit substrate of the semiconductor device is filled with the sealing resin by penetration, and then heated to be cured.

【0046】この実装構造体の製造方法は、半導体装置
と回路基板間の硬化収縮性樹脂のガラス転移点を封止樹
脂のガラス転移点より低く設定することにより、封止樹
脂硬化時、特に封止樹脂硬化後の降温時に上記硬化収縮
性樹脂と上記封止樹脂との境界部に発生する応力を硬化
収縮性樹脂のガラス転移点以上では吸収することができ
室温状態にした時の実装構造体内の残留応力を低減する
ことができ実装構造体の信頼性を向上させることが可能
となる。
In the method of manufacturing the mounting structure, the glass transition point of the curing shrinkable resin between the semiconductor device and the circuit board is set lower than the glass transition point of the sealing resin. The stress generated at the boundary between the curing shrinkable resin and the encapsulating resin when the temperature is lowered after the hardening resin is cured can be absorbed above the glass transition point of the curing shrinkable resin and can be absorbed in the mounting structure at room temperature. Can be reduced, and the reliability of the mounting structure can be improved.

【0047】(実施形態4)半導体装置のIC基板に公
知の方法により電気的接続点(バンプ電極)を形成し半
導体装置とする。上記半導体装置と回路基板の少なくと
も一方へ封止樹脂のガラス転移点より低い特性を有する
硬化収縮性樹脂を上記半導体装置実装前に2箇所以上盛
り付けする。
Embodiment 4 An electrical connection point (bump electrode) is formed on an IC substrate of a semiconductor device by a known method to obtain a semiconductor device. At least one of the semiconductor device and the circuit board is provided with two or more hardening-shrinkable resins having characteristics lower than the glass transition point of the sealing resin before mounting the semiconductor device.

【0048】続いて上記半導体装置を上記回路基板上へ
フリップチップ実装を行った後に硬化収縮性樹脂の硬化
を行う。硬化収縮性樹脂の硬化後に、半導体装置のIC
基板と回路基板との間隙に封止樹脂を浸透充填し、加温
して硬化させる。
Subsequently, after the semiconductor device is flip-chip mounted on the circuit board, the curing shrinkable resin is cured. After the curing shrinkable resin is cured, the IC of the semiconductor device
A gap between the substrate and the circuit board is filled with a sealing resin by infiltration and is heated and cured.

【0049】本実施形態の実装構造体においては、半導
体装置のIC基板と回路基板との間の硬化収縮性樹脂に
より接続領域を2箇所にすることにより封止樹脂硬化時
に上記硬化収縮性樹脂と上記封止樹脂との境界部に発生
する応力を分散することができ、かつ上記硬化収縮性樹
脂のガラス転移点を封止樹脂のガラス転移点より低く設
定することにより封止樹脂硬化後の降温時に上記硬化収
縮性樹脂と封止樹脂との境界部分に発生する応力も吸収
することができ相乗効果的に生産性を向上させることが
可能となる。
In the mounting structure according to the present embodiment, by setting the connection region to two places by the hardening / shrinking resin between the IC substrate and the circuit board of the semiconductor device, the hardening and shrinking resin is hardened when the sealing resin is hardened. The stress generated at the boundary with the sealing resin can be dispersed, and the glass transition point of the cured shrinkable resin is set to be lower than the glass transition point of the sealing resin, thereby lowering the temperature after the sealing resin is cured. In some cases, stress generated at the boundary between the curing shrinkable resin and the sealing resin can be absorbed, so that productivity can be synergistically improved.

【0050】(実施形態5)IC基板に公知の方法によ
り電気的接続点(バンプ電極)を形成し半導体装置とす
る。上記半導体装置と回路基板の少なくとも一方の電極
形成面に硬化収縮性樹脂を盛り付け塗着する。
(Embodiment 5) An electrical connection point (bump electrode) is formed on an IC substrate by a known method to obtain a semiconductor device. At least one of the electrode forming surfaces of the semiconductor device and the circuit board is coated with a curing shrinkable resin and applied.

【0051】続いて上述の方法で上記半導体装置を上記
回路基板上へフリップチップ実装を行った後に硬化収縮
性樹脂を半硬化状態に保持し、最後に封止樹脂を間隙に
充填して硬化を行うがこのとき上記硬化収縮性樹脂の本
硬化も同時に行い実装構造体とする。
Subsequently, the semiconductor device is flip-chip mounted on the circuit board by the above-described method, and then the cured shrinkable resin is held in a semi-cured state. Finally, the sealing resin is filled in the gap to cure the resin. At this time, the main curing of the cured shrinkable resin is also performed at the same time to obtain a mounting structure.

【0052】この実施の形態に使用される硬化収縮性樹
脂は、硬化時の収縮性と盛り付け可能な程度の高粘度と
を備える点は上述の通りであるが、その硬化速度を抑制
して加温により硬化が進行する熱硬化性樹脂が利用さ
れ、硬化収縮性樹脂を半硬化状態に保持し、封止樹脂の
加温時に硬化させるものである。
As described above, the curing shrinkable resin used in this embodiment has shrinkage during curing and a high viscosity that can be applied as described above. A thermosetting resin that cures with temperature is used, and the curing shrinkable resin is maintained in a semi-cured state, and is cured when the sealing resin is heated.

【0053】この実装構造体においては、硬化収縮性樹
脂の本硬化を封止樹脂の硬化と同時に行うことにより、
硬化収縮性樹脂と封止樹脂との界面の密着性を増すこと
ができ実装構造体の信頼性を向上させることが可能とな
る。
In this mounting structure, the main curing of the curing shrinkable resin is performed simultaneously with the curing of the sealing resin, so that
The adhesion at the interface between the curing shrinkable resin and the sealing resin can be increased, and the reliability of the mounting structure can be improved.

【0054】(実施形態6)IC基板に公知の方法によ
り電気的接続点(バンプ電極)を形成し半導体装置とす
る。上記半導体装置と回路基板の電極形成面とを、公知
の方法で、フリップチップ実装を行い、導電性樹脂接着
剤により、電極間を接続する。
(Embodiment 6) An electrical connection point (bump electrode) is formed on an IC substrate by a known method to obtain a semiconductor device. The semiconductor device and the electrode forming surface of the circuit board are flip-chip mounted by a known method, and the electrodes are connected by a conductive resin adhesive.

【0055】次いで、半導体装置のIC基板と回路基板
と電極形成面の間隙に封止樹脂を浸透充填するが、この
際、真空槽に装入して、10-2Torr程度まで真空状態に
した後に、電極形成面の間隙に封止樹脂を充填する。充
填後に真空槽を大気圧に復圧して加温して上記封止樹脂
の硬化を行う。この場合、電極形成面間隙に充填時に封
止樹脂の未充足部が残っても、復圧時に封止樹脂に外圧
が作用して、上記間隙への封止樹脂の完全充足が可能に
なる。さらに、封止樹脂の粘度変化による充填のバラツ
キが生じても、減圧と復圧による完全充足ができるの
で、封止樹脂の粘度等の材料管理を緩和することが可能
となる。封止樹脂の充填時の圧力は、上記10-2Torrに
限らず、雰囲気圧力は、好ましくは100Torr〜10-3
Torr程度までの真空度が利用できるが、この範囲に限ら
ず、適宜設定してよい。
Next, the gap between the IC substrate, the circuit substrate, and the electrode forming surface of the semiconductor device is filled with a sealing resin by permeation. At this time, the sealing resin is charged into a vacuum chamber to make a vacuum state to about 10 −2 Torr. Subsequently, the sealing resin is filled in the gap between the electrode forming surfaces. After the filling, the pressure in the vacuum chamber is restored to the atmospheric pressure and heated to cure the sealing resin. In this case, even if an unfilled portion of the sealing resin is left in the gap between the electrode forming surfaces at the time of filling, an external pressure acts on the sealing resin at the time of restoring pressure, so that the gap can be completely filled with the sealing resin. Furthermore, even if the filling varies due to a change in the viscosity of the sealing resin, the pressure can be completely satisfied by reducing and returning the pressure, so that material management such as the viscosity of the sealing resin can be eased. Pressure during filling of the sealing resin is not limited to the above 10 -2 Torr, the atmosphere pressure is preferably 100Torr~10 -3
A degree of vacuum up to about Torr can be used, but is not limited to this range and may be set as appropriate.

【0056】(実施形態7)IC基板に公知の方法によ
り電気的接続点(バンプ電極)を形成し半導体装置とす
る。次にこの半導体装置のIC基板と回路基板と電極形
成面間の間隙31に従来の方法により封止樹脂6を充填
した後に真空槽内に配置し減圧して真空状態にする。雰
囲気圧力は、好ましくは100Torr〜10-3Torr程度ま
での真空度が利用できる。その後大気圧に復圧して上記
封止樹脂の硬化を行う。
(Embodiment 7) An electrical connection point (bump electrode) is formed on an IC substrate by a known method to obtain a semiconductor device. Next, the gap 31 between the IC substrate, the circuit board, and the electrode forming surface of the semiconductor device is filled with the sealing resin 6 by a conventional method, and then placed in a vacuum chamber to be evacuated to a vacuum state. As the atmospheric pressure, a vacuum degree of preferably about 100 Torr to 10 -3 Torr can be used. Thereafter, the pressure is returned to the atmospheric pressure to cure the sealing resin.

【0057】本実施形態の製造方法においては、電極形
成面10、30間の間隙31に充填した封止樹脂が、間
隙に完全に充足せずに未充足部が気泡として残っている
場合にも、減圧することにより気泡が膨張して間隙から
放出され、その残部を封止樹脂が埋めて復圧の際に間隙
への封止樹脂の完全充足が可能になる。この方法は、特
に、封止樹脂の硬化を真空状態ではなく大気中で行うこ
とにより熱伝導を促進するので、硬化に要する時間を短
縮することができ生産性を向上させることが可能とな
る。減圧と復圧の操作により高粘度の封止樹脂でも間隙
31への完全充足が可能になるので、封止樹脂の粘度等
の材料管理を緩和することが可能となる。
In the manufacturing method of the present embodiment, even when the sealing resin filled in the gap 31 between the electrode forming surfaces 10 and 30 does not completely fill the gap and the unfilled portion remains as bubbles. When the pressure is reduced, the bubbles expand and are released from the gap, and the remaining portion is filled with the sealing resin, so that the gap can be completely filled with the sealing resin when the pressure is restored. This method promotes heat conduction by curing the sealing resin not in a vacuum state but in the air, so that the time required for curing can be shortened and the productivity can be improved. Since the gap 31 can be completely filled even with the sealing resin having a high viscosity by the operation of reducing the pressure and returning the pressure, the material management such as the viscosity of the sealing resin can be eased.

【0058】(実施形態8)IC基板に公知の方法によ
り電気的接続点(バンプ電極)を形成し半導体装置とす
る。上記半導体装置と回路基板の少なくとも一方へ封止
樹脂とは異なる硬化収縮性樹脂を上記半導体装置実装前
の回路基板上に供給する。続いて上記半導体装置を上記
回路基板上へフリップチップ実装を行った後に上記硬化
収縮性樹脂の硬化を行う。次に上記半導体装置に封止樹
脂を供給し真空状態にする。10-2Torr程度に減圧す
る。尤も本発明は、この真空度に制限されるものではな
い。その後に大気圧に復圧して大気中に取り出し、上記
封止樹脂の加熱硬化を行う。
(Embodiment 8) An electrical connection point (bump electrode) is formed on an IC substrate by a known method to obtain a semiconductor device. A curing shrinkable resin different from the sealing resin is supplied to at least one of the semiconductor device and the circuit board on the circuit board before mounting the semiconductor device. Subsequently, after the semiconductor device is flip-chip mounted on the circuit board, the curing shrinkable resin is cured. Next, a sealing resin is supplied to the semiconductor device to make it vacuum. Reduce the pressure to about 10 -2 Torr. However, the present invention is not limited to this degree of vacuum. Thereafter, the pressure is returned to the atmospheric pressure, and the pressure is taken out to the atmosphere, and the sealing resin is heated and cured.

【0059】本実施形態8の製造方法においては、フリ
ップチップ実装前に半導体装置と回路基板間に硬化収縮
性樹脂を塗着してその硬化時の収縮引張力により電極間
の接続を完全にするので、半導体装置が実装される前の
回路基板に反りがあっても、利用可能となり、回路基板
の反り変形に関する管理を緩和することができる。さら
に、封止樹脂の供給を圧力差を利用して行うことによ
り、封止樹脂の粘度の変動があっても電極形成面間の間
隙への完全充足が可能になり、封止樹脂の粘度に関する
管理を緩和することが可能となる。半導体装置の実装構
造体への生産性を向上することができる。
In the manufacturing method according to the eighth embodiment, before the flip chip is mounted, a hardening and shrinking resin is applied between the semiconductor device and the circuit board, and the connection between the electrodes is completed by the shrinking tensile force at the time of hardening. Therefore, even if the circuit board before the semiconductor device is mounted has warpage, the circuit board can be used, and management of warpage deformation of the circuit board can be eased. Further, by performing the supply of the sealing resin using the pressure difference, it is possible to completely fill the gap between the electrode forming surfaces even if the viscosity of the sealing resin fluctuates. Management can be eased. The productivity of the mounting structure of the semiconductor device can be improved.

【0060】[0060]

【発明の効果】以上述べてきたように本発明は、半導体
装置と回路基板との間を封止樹脂とは異なる硬化収縮性
樹脂にて接続する領域を設けることにより、回路基板の
反り変形に対しての許容範囲が広くなり、半導体装置実
装前の回路基板の反りに関する管理条件を緩和すること
ができ、生産性を向上することができる。
As described above, according to the present invention, by providing a region for connecting a semiconductor device and a circuit board with a hardening / shrinking resin different from a sealing resin, warpage of the circuit board can be reduced. As a result, it is possible to relax the control conditions relating to the warpage of the circuit board before mounting the semiconductor device, thereby improving the productivity.

【0061】また、半導体装置と回路基板間を封止樹脂
とは異なる硬化収縮性樹脂にて少なくとも2個所以上接
続する領域を設けることにより封止樹脂の硬化時に発生
する応力を分散することができ生産性を向上させること
ができる。
Further, by providing at least two regions for connecting the semiconductor device and the circuit board with a hardening / shrinking resin different from the sealing resin, stress generated when the sealing resin is hardened can be dispersed. Productivity can be improved.

【0062】また、上記硬化収縮性樹脂のガラス転移点
を封止樹脂より低く設定することにより封止樹脂硬化後
の降温時に発生する応力を分散することができ生産性を
向上させることができる。
Further, by setting the glass transition point of the curing shrinkable resin to be lower than that of the sealing resin, stress generated when the temperature of the sealing resin is lowered after the curing of the sealing resin can be dispersed, and the productivity can be improved.

【0063】さらに、上記硬化収縮性樹脂を半硬化状態
とし封止樹脂と共に本硬化を行うことにより硬化収縮性
樹脂と封止樹脂との密着性が向上し実装構造体の信頼性
を向上することができる。
Further, by making the cured shrinkable resin semi-cured and performing the main curing together with the sealing resin, the adhesion between the cured shrinkable resin and the sealing resin is improved, and the reliability of the mounting structure is improved. Can be.

【0064】一方、封止樹脂を供給する際に半導体装置
と回路基板間の隙間と外部とに気圧差を設けることによ
り封止樹脂の粘度に関する管理条件を緩和することがで
き生産性を向上させることができる。
On the other hand, by providing a pressure difference between the semiconductor device and the circuit board and the outside when supplying the sealing resin, the control condition relating to the viscosity of the sealing resin can be relaxed and the productivity can be improved. be able to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】半導体装置と回路基板間に封止樹脂とは異なる
硬化収縮性樹脂にて接続する領域を有する実装構造体の
概略断面図(A)と回路基板に反りがある場合の、硬化
収縮性樹脂にて接続する際の概略断面図(B)。
FIG. 1 is a schematic cross-sectional view of a mounting structure having a region connected between a semiconductor device and a circuit board with a curing shrinkage resin different from a sealing resin, and curing shrinkage when the circuit board is warped; FIG. 2B is a schematic cross-sectional view when connecting with a conductive resin.

【図2】半導体装置と回路基板間に封止樹脂とは異なる
硬化収縮性樹脂にて2箇所で接続した領域を有する実装
構造体の概略断面図。
FIG. 2 is a schematic cross-sectional view of a mounting structure having two regions connected between a semiconductor device and a circuit board with a hardening / shrinking resin different from a sealing resin.

【図3】従来のはんだバンプ電極を有する半導体装置の
バンプ電極の概略断面図(A)と、従来のはんだバンプ
電極を有する半導体装置の実装構造体の概略断面図
(B)。
3A is a schematic cross-sectional view of a bump electrode of a semiconductor device having a conventional solder bump electrode, and FIG. 3B is a schematic cross-sectional view of a mounting structure of the semiconductor device having a conventional solder bump electrode.

【図4】従来の導電性接着剤を用いた実装構造体の概略
説明図。
FIG. 4 is a schematic explanatory view of a mounting structure using a conventional conductive adhesive.

【符号の説明】[Explanation of symbols]

1 IC基板 10 電極形成面 2 電気的接続点(バンプ電極) 22 はんだバンプ 23 電気的接続点(Auバンプ) 3 回路基板 30 電極形成面 4 封止樹脂 5 硬化収縮性樹脂 6 導電性接着剤(接合層) 7 電極(入出力端子電極) 8 電極(電極パッド) DESCRIPTION OF SYMBOLS 1 IC board 10 Electrode formation surface 2 Electrical connection point (bump electrode) 22 Solder bump 23 Electrical connection point (Au bump) 3 Circuit board 30 Electrode formation surface 4 Sealing resin 5 Curing shrinkable resin 6 Conductive adhesive ( 7) Electrode (input / output terminal electrode) 8 Electrode (electrode pad)

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成11年1月18日[Submission date] January 18, 1999

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

───────────────────────────────────────────────────── フロントページの続き (72)発明者 林 祥剛 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shogo Hayashi

Claims (19)

【特許請求の範囲】[Claims] 【請求項1】 素子基板を含む機能素子を回路基板にフ
リップチップ実装して成る実装構造体において、 上記機能素子の素子基板と上記回路基板間との相対向す
る電極形成面間の間隙に、電極形成面の面域の一部を接
合する硬化収縮性樹脂と、該面域の残部を充填する封止
樹脂とを有することを特徴とする機能素子の実装構造
体。
1. A mounting structure in which a functional element including an element substrate is flip-chip mounted on a circuit board, wherein a gap between opposing electrode forming surfaces between the element substrate of the functional element and the circuit board is provided. A mounting structure for a functional element, comprising: a curing shrinkable resin for joining a part of a surface area of an electrode forming surface; and a sealing resin for filling a remaining part of the surface area.
【請求項2】 上記実装構造体が、機能素子と回路基板
との電極間が導電性接着剤により電気的接続されたこと
を特徴とする請求項1記載の実装構造体。
2. The mounting structure according to claim 1, wherein the mounting structure is electrically connected between electrodes of the functional element and the circuit board by a conductive adhesive.
【請求項3】 上記の硬化収縮性樹脂が、上記電極形成
面の面域内に、少なくとも2箇所以上接続する領域を有
することを特徴とする請求項1又は2に記載の実装構造
体。
3. The mounting structure according to claim 1, wherein the curing shrinkable resin has at least two or more connecting regions in a surface area of the electrode forming surface.
【請求項4】 上記の硬化収縮性樹脂は、上記の封止樹
脂よりガラス転移点が低い特性を有することを特徴とす
る請求項1ないし3何れかに記載の実装構造体。
4. The mounting structure according to claim 1, wherein the curing shrinkable resin has a property that the glass transition point is lower than that of the sealing resin.
【請求項5】 上記硬化収縮性樹脂は、上記の封止樹脂
よりガラス転移点が低い特性を有し、且つ、上記電極形
成面の面域内に、少なくとも2箇所以上接続する領域を
有することを特徴とする実装構造体。
5. The curing shrinkable resin has a property that the glass transition point is lower than that of the sealing resin, and has at least two or more connection regions in a surface area of the electrode forming surface. Characteristic mounting structure.
【請求項6】 上記機能素子が、半導体装置である請求
項1ないし5記載の実装構造体。
6. The mounting structure according to claim 1, wherein the functional element is a semiconductor device.
【請求項7】 素子基板を含む機能素子を回路基板の電
極形成面にフリップチップ実装して、実装構造体を製造
する方法において、 上記機能素子の素子基板と回路基板とのいずれかの電極
形成面の面域の一部に硬化収縮性樹脂を実装前の回路基
板上の反り以上の収縮量をもって塗着し、 上記機能素子と回路基板との電極形成面間を対向し、上
記硬化収縮性樹脂を硬化させて接合し、 次いで、上記電極形成面間に封止樹脂を充填して硬化さ
せることを特徴とする実装構造体の製造方法。
7. A method for manufacturing a mounting structure by flip-chip mounting a functional element including an element substrate on an electrode forming surface of a circuit board, comprising: forming an electrode on one of the element substrate and the circuit board of the functional element; A hardening shrinkable resin is applied to a part of the surface area of the surface with a shrinkage amount equal to or more than the warpage on the circuit board before mounting, and the electrode forming surfaces of the functional element and the circuit board are opposed to each other. A method for manufacturing a mounting structure, comprising curing and joining a resin, and then filling and curing a sealing resin between the electrode forming surfaces.
【請求項8】 上記電極形成面の接合の際に、機能素子
と回路基板との電極形成面の電極間を導電性接着剤によ
り電気的に接続することを特徴とする請求項7に記載の
実装構造体の製造方法。
8. The method according to claim 7, wherein, at the time of joining the electrode forming surfaces, the electrodes on the electrode forming surfaces of the functional element and the circuit board are electrically connected by a conductive adhesive. Manufacturing method of mounting structure.
【請求項9】 上記の硬化収縮性樹脂は、電極形成面に
塗着の際に、上記電極形成面の面域内に、少なくとも2
箇所以上塗着することを特徴とする請求項7に記載の実
装構造体の製造方法。
9. The method according to claim 9, wherein the curing shrinkable resin is applied to the electrode forming surface at least in a surface area of the electrode forming surface.
The method for manufacturing a mounting structure according to claim 7, wherein the coating is performed at more than one portion.
【請求項10】 上記硬化収縮性樹脂が、上記の封止樹
脂よりガラス転移点が低い特性を有することを特徴とす
る請求項7又は9に記載の実装構造体の製造方法。
10. The method according to claim 7, wherein the curing shrinkable resin has a lower glass transition point than the sealing resin.
【請求項11】 上記硬化収縮性樹脂は、上記の封止樹
脂よりガラス転移点が低い特性を有し、且つ、上記電極
形成面の面域内に、少なくとも2箇所以上接続する領域
を有することを特徴とする請求項7又は9に記載の実装
構造体の製造方法。
11. The curing shrinkable resin has a property that a glass transition point is lower than that of the sealing resin, and has at least two or more connection regions in a surface area of the electrode forming surface. The method for manufacturing a mounting structure according to claim 7 or 9, wherein:
【請求項12】 電極形成面間を接合する際に、上記硬
化収縮性樹脂を半硬化状態とし、次いで、封止樹脂の充
填後の硬化の際に同時に硬化収縮性樹脂の本硬化を行う
ことを特徴とする請求項7又は9に記載の実装構造体の
製造方法。
12. When the electrode forming surfaces are joined, the cured shrinkable resin is brought into a semi-cured state, and then, the main curing of the cured shrinkable resin is performed simultaneously with the curing after filling with the sealing resin. The method for manufacturing a mounting structure according to claim 7 or 9, wherein:
【請求項13】 素子基板を含む機能素子を回路基板の
電極形成面にフリップチップ実装して、実装構造体を製
造する方法において、 上記機能素子の素子基板と回路基板との電極形成面間に
封止樹脂を充填して該封止樹脂を減圧下で保持し、次い
で硬化させることを特徴とする実装構造体の製造方法。
13. A method of manufacturing a mounting structure by flip-chip mounting a functional element including an element substrate on an electrode forming surface of a circuit board, wherein the functional element is provided between the electrode forming surface of the functional substrate and the electrode forming surface of the circuit board. A method for manufacturing a mounting structure, comprising filling a sealing resin, holding the sealing resin under reduced pressure, and then curing the resin.
【請求項14】 上記封止樹脂の充填の際に、減圧下で
上記電極形成面間に充填することを特徴とする請求項1
3に記載の実装構造体の製造方法。
14. The method according to claim 1, wherein said sealing resin is filled between said electrode forming surfaces under reduced pressure.
4. The method for manufacturing the mounting structure according to 3.
【請求項15】 上記封止樹脂の硬化の際に、大気中雰
囲気で行うことを特徴とする請求項13又は14に記載
の実装構造体の製造方法。
15. The method according to claim 13, wherein the curing of the sealing resin is performed in an air atmosphere.
【請求項16】 上記封止樹脂を充填して硬化させる際
に、上記機能素子の素子基板と回路基板との電極形成面
間に充填した該封止樹脂を減圧下で保持し、次いで硬化
させることを特徴とする請求項7ないし12何れかに記
載の実装構造体の製造方法。
16. When the sealing resin is filled and cured, the sealing resin filled between the electrode forming surfaces of the element substrate and the circuit board of the functional element is held under reduced pressure, and then cured. 13. The method for manufacturing a mounting structure according to claim 7, wherein:
【請求項17】 上記封止樹脂の充填の際に、減圧下で
上記電極形成面間に充填することを特徴とする請求項1
6に記載の実装構造体の製造方法。
17. The method as claimed in claim 1, wherein said sealing resin is filled under a reduced pressure between said electrode forming surfaces.
7. The manufacturing method of the mounting structure according to 6.
【請求項18】 上記封止樹脂の硬化の際に、大気中雰
囲気で保持することを特徴とする請求項16に記載の実
装構造体の製造方法。
18. The method according to claim 16, wherein the sealing resin is kept in an atmosphere in the atmosphere when the sealing resin is cured.
【請求項19】 上記機能素子が、半導体装置である請
求項7ないし18いずれかに記載の実装構造体の製造方
法。
19. The method according to claim 7, wherein the functional element is a semiconductor device.
JP00296498A 1998-01-09 1998-01-09 Mounting structure of functional element and method of manufacturing the same Expired - Fee Related JP3273556B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7670873B2 (en) 2006-02-08 2010-03-02 Fujitsu Limited Method of flip-chip mounting
WO2012131800A1 (en) * 2011-03-31 2012-10-04 Necエナジーデバイス株式会社 Battery pack and electric bicycle
CN109936923A (en) * 2019-03-25 2019-06-25 北京百度网讯科技有限公司 Method and apparatus for determining chip attachment data

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7670873B2 (en) 2006-02-08 2010-03-02 Fujitsu Limited Method of flip-chip mounting
WO2012131800A1 (en) * 2011-03-31 2012-10-04 Necエナジーデバイス株式会社 Battery pack and electric bicycle
JP2012212599A (en) * 2011-03-31 2012-11-01 Nec Energy Devices Ltd Battery pack, and power-assisted bicycle
US9287591B2 (en) 2011-03-31 2016-03-15 Nec Energy Devices, Ltd. Battery pack with protective circuit board and electric bicycle including the battery pack
CN109936923A (en) * 2019-03-25 2019-06-25 北京百度网讯科技有限公司 Method and apparatus for determining chip attachment data
CN109936923B (en) * 2019-03-25 2020-10-13 北京百度网讯科技有限公司 Method and apparatus for determining chip mounting data

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