JPH11203155A - Data storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decide the normality of a data order by comparing quantity of data that is transmitted by a communication processor with quantity of data of which communication processing is completed. SOLUTION: When value DP that is written from a data processor 11' is below the sum of data number X2 which is completed transmission processing and data number (n) which can be transmitted through bidirectional memory 31 at one time, it is normal. If it exceeds the sum, data number that is transmitted is too large than data number that is performed transmission processing, it is decided that abnormality occurs, and '1' is written to the bidirectional memory EF and the processing is finished. When there is no abnormality, it is decided whether or not data number DP that is next transmitted is below the data number X2 that is completed transmission processing. When the DP is below the X2, it is decided that abnormality occurs and '1' is written to the memory EF. And when there is no abnormality, next, an index register Y2 which stores an offset of the memory EF is made '0' and this makes it possible to access from a leading address DM+0 of the memory 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device for storing data.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a conventional data storage device. 3, 11 is a data processing device, 12 is a communication processing device, 2 is a main memory, 31 and 32 are bidirectional memories, 41, 42, 43 and 44 are index registers,
Reference numeral 5 denotes a communication interface. For convenience of explanation, the number of internal memories of the main memory 2 is m, the head address is MM + 0, and the following addresses are updated to offset MM + 1,
MM + 2,..., MM + m. Similarly, the number of internal memories of the bidirectional memory 31 is set to n, the start address is set to DM + 0, and the following addresses are updated by updating the offset to DM + 1,
.., DM + n. Here, it is assumed that the relationship between the number m of the internal memories of the main memory 2 and the number n of the internal memories of the bidirectional memory 31 is m> n. The bidirectional memory 3
2 for DF, index register 41 for X1, 42 for Y
1, 43 for X2, 44 for Y2, communication interface 5
Is denoted by COM.

The operation of FIG. 3 is divided into a data control unit and a communication control unit, and the operation will be described below with reference to a flowchart of FIG. However, the initial value of the bidirectional memory DF is set to 0. The data processing unit 11 of the data control unit has an index register X1 for storing the offset of the main memory 2.
Is set to 0 so that the main memory 2 can be accessed from the start address MM + 0. Next, the data is stored in the bidirectional memory 31.
When the value of the bidirectional memory DF indicating that the data has been written to the communication control unit is 1, it is assumed that the processing of the communication control unit has not been completed, and the communication control unit enters a wait state. Next, the data processing device 11 sets the index register Y1 for storing the offset of the bidirectional memory 31 to 0, and sets the start address DM of the bidirectional memory 31 to 0.
Make it accessible from +0. Data processing device 1
1 reads the data at the address MM + 0 of the main memory 2 and writes the data at the address DM + 0 of the bidirectional memory 31.
1 is added to the original value of each of X1 and Y1 and stored. First, it is determined whether or not the value of X1 has reached the total number of memories of the main memory 2, that is, m, and all the data transmission to the bidirectional memory 31 has been completed.

If the data transmission for all the memories of the main memory 2 is not completed, the value of Y1 next reaches the total number of memories of the bidirectional memory 31, that is, n, and the value of the bidirectional memory 31 can be transmitted at one time. It is determined whether data writing has been completed. If the n data transmissions have not been completed, the process is repeated until the writing of the n data is completed. When n data transmissions are completed, 1 is written to DF,
Is 0, that is, a standby state is established until the processing of the communication control unit is completed. After the DF becomes 0, the process is repeated until all the data in the main memory 2, that is, m data transmissions are completed. When m data transmissions are completed, 1 is written to the DF, and the processing of the data control unit ends.

[0005] The data processing device 12 of the communication control unit firstly stores an index register X2 for counting the number of transmission data.
Is set to 0, and when DF is 0, that is, when there is no data transmission from the data control unit, the system is in a waiting state until transmission is performed. When the DF becomes 1, the index register Y2 for storing the offset of the bidirectional memory 31 is set to 0 so that the bidirectional memory 31 can be accessed from the start address DM + 0. The communication processing device 12 reads the data at the address DM + 0 of the bidirectional memory 31, writes the data at the communication interface COM, and transmits the data. 1 is added to the original value of each of X2 and Y2 and stored, and first, the value of X2 is the total number of memories in main memory 2, that is, m
Is reached, it is determined whether or not all data writing to the communication interface COM has been completed.

If the data transmission for the total number of memories in the main memory 2 is not completed, the value of Y2 next reaches the total number of memories in the bidirectional memory 31, that is, n, so that the bidirectional memory 31 can transmit at one time. It is determined whether the reading of data is completed. If the transmission of n data has not been completed, the processing is repeated until the reading of n data is completed. When n data transmissions are completed, 0 is written to DF,
Is 1, that is, from the data control unit to the bidirectional memory 31 again.
It is in a waiting state until the writing of data to is completed. D
After F becomes 1, the process is repeated until the data transmission of the total number m of data in the main memory 2 is completed. When m data transmissions have been completed, 0 is written to DF, and the processing of the communication control unit ends. By performing the above processing, more data is transmitted than the medium for transmitting data,
Can be sent.

[0007]

In this apparatus, however, the communication processing unit 12 is notified only that data has been transmitted from the data processing unit 11 via the bidirectional memory DF. If synchronization is lost between the device 12 and the data processing device 11,
For example, the number of data transmitted by the data processing device 11 is 2n
However, if the communication processing device 12 determines that the number of data that has completed the transmission processing is n, the data transmission is not performed normally, but it is impossible to determine the abnormality. The present invention has been made in view of the above points, and an object of the present invention is to provide a data storage device that solves these disadvantages.

[0008]

Means for achieving the object are as follows: 1) In claim 1, a data processing device for controlling data and a plurality of data processing devices for recording or reproducing data. A main memory, an index register for recording or reproducing an offset of a memory in which the data processing device stores data, a plurality of bidirectional memories for transmitting data, and a data transmission device for transmitting data. An index register for recording or reproducing the offset of the bidirectional memory, a bidirectional memory for transmitting the amount of data, a communication processing device for controlling communication, and the communication processing device transmitting data. An index register for recording or reproducing the offset of the bidirectional memory for performing the communication processing. And an index register for recording or reproducing the number of completed data, and the communication processing device determines whether the data transmission order is correct by comparing the transmitted data quantity and the communication processed data quantity. A data storage device characterized in that it is configured to perform

2) A data processing device for controlling data, a plurality of main memories for recording or reproducing data, and an offset of a memory in which the data processing device stores data. Or an index register for reproducing, a plurality of bidirectional memories for transmitting data, an index register for recording or reproducing the offset of the bidirectional memory for transmitting data by the data processing device, and A two-way memory for transmitting the quantity of data, a communication processing device for controlling communication, and an index register for recording or reproducing the offset of the two-way memory for transmitting data by the communication processing device. An index for recording or reproducing the quantity of data for which the communication processing device has completed communication processing. The communication processing device comprises a bidirectional memory for transmitting the occurrence of an abnormality to the data processing device, and the communication processing device compares the number of transmitted data with the number of data subjected to the communication processing. The data storage device is configured to determine whether the data transmission order is correct or not, and to transmit the occurrence of the abnormality to the data processing device via the bidirectional memory.

[0010] The effect of this is that the processing means for controlling the communication compares the number of transmitted data with the number of data that has completed the communication processing by such a solving means to determine whether the order of the transmitted data is normal. Can be determined. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment according to claim 1 or 2 of the present invention in a manner similar to FIG.
1 'is a data processing device, 12' is a communication processing device, 2 is a main memory, 31, 32 'and 33 are bidirectional memories, 41 and 4,
2, 43, and 44 indicate index registers, and 5 indicates a communication interface. Assume that the relationship between the number m of internal memories of the main memory 2 and the number n of internal memories of the bidirectional memory 31 satisfies m> n, as in the conventional example. For convenience of explanation, the bidirectional memory 32 'is denoted by DP, and the bidirectional memory 33 is denoted by EF. The operation of FIG. 1 is divided into a data control unit and a communication control unit, and the operation will be described below with reference to the flowchart of FIG. However, the initial values of the bidirectional memories DP and EF are set to 0.

The data processing unit 11 'of the data control unit sets the index register X1 for storing the offset of the main memory 2 to 0, and sets the start address MM +
Make it accessible from 0. Next, the bidirectional memory E
The value of F is read to determine whether the communication control unit has detected an abnormality.
If the value of EF is 1, it is determined that an abnormality has occurred and E
F is set to 0, and the processing of the data control unit is terminated. However, since the initial value of EF is 0, the value of the bidirectional memory DP indicating the number of data which has been written to the bidirectional memory 31 is read next, and the communication control unit is read. It is determined whether the process has been completed. D
If P is not 0, the process goes to the wait state assuming that the processing of the communication control unit is not completed. However, since the initial value of the DF is 0, the data processing device 11 ′ Is set to 0 so that the bidirectional memory 31 can be accessed from the start address DM + 0. The data processing device 11 ′ reads the data at the address MM + 0 of the main memory 2 and writes the data at the address DM + 0 of the bidirectional memory 31. 1 is added to the original value of each of X1 and Y1 and stored, and first, the value of X1 is the total number of memories in the main memory 2, that is, m
Is reached, and it is determined whether or not all data transmission to the bidirectional memory 31 has been completed.

If the data transmission for all the memories of the main memory 2 is not completed, the value of Y1 reaches the total number of memories of the bidirectional memory 31, ie, n, and the value of the bidirectional memory 31 can be transmitted at one time. It is determined whether data writing has been completed. If the n data transmissions have not been completed, the process is repeated until the writing of the n data is completed. When n data transmissions have been completed, X1 is written to DP and D
It waits until P is 0, that is, the processing of the communication control unit is completed. After the DP becomes 0, the process is repeated until the total number of data in the main memory 2, that is, the data transmission of m data is completed. However, if the EF is 1, that is, if an abnormality of the communication control unit is detected, the process is performed. Interrupt. When m data transmissions have been completed, X1 is written to DP, and the processing of the data control unit ends.

The data processing unit 12 'of the communication control unit firstly stores an index register X for counting the number of transmission data.
2 is set to 0, and when the DP is 0, that is, when there is no data transmission from the data control unit, a standby state is set until transmission is performed. When the value of DP becomes a value other than 0, it is next determined whether or not the value of DP is normal. The value DP written from the data processing device 11 'is the number of data X2 for which transmission processing has been completed and the number of data n which can be transmitted at one time via the bidirectional memory 31.
If the sum is less than or equal to the sum, the data is normal, and if the sum is exceeded, the number of data transmitted is excessive with respect to the number of data subjected to the transmission processing. In the communication control unit. If there is no abnormality, it is determined whether or not the next transmitted data number DP is equal to or less than the data number X2 for which transmission processing has been completed. DP is X
If the number is larger than 2, the data is normal, and if the DP is less than X2, the number of data transmitted is too small compared to the number of data subjected to the transmission processing. The process of the write communication control unit ends. If there is no abnormality, the index register Y2 for storing the offset of the bidirectional memory 31 is set to 0 so that the bidirectional memory 31 can be accessed from the start address DM + 0. The communication processing device 12 reads the data at the address DM + 0 of the bidirectional memory 31, writes the data at the communication interface COM, and transmits the data. X2,
1 is added to the original value of Y2 and stored, and first, X2
Has reached the total memory number m of the main memory 2, and it is determined whether or not all data writing to the communication interface COM has been completed.

If the data transmission for the total number of memories in the main memory 2 is not completed, the value of Y2 reaches the total number of memories in the bidirectional memory 31, that is, n, so that the bidirectional memory 31 can transmit at one time. It is determined whether the reading of data is completed. If the transmission of n data has not been completed, the processing is repeated until the reading of n data is completed. When n data transmissions are completed, 0 is written to DP, and DF
Is 1, that is, from the data control unit to the bidirectional memory 31 again.
It is in a waiting state until the writing of data to is completed. D
After P becomes 1, the process is repeated until all the data in the main memory 2, that is, n data transmissions, is completed. Interrupt. When n data transmissions have been completed, 0 is written to DP, and the processing of the communication control unit ends.

[0016]

As described above in detail, according to the present invention, the number of transmitted data is compared with the number of data for which communication processing has been completed, thereby controlling communication with a processing device which controls data due to disturbance or the like. When synchronization cannot be established between the processing devices, an abnormality can be detected and a device having a simple configuration capable of interrupting the process can be provided, and the practical effect is remarkable. In this example, data transmitted from the data processing device is transmitted by the communication processing device. However, as is apparent from the configuration, the present invention is also applied to a device that transmits data received by the communication processing device to the data processing device. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a flowchart for explaining the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 11 data processing device 11 'data processing device 12 communication processing device 12' communication processing device 2 main memory 31 bidirectional memory 32 bidirectional memory 32 'bidirectional memory 33 bidirectional memory 41 index register 42 index register 43 index register 44 index register 5 Communication interface

Claims (2)

[Claims] 1. A data processing apparatus for controlling data, a plurality of main memories for recording or reproducing data, and an apparatus for recording or reproducing offsets of a memory in which the data processing apparatus stores data. An index register; a plurality of bidirectional memories for transmitting data; an index register for recording or reproducing an offset of the bidirectional memory for transmitting data by the data processing device; and transmitting a quantity of data. Memory for controlling communication, a communication processing device for controlling communication, an index register for recording or reproducing an offset of the bidirectional memory for transmitting data by the communication processing device, and the communication processing device And an index register for recording or reproducing the amount of data that has completed communication processing. A data processing device configured to determine whether the data transmission order is correct by comparing the number of transmitted data with the number of data subjected to the communication processing by the communication processing device. 2. A data processing apparatus for controlling data, a plurality of main memories for recording or reproducing data, and an apparatus for recording or reproducing offsets of a memory in which the data processing apparatus stores data. An index register; a plurality of bidirectional memories for transmitting data; an index register for recording or reproducing an offset of the bidirectional memory for transmitting data by the data processing device; and transmitting a quantity of data. Memory for controlling communication, a communication processing device for controlling communication, an index register for recording or reproducing an offset of the bidirectional memory for transmitting data by the communication processing device, and the communication processing device An index register for recording or reproducing the quantity of data for which communication processing has been completed; The communication processor comprises a two-way memory for transmitting the occurrence of an abnormality to the data processor, and the communication processor compares the number of transmitted data with the number of data that has been subjected to the communication processing to thereby determine the data transmission order. A data storage device configured to determine whether the data processing device is correct or not, and to transmit the occurrence of the abnormality to the data processing device via the bidirectional memory.