JPH11202841A - Device for supplying polyphase image signal to liquid crystal display device making display with polyphase image signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a polyphase image signal for shifting an image of the liquid crystal display device in one pixel unit. SOLUTION: Delay digital image signals Φ2d, Φ3d, Φ4d, Φ5d, Φ6d, Φ7d, Φ8d...Φnd which are delayed one sample cycle behind digital image signals Φ2, Φ3, Φ4, Φ5, Φ6, Φ7, Φ8...Φn of respective phases except the 1st phase of an N-phase digital image signal to be displayed by the liquid crystal display device by (N-1) data latches 19 to 35 are generated. To input terminals (a) to (h) on N mutiplexers 28 to 25. the digital image signals Φ1, Φ2, Φ3, Φ4, Φ5, Φ6, Φ7, Φ8...Φn and delay digital image signals Φ1d, Φ2d, Φ3d, Φ4d, Φ5d, Φ6d, Φ7d, Φ8d...Φnd are inputted in the distribution style shown in the figure 1. Digital signals supplied to input terminals of the same sign of the N multiplexes 28 to 35 are selected at the same time and digital image signals Φ1', Φ2', Φ3', Φ4', Φ5', Φ6', Φ7', Φ8'...Φn' of new phases are outputted from the N multiplexes 28 to 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for supplying a multi-phase image signal to a liquid crystal display device in which display is performed by the multi-phase image signal.

[0002]

2. Description of the Related Art A voltage applied to each pixel is applied to an intersection of a signal electrode (signal line) and a scanning electrode so that pixels arranged vertically and horizontally are completely separated and driving without crosstalk is performed. In an active matrix type liquid crystal display device provided with intermittent switches [for example, a transistor switch (thin film transistor: TFT switch, MOS transistor switch) and the like], a storage element that holds a voltage corresponding to an image signal for each pixel In the case where the frequency characteristic of the image signal is poor or the response of the switch of the transistor for switching the pixel is poor, an image signal to be displayed conventionally is converted into a multi-phase signal, for example, an N-phase (N Is a natural number of 2 or more), so that the occupied frequency band of the image signal for each phase is
2. Description of the Related Art An image signal reduced to 1 / N of the occupied frequency band of an original image signal is supplied to a liquid crystal display device.

FIG. 2 is a block diagram showing a schematic configuration of an active matrix type liquid crystal display device to which multi-phase image signals are supplied and a driving circuit. In FIG. Denotes a horizontal drive unit, 3 denotes a vertical drive unit, 4 denotes a drive signal source, and 5 denotes an image signal source. In the active matrix type liquid crystal display device 1 described above, liquid crystal is sealed between a pair of substrates, a common electrode is disposed on one of the pair of substrates, and A pixel electrode provided corresponding to each of the pixels arranged vertically and horizontally, a storage element connected to the pixel electrode, and a signal line # H1 for supplying an image signal to the storage element. , #
H2 ... # H1920 (1920 = N) and address lines # V1, # V2 ... # V1035 for selecting storage elements
(1035 = Q). Furthermore, TFT
Is a switch thin film transistor provided for each pixel, and CS is a storage element (capacitance) provided for each pixel.

[0004] In FIG. 2 (and FIG. 3), a horizontal driving unit 2 receives a start pulse H-ST of a horizontal shift register 9 (FIG. 3) and a two-phase clock pulse H- C1, H-C2, a shift direction control signal R / L-CTL, etc., are provided, and an image signal obtained by polymorphing an image signal to be displayed by the transmission line 8 from the image signal source 5. [In the following description, eight phases (N
= 8) is also supplied. FIG. 3 is a block diagram mainly illustrating a specific configuration of the horizontal drive unit 2 in FIG. 2. In FIG. 3, reference numeral 1 denotes an active matrix type liquid crystal display device 1; , P2, P3... P1920 are 1 in the active matrix type liquid crystal display device 1 in FIG.
The pixel array in the row is shown as a representative example. # H1 ... #
H16 ... # H1913 ... correspond to the N signal lines # H1, # H2 ... # H1920 shown in FIG.

By the way, 1920 (N) liquid crystal display devices 1 arranged in the horizontal direction of the active matrix type liquid crystal display device 1 are arranged.
1920) signal lines # H1, #H provided between the horizontal drive unit 2 and the active matrix type liquid crystal display device 1 in correspondence with the pixels P1, P2.
2. The pixel P described above performed by # H1920
1, P2... P1920 are supplied with image signals in the following manner.
When the image signal is single-phase, the signal lines # H1, # H2,... # H1920 are sequentially selected one by one on the time axis by the shift operation of the shift register 9 provided in the horizontal drive unit 2. , One by one pixels P1, P2,.
An image signal is supplied to P1920.
When the active matrix type liquid crystal display device 1 performs a display operation with a multi-phase image signal, the number (N) of pixels corresponding to the number of phases (N phases) of the image signal is defined as one group. An image signal is supplied to the pixels forming a group in such a manner that the group of pixels is simultaneously selected.

A case where the above-mentioned active matrix type liquid crystal display device 1 performs a display operation with a multi-phase image signal will be specifically described as follows. Assume that the number of phases of an image signal to be displayed is N, and the total number of pixels P1, P2,... Arranged in the horizontal direction of the active matrix type liquid crystal display device 1 is P. , The number of pixels of a group of pixels simultaneously selected on the time axis is P / N. For example, if the image signal is 8
The pixels P1 and P2 which are divided into phases (N = 8) and are arranged in the horizontal direction of the active matrix type liquid crystal display device 1
If the total number P of... Is 1920, the 1920 pixels arranged in the horizontal direction of the active matrix type liquid crystal display device 1 are grouped into eight pixels.
It is divided into 20/8 = 240 pixel groups.
The output lines # 1H, # 2H... # 240H connected from the shift register 9 to the level shifter 10 in FIG. 3 are 240 signal lines (signal electrodes) provided corresponding to the 240 pixel groups described above. It is. The number of pixels arranged in the vertical direction of the active matrix type liquid crystal display device 1 is Q.

Each output line # 1 of the shift register 9
The output signals supplied from H, # 2H... # 240H to the level shifter 10 are continuous N (N = N in the example) constituting a specific group of pixels for each of the output lines.
8) Used as an open / close control signal of the switch SW that operates so that the pixels are simultaneously selected. ,... # 8 of the N-phase (N = 8 in the example) supplied from the image signal source 5 to the horizontal drive unit 2 in FIG. 2 are transmitted. The transmission line 8 (corresponding to the transmission line 8 shown in FIG. 1) is shown. The first-phase image signal in the N-phase image signal is supplied to the signal line # H1 by a switch SW that closes when an output appears on the output line # 1H of the shift register 9, and the signal of the shift register 9 The output line #K of the shift register 9 is supplied to the signal line # H9 by the switch SW that closes when an output appears on the output line # 2H, and so on.
H (where K is 1, 2,..., 240) is closed by a switch SW that closes when an output appears on the signal line #H [1+ (K
-1) N] is supplied with the image signal of the first phase.

The image signal of the second phase in the N-phase (N = 8 in the example) image signal supplied from the image signal source 5 to the horizontal drive unit 2 is the output line # 1H of the shift register 9.
Is supplied to the signal line # H2 by a switch SW that closes when an output appears on the output line # 2, and is supplied to the signal line # H10 by a switch SW that closes when an output appears on the output line # 2H of the shift register 9. As described above, the output line #KH of the shift register 9 (where K is 1, 2,...)
The image signal of the second phase is supplied to the signal line #H [2+ (K-1) N] by the switch SW which closes when the output appears at 240). The image signal of the third phase in the N-phase (N = 8 in the example) image signal supplied to the horizontal drive unit 2 from the image signal source 5 is output to the output line # 1H of the shift register 9. It is supplied to the signal line # H3 by the switch SW that closes when it appears, and is supplied to the signal line # H11 by the switch SW that closes when the output appears on the output line # 2H of the shift register 9, and so on. A switch SW that closes when an output appears on the output line #KH (where K is 1, 2,..., 240) of the shift register 9 is connected to the signal line #H [3+ (K−1) N].
A phase image signal is supplied.

Similarly, the image signal of the eighth phase in the N-phase (N = 8 in the example) image signal supplied from the image signal source 5 to the horizontal drive unit 2 Switch S that closes when an output appears on output line # 1H
The output line of the shift register 9 is supplied to the signal line # H8 by W, and is supplied to the signal line # H16 by a switch SW that closes when an output appears on the output line # 2H of the shift register 9, and so on. #KH (however,
The image signal of the eighth phase is supplied to the signal line #H [8+ (K-1) N] by the switch SW which closes when the output appears at K (1, 2,... 240). As mentioned above,
The image signal of each phase in the N-phase (N = 8 in the example) image signal supplied to the horizontal drive unit 2 from the image signal source 5 is output to the output line #KH of the shift register 9 (where K is 1, 2). .. 240), N switches SW which are simultaneously closed when an output appears on the N signal lines #H [i
+ (K-1) N] (where i is a number from 1 to 8).

On the other hand, a vertical drive section 3 shown in FIG. 2 is connected to a start signal VST of a vertical shift register and a two-phase clock pulse VC by a transmission line 7 from a drive signal source 4.
1, VC2. Then, the output is supplied from the vertical shift register provided in the vertical drive unit 4 to the sequential scanning electrodes # V1, # V2,... # V1035.
In the horizontal scanning direction, the number of pixels corresponding to the number of phases of the image signal is simultaneously selected as a group of pixels, and scanning is performed in the vertical direction while displaying the pixels forming a group one after another. , An image is displayed.

By making the image signal multi-phase as described above, the image signal for each phase supplied to the active matrix type liquid crystal display device 1 is occupied narrower than the occupied frequency band of the original image signal. Since the image signal is in the frequency band, the frequency characteristic of the storage element that holds the voltage corresponding to the image signal for each pixel in the active matrix type liquid crystal display device 1 is poor, or a transistor for switching the pixel is used. Even if the response of the switch is poor, it is possible to display a good display image.

[0012]

By the way, a display image of each of the three primary colors of the additive color mixture is displayed on an individual active matrix type liquid crystal display device, and the three active matrix type liquid crystals are displayed. In a projection display device configured to superimpose a display image of each of the three primary colors of the additive color mixture displayed on the display device on a screen to project a color image on the screen,
If the display images of the three primary colors of the additive color mixture displayed on the three active matrix type liquid crystal display devices are not accurately superimposed, a color shift occurs in the projected color image.

However, in order to avoid the above-mentioned color shift,
It is extremely difficult to accurately adjust the mounting positions of the three active matrix type liquid crystal display devices in units of pixel pitch. Therefore, in an active matrix type liquid crystal display device in which a display image is formed by a single-phase image signal, the horizontal shift register 9 (see FIG. 3) of the horizontal drive unit 2 provided in the active matrix type liquid crystal display device. ), The time position of the start pulse H-ST is changed on the time axis, so that the display image of each of the three primary colors of the additive color mixture displayed on the three active matrix type liquid crystal display devices is displayed. The superposition (registration) is performed in a good state.

However, when three active matrix type liquid crystal display devices used as components of the projection type display device display a display image by a multi-phased image signal. As described above, the horizontal shift register 9 of the horizontal drive unit 2 provided in the active matrix type liquid crystal display device (FIG. 3)
When the time position of the start pulse H-ST is changed on the time axis, the registration adjustment between the primary color images constituting the color image cannot be satisfactorily performed. Further, even in a projection device using only one active matrix type liquid crystal display device, if the projection device displays a display image by a multi-phased image signal, it may be displayed on a screen in units of one pixel. Position adjustment that moves the position of the image in the horizontal direction cannot be performed. SUMMARY OF THE INVENTION The present invention provides an apparatus for supplying a multi-phase image signal to a liquid crystal display device in which display is performed using a multi-phase image signal which can solve the above-described problems.

[0015]

According to the present invention, a liquid crystal is sealed between a pair of substrates, a common electrode is arranged on one of the pair of substrates, and a common electrode is arranged on the other substrate. (P horizontal x Q vertical) Pixel electrodes provided individually corresponding to the pixels and storage elements connected to the above-mentioned pixel electrodes are separated into N phases (N is a natural number of 2 or more). (P / N) N signal lines for supplying the multi-phased image signal to the storage element and Q address lines for selecting the storage element are provided. ,
For a liquid crystal display device in which light modulation by liquid crystal is performed based on the electric charge stored in the storage element in accordance with the voltage of each phase of the input image signal that has been converted into a polyphase, An image signal supply device for supplying a phase image signal, wherein each phase of a multi-phased N-phase digital image signal to be displayed by a liquid crystal display device, excluding a reference phase digital image signal. (N-1) time delay means for giving a time delay of one sampling period to each of the digital signals, and an N-phase digital image signal and (N-1) Signal selection means for selecting a predetermined one of the digital image signals output from the time delay means, and a signal control means for controlling a horizontal position of an image in the liquid crystal display device. Signal selection means And it is configured to output as a digital image signal of N-phase digital image signal of a predetermined phase to a predetermined is subject to signal processing.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a liquid crystal display device for displaying images by using a multi-phase image signal according to the present invention; This will be described in detail. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a supply device of a multi-phase image signal for a liquid crystal display device in which display is performed by a multi-phase image signal according to the present invention. In FIG.
Reference numeral 17 denotes a digital image signal Φ1, Φ2, Φ3, Φ4, Φ5, Φ6, Φ7,
Φ8 (when N = 8). Φ1 mentioned above
Is a digital image signal of each phase of the first phase digital image signal, Φ2 is a digital image signal of each phase of the second phase digital image signal, and similarly, Φ3 to Φ8 are third to eighth phases, respectively. 3 shows a phase digital image signal. In addition,
In the following example, it is assumed that the multi-phase digital image signal is an 8-phase digital image signal (when N = 8).

In FIG. 1, reference numerals 19 to 25 denote digital image signals .PHI.1, .PHI.2, .PHI.3, .PHI.4, .PHI.5, .PHI.6, .PHI.7, and .PHI.8 of each phase of the multi-phase digital image signal.
(N = 8) of the first phase digital image signal Φ1
Φ2, Φ3, Φ4, Φ
5, Φ6, Φ7, Φ8 (in the case of N = 8) (N−1) data latches (digital image signals Φ2 to Φ8 are given a time delay of one sampling cycle, respectively. , N-1 delay circuits for generating the delayed digital image signals Φ2d to Φ8d), and the data latch 19 to which the second-phase digital image signal Φ2 is supplied via the input terminal 11 has the second-phase digital image signal Φ2d. The image signal Φ2 is time-delayed by one sampling period to output a second-phase delayed digital image signal Φ2d.

In the data latch 20 to which the third-phase digital image signal Φ3 is supplied via the input terminal 12,
The third-phase delayed digital image signal Φ in a state where the third-phase digital image signal Φ3 is time-delayed by one sampling period
In the data latch 21 that outputs 3d and further receives the fourth-phase digital image signal Φ4 via the input terminal 13, the fourth-phase digital image signal Φ4 is time-delayed by one sampling period. A fourth phase delayed digital image signal Φ4d is output. Hereinafter, similarly, the input terminal 14
Through 17 through 5 to 8 phase digital image signals Φ5 to Φ
8 are supplied to the data latches 22 to 25,
The phase-shifted digital image signals Φ5d to Φ8d are output in a state where the phase digital image signals Φ5 to Φ8 are delayed by one sampling period.

Reference numerals 28 to 35 denote eight (N = 8 in the example) multiplexers.
Has eight input terminals a to h and one output terminal y. The eight input terminals a to h include:
An input digital image signal of each phase is supplied in a distribution manner as illustrated in FIG. And the above 8
The input digital image signal of each phase supplied to the input terminals a to h is supplied from a control unit (not shown) to the control signal input terminal s of the multiplexer via the input terminal 27 of the selection control signal. The signal is selected by the selection control signal and output to the output terminal y. The multiplexer 28
Outputs a new first-phase digital image signal Φ1 ′ from the output terminal y, and outputs a new second-phase digital image signal Φ2 ′ from the output terminal y of the multiplexer 29. And multiplexers 30 to 35
, New digital image signals Φ3 ′ to Φ8 ′ of the third to eighth phases are output.

That is, to the eight (N = 8) input terminals a, b, and kh of the multiplexer 28, the first-phase digital image signal Φ1 (input Terminal a), an eighth-phase delayed digital image signal φ8d output from the data latch 25 (input terminal b), a seventh-phase delayed digital image signal φ7d output from the data latch 24 (input terminal c), and a data latch 2
6d delayed digital image signal Φ6d output from
(Input terminal e), the fifth output from the data latch 22
Phase delayed digital image signal φ5d (input terminal f), fourth phase delayed digital image signal φ4d output from data latch 21 (input terminal g), third phase delayed digital image signal output from data latch 20 Φ3d (input terminal h) are individually supplied. In the multiplexer 28, one input digital signal selected by the selection control signal supplied to its control signal input terminal s is output from the output terminal y as a new first phase digital image signal Φ1 '.

The eight (N = 8) input terminals a, b, and kh of the multiplexer 29 are sequentially connected to the second phase digital image signal Φ supplied from the input terminal 11.
2 (input terminal a), first-phase digital image signal Φ1 (input terminal b) supplied from input terminal 10, and eighth-phase delayed digital image signal Φ8 output from data latch 25.
d (input terminal c), the seventh phase delayed digital image signal Φ7d output from the data latch 24 (input terminal d), and the sixth phase delayed digital image signal Φ6d output from the data latch 23 (input terminal e) , A fifth-phase delayed digital image signal Φ5d (input terminal f) output from the data latch 22, a fourth-phase delayed digital image signal Φ4d (input terminal g) output from the data latch 21, and an output from the data latch 20. 3rd phase delayed digital image signal Φ3
d (input terminal h) is individually supplied. In the multiplexer 29, one input digital signal selected by the selection control signal supplied to its control signal input terminal s is output from the output terminal y as a new second-phase digital image signal Φ2 ′.

Further, 8 of the aforementioned multiplexer 30
(N = 8) input terminals a, b, c to h
The third-phase digital image signal Φ3 (input terminal a) supplied from the input terminal 12 and the second phase digital image signal Φ3 supplied from the input terminal 11
Phase digital image signal Φ2 (input terminal b), input terminal 1
0, the first-phase digital image signal Φ1 (input terminal c), the eighth-phase delayed digital image signal Φ8d output from the data latch 25 (input terminal d), and the seventh digital image signal Φ8d (input terminal d) output from the data latch 24. Phase delayed digital image signal Φ
7d (input terminal e), the sixth-phase delayed digital image signal Φ6d output from the data latch 23 (input terminal f),
The fifth-phase delayed digital image signal φ5d (input terminal g) output from the data latch 22 and the fourth-phase delayed digital image signal φ4d (input terminal h) output from the data latch 21 are individually supplied. I have. Multiplexer 3
0, one input digital signal selected by the selection control signal supplied to its control signal input terminal s is:
From the output terminal y, a new third-phase digital image signal Φ3 ′
Output as

The eight multiplexers 31 (N =
8) The input terminals a, b, and c to h are sequentially connected to the fourth-phase digital image signal Φ4 (input terminal a) supplied from the input terminal 13 and the third-phase digital image signal Φ4 supplied from the input terminal 12. The digital image signal φ3 (input terminal b), the second phase digital image signal φ2 (input terminal c) supplied from the input terminal 11, and the first phase digital image signal φ1 (input terminal d) supplied from the input terminal 10. ), The eighth-phase delayed digital image signal φ8d (input terminal e) output from the data latch 25, the seventh-phase delayed digital image signal φ7d (input terminal f) output from the data latch 24, and the data latch 2
6d delayed digital image signal Φ6d output from
(Input terminal g), the fifth signal output from the data latch 22.
The phase delayed digital image signal Φ5d (input terminal h) is individually supplied. In the multiplexer 31, one input digital signal selected by the selection control signal supplied to its control signal input terminal s is output from the output terminal y as a new fourth-phase digital image signal Φ4 '.

Eight of the multiplexers 32 (N =
8) input terminals a, b, and c to h of the fifth-phase digital image signal Φ5 (input terminal a) supplied from the input terminal 14 and the fourth-phase digital image signal Φ5 supplied from the input terminal 13 sequentially. Digital image signal φ4 (input terminal b), third-phase digital image signal φ3 (input terminal c) supplied from input terminal 12, and second-phase digital image signal φ2 (input terminal d) supplied from input terminal 11. ), The first-phase digital image signal Φ1 (input terminal e) supplied from the input terminal 10, the eighth-phase delayed digital image signal Φ8d (input terminal f) output from the data latch 25, and the output from the data latch 24. The obtained seventh-phase delayed digital image signal Φ7d (input terminal g) and the sixth-phase delayed digital image signal Φ6d (input terminal h) output from the data latch 23 are individually supplied. In the multiplexer 32, one input digital signal selected by the selection control signal supplied to the control signal input terminal s of the multiplexer 32 is transmitted from the output terminal y to a new fifth digital signal.
The phase digital image signal Φ5 ′ is output.

Eight of the multiplexers 33 (N =
8) input terminals a, b, and c to h in order, the sixth-phase digital image signal Φ6 (input terminal a) supplied from the input terminal 15 and the fifth-phase digital image signal Φ6 supplied from the input terminal 14. The digital image signal Φ5 (input terminal b), the fourth phase digital image signal Φ4 supplied from the input terminal 13 (input terminal c), and the third phase digital image signal Φ3 supplied from the input terminal 12 (input terminal d) ), The second-phase digital image signal Φ2 (input terminal e) supplied from the input terminal 11, and the first-phase digital image signal Φ1 supplied from the input terminal 10.
(Input terminal f), the eighth signal output from the data latch 25.
The phase delayed digital image signal φ8d (input terminal g) and the seventh phase delayed digital image signal φ7d (input terminal h) output from the data latch 24 are individually supplied.
In the multiplexer 33, one input digital signal selected by the selection control signal supplied to the control signal input terminal s thereof is output from the output terminal y as a new sixth-phase digital image signal Φ6 '.

Eight of the multiplexers 34 (N =
8) The input terminals a, b, and c to h are sequentially connected to the seventh-phase digital image signal Φ7 (input terminal a) supplied from the input terminal 16 and the sixth-phase digital image signal Φ7 supplied from the input terminal 15. The digital image signal Φ6 (input terminal b), the fifth phase digital image signal Φ5 supplied from the input terminal 14 (input terminal c), and the fourth phase digital image signal Φ4 supplied from the input terminal 13 (input terminal d) ), The third-phase digital image signal Φ3 supplied from the input terminal 12 (input terminal e), and the second-phase digital image signal Φ2 supplied from the input terminal 11.
(Input terminal f), first phase digital image signal Φ1 (input terminal g) supplied from input terminal 10, data latch 2
8d delayed digital image signal Φ8d output from 5
(Input terminal h) are individually supplied. In the multiplexer 34, one input digital signal selected by the selection control signal supplied to the control signal input terminal s of the multiplexer 34 outputs a new seventh-phase digital image signal Φ from the output terminal y.
Output as 7 '.

Eight of the multiplexers 35 (N =
8) The input terminals a, b, and c to h are sequentially connected to the eighth-phase digital image signal Φ8 (input terminal a) supplied from the input terminal 17 and the seventh-phase digital image signal Φ8 supplied from the input terminal 16. The digital image signal Φ7 (input terminal b), the sixth phase digital image signal Φ6 supplied from the input terminal 15 (input terminal c), and the fifth phase digital image signal Φ5 supplied from the input terminal 14 (input terminal d) ), The fourth phase digital image signal Φ4 supplied from the input terminal 13 (input terminal e), and the third phase digital image signal Φ3 supplied from the input terminal 12.
(Input terminal f), the second-phase digital image signal Φ2 (input terminal g) supplied from the input terminal 11, and the first-phase delayed digital image signal Φ1 (input terminal h) supplied from the input terminal 10. Supplied individually. Multiplexer 3
At 5, one input digital signal selected by the selection control signal supplied to its control signal input terminal s is:
From the output terminal y, a new 8th-phase digital image signal Φ8 ′
Output as

As described above, the eight multiplexers 28
In each of the eight input terminals a to h shown in FIGS. 1 to 35, the input digital signals supplied to the eight input terminals in each of the multiplexers 28 to 35 in FIG. Since the N input digital signals whose input digital signal combination modes are changed in an order according to the rule of changing the input digital signal combination mode are distributed and supplied to the N input terminals a to h. Yes,
In the eight multiplexers 28 to 35 described above, one specific terminal of the eight input digital signals (the same terminal is a terminal indicated by the same terminal code a, b, c...) To generate a digital image signal of a new specific phase.

The above-mentioned eight multiplexers 28 to 35
Are selected by a selection control signal supplied from a control unit (not shown) to a control signal input terminal s of each multiplexer via a selection control signal input terminal 27.
If the input digital signal of one specific terminal among the input digital signals is the input digital signal supplied to the input terminal a, the output terminals y of the eight multiplexers 28 to 35 are used. The new digital image signals Φ1 ′ to Φ8 ′ of the respective phases output from are used as digital image signals for generating an image without any pixel displacement.

Further, eight multiplexers 28 to 35
When the input digital signal supplied to the input terminal b is selected as the input digital signal of one specific terminal among the eight input digital signals, the above-mentioned eight multiplexers 28 To 35 new digital image signals φ1 ′ to φ8 ′ output from the output terminals y.
Is used as a digital image signal for generating an image in which pixels are displaced by one pixel in the horizontal direction.
Further, when the eight multiplexers 28 to 35 select the input digital signal supplied to the input terminal c as the input digital signal of one specific terminal among the eight input digital signals. The new digital image signals Φ1 ′ to Φ8 ′ of the respective phases output from the output terminals y of the eight multiplexers 28 to 35 generate an image in which the pixels are displaced in the horizontal direction by two pixels. It is used as a digital image signal in the case.

Hereinafter, similarly, the eight multiplexers 28 to 35 are supplied to the input terminals d to h as input digital signals of one specific terminal among the eight input digital signals. When the input digital signal is selected, the new digital image signals Φ1 ′ to Φ8 ′ of the respective phases output from the output terminals y of the eight multiplexers 28 to 35 have 3 to 7 pixels, respectively. It is used as a digital image signal for generating an image in which pixels are displaced only in the horizontal direction. In order to displace the image in the horizontal direction by 8 pixels or a multiple of 8 pixels when N = 8, it is necessary to start the horizontal shift register 9 of the horizontal drive unit 2 provided in the active matrix type liquid crystal display device. What is necessary is just to change the time position of the pulse H-ST as predetermined.

The displacement of pixels in the horizontal direction in units of eight pixels by changing the time position of the start pulse H-ST of the horizontal shift register 9 in a predetermined manner, and 1 by the device shown in FIG. Combining horizontal pixel displacement with pixel by pixel horizontal displacement allows any number of pixels to be displaced in the horizontal direction. The new digital image signals φ1 ′ to φ8 ′ of the respective phases output from the output terminals y of the multiplexers 28 to 35 in FIG. 1 are output via corresponding output terminals 36 to 43, respectively. The signal is supplied to a processing circuit, subjected to predetermined signal processing, and supplied as an 8-phase analog image signal to an active matrix type liquid crystal display device.

[0033]

As will be apparent from the above description, the apparatus for supplying a multi-phase image signal to a liquid crystal display device according to the present invention for displaying on the basis of the multi-phase image signal is capable of displaying an image. In order to easily generate a multi-phase image signal that can be displaced in the horizontal direction in pixel units, each of the three primary colors of additive color mixture is used.
The display image for each primary color can be accurately adjusted by displacing the display image for each pixel, and therefore, the superimposition of the display images for each of the three primary colors of the additive color mixture displayed on the three active matrix type liquid crystal display devices. (Registration) can be easily performed in a favorable state, and even in a projection device using only one active matrix type liquid crystal display device, a display image can be formed by a multi-phase image signal. Even in the case of display, it is possible to easily perform the position adjustment such that the position of the image on the screen is moved in the horizontal direction in units of one pixel. Provided is a device for supplying a polyphased image signal to a liquid crystal display device in which display is performed by a polyphased image signal capable of favorably solving points.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a supply device of a multi-phase image signal for a liquid crystal display device in which display is performed by a multi-phase image signal.

FIG. 2 is a block diagram illustrating a schematic configuration of an active matrix type liquid crystal display device to which a multi-phase image signal is supplied and a driving circuit.

FIG. 3 is a block diagram illustrating a schematic configuration of an active matrix liquid crystal display device to which a multi-phase image signal is supplied and a part of a driving circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Active matrix type liquid crystal display device, 2 ... Horizontal drive part, 3 ... Vertical drive part, 4 ... Drive signal source, 5 ... Image signal source, 6-8 ... Transmission line, 9 ... Horizontal shift register, 1
0: level shifter, 19 to 25: data latch, 28 to
35 ... multiplexer,

Claims (1)

[Claims] 1. A liquid crystal is sealed between a pair of substrates,
A common electrode is arranged on one of the pair of substrates, and (P × H × Q) is disposed on the other substrate.
) Pixels and a memory element connected to the pixel electrode and N-phase (N is a natural number of 2 or more) to form a multi-phase. (P /) for supplying an image signal to the above-described storage element.
N) N signal lines and Q address lines for selecting storage elements are provided, and the storage is performed in accordance with the voltage of each phase of the multi-phase input image signal. An image signal supply device for supplying a multi-phased N-phase image signal to a liquid crystal display device in which light modulation by liquid crystal is performed based on electric charges stored in an element. In the multi-phased N-phase digital image signal targeted for (1), each of the digital signals of each phase other than the digital image signal of the reference phase is given a time delay of one sampling period (N−1). , And an N-phase digital image signal (N−
1) signal selecting means for selecting a predetermined one of the digital image signals output from the time delay means, and corresponding to a position control signal of an image in a horizontal direction in the liquid crystal display device. The display is performed by the above-described signal selecting means by using a multi-phase image signal that outputs a digital image signal of a predetermined phase as an N-phase digital image signal to be subjected to signal processing. A device for supplying a multi-phase image signal to a liquid crystal display device to be performed.