JPH11194151A - Test method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a failed part surely without causing any oscillation at the time of testing a semiconductor integrated circuit including a loop circuit. SOLUTION: A semiconductor integrated circuit comprises FF 3A-3D operable with a CLK, and combination circuits 2A-2C producing the logical output of CLK or internal data with IN1-IN6 or normal output DOT and the CLK is delivered through the combination circuits 2A-2C to the FF. Each FF has a first clock terminal CLK and a second clock terminal TLK wherein a test clock is fed to the TCK after the IN1-IN6 are held by providing a signal of specified value in order to operate the FF circuits sequentially from the input side. Test is performed by comparing the output value to an output terminal OUT1, OUT2 with a preset expected value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a semiconductor integrated circuit, and more particularly to a test method for easily testing a semiconductor integrated circuit having a combinational circuit and a sequential circuit.

[0002]

2. Description of the Related Art Conventionally, such a test method has been used to easily detect a faulty portion of a transistor occurring in a manufacturing stage of a semiconductor integrated circuit having a combinational circuit and a sequential circuit by using a test pattern. In addition, the number of test patterns becomes complicated and enormous as the scale of integrated circuits increases in recent years.

In order to solve such a problem, a scan path circuit method has been adopted for the purpose of simplifying the creation of a test pattern in the test method and reducing the number of patterns.

The above-mentioned specific example is disclosed in, for example,
It is known in, for example, Japanese Patent Publication No. 72290.

FIG. 8 is a semiconductor integrated circuit diagram for explaining an example of the related art. As shown in FIG. 8, a conventional semiconductor integrated circuit 14 includes a combination circuit unit 1 connected to external input terminals IN1 to IN4 and external input terminals IN5 and IN6.
2A and 12B, the outputs Q1 and Q2 of the combinational circuit 11A and the external scan path
A flip-flop (F) connected to a shift data input terminal ISIN, an external shift / test mode switching input terminal ISMC, an external scan clock ISCK, and an external scan path test / normal mode switching input terminal IAMC.
F) Combination circuit 1 that supplies 13A and normal output terminal DOT of FF 13A as input I1 and supplies outputs Q1 and Q2
1B and similar FFs 13B to 13D and combination circuit 1
1C, and outputs the external scan path / shift data output terminal DSOT and the external output terminals OUT1 and OUT1.
2 is provided.

In this semiconductor integrated circuit 14, FF1
When the shift / test mode switching input SMC is at the active level, the scan path circuit formed by 3A to 13D reads data from the scan path shift data input SIN, and scans the next FF from the scan path shift data output SOT. The FFs 13A to 13D are all connected so as to be supplied to the campus shift data input SIN, and the external input terminals IN1 to IN6 and the external output terminal OUT
1 and OUT2 and a combination of the combinational circuits 11A to 11C.

That is, in the semiconductor integrated circuit 14, FFs 13A to 13A as circuits for realizing desired functions are provided.
3D operates with a clock signal input to a clock terminal CLK. More specifically, the signal input to the normal input terminal DIN is read by the clock CLK and output to the normal output terminal DOT.

In detecting a failure of the combinational circuits 11A to 11C in the semiconductor integrated circuit 14, an external scan path test / normal mode switching input terminal I
When the shift mode is set by the external shift / test mode switching input terminal ISMC after the scan path mode is set by the AMC, the FFs 13A to 13D operate by the scan clock input to the external scan clock terminal ISCK, and the external scan path shift data The scan path shift data input to the input terminal ISIN is sequentially shifted and set in the order of FFs 13A → 13B → 13C → 13D.

When a test mode is set by an external shift / test mode switching input terminal ISMC,
F13A to 13D are external scan clock terminals ISCK
It operates with the scan clock input to the normal input terminal DIN, reads the signal input to the normal input terminal DIN with the scan clock, and outputs the signal to the normal output terminal DOT.

Further, when the shift mode is set by the external shift / test mode switching input terminal ISMC,
FFs 13A to 13D are external scan clock terminals ISC
Operated by the scan clock input to K, and FF1
The data held in 3A to 13D is supplied to the external scan path shift data output terminal DSOT by FF13D → 13C →
13B → 13A in order and outputs the data. The expected value prepared in advance and the external scan path shift data output terminal DSOT and the external output terminals OUT1 and OUT1 are output.
The output value of No. 2 is compared and verified.

By the above comparative verification, the semiconductor integrated circuit 1
4 has detected a failure in the combinational circuits 11A to 11C.

FIG. 9 shows the flip-flop (F) shown in FIG.
F) It is a circuit diagram. As shown in FIG. 9, the FF 13 used in the scan path circuit is connected to the normal input DIN and the scan path shift data input SIN, and is controlled by the shift / test mode switching input SMC. A control clock is switched by a cascade-connected front-stage latch circuit 16 and rear-stage latch circuit 17 for latching outputs, that is, inputs RIN1 and RIN2, and a clock CLK, a scan clock SCK, and a scan path test / normal mode switching input AMC. , A test terminal switching circuit 18 and inverters IV21 and IV22. These latch circuits 16 and 17 are respectively
Transfer gates T1, T2 composed of MOSFETs
And inverters IV1 and IV2, transfer gates T3 and T4, and inverters IV3 and IV4. In particular, the latter-stage latch circuit 17 outputs data from the normal output terminal DOT in the normal mode, but outputs the scan path shift data output terminal S in the test mode.
Output from OT.

The transfer gates T1, T in the front-stage latch circuit 16 and the rear-stage latch circuit 17 of the FF 13
3 and the transfer gates T2 and T4 perform the opposite operation (ON / OFF) such that the operation control clocks CK and CKB (inversion) are supplied in reverse.

However, the above-described scan path circuit method has a problem that the number of external input terminals for testing increases to facilitate the test, and the overhead of the circuit also increases. As a technique for solving such a problem, for example, there is a technique described in Japanese Patent Application Laid-Open No. 5-72290.

FIG. 10 is a semiconductor integrated circuit diagram for explaining another conventional example. As shown in FIG. 10, the semiconductor integrated circuit 14 has the same basic configuration as the integrated circuit of FIG. 8, but has a smaller number of terminals.
This is configured using F19A to 19D. That is, as compared with the scan path circuit of FIG. 8, each FF does not have SIN, SMC, SCK, and AMC on the input side, but has a DTC instead, and the output side has only the normal output terminal DOT. It has a configuration.

When the test mode switching terminal DTC is at an inactive level, the semiconductor integrated circuit 14 operates in a normal mode, and each of the FFs 19A to 19D functions as a normal flip-flop. On the other hand, when the terminal DTC is at the active level, regardless of the logical value of the clock terminal CLK, F
F19A to 19D constitute a data through circuit. For this reason, since the output terminals of the FFs 19A to 19D have the same logic as the input terminals, the entire semiconductor integrated circuit 14 can be tested as a combination circuit.

FIG. 11 is an operation timing chart of each circuit in FIG. As shown in FIG. 11, first, in the normal mode, that is, when the DTC is at the 0 level (period t1),
When input values are supplied to the external input terminals IN1 to IN6,
The value of the combinational circuit 11A is determined to be 0 level in both Q1 and Q2. However, since the inputs of the FF 19A are all 0, the value of the output DOT is not determined, and the FF 19A is accordingly determined.
The logical values of 19B to 19D and the combinational circuits 11B and 11C are not determined. Therefore, the outputs OUT1 and OUT2 of the semiconductor integrated circuit 14 are also undefined.

Next, in the test mode, that is, when the DTC is at 1 level (period t2), the external input terminals IN1 to IN1
IN6 does not change as in the normal mode described above,
By setting DTC to 1 level, FF19A
-19D each pass data through the DIN input value to the DOT output value. For this reason, the FFs 19A to 19D and the combination circuits 11B and 11C sequentially determine the logic values with a delay of the delay time of each element, and the external output terminals OUT1 and OU1.
T2 is also determined. That is, the semiconductor integrated circuit 14
The whole is regarded as one combinational circuit and becomes testable.

FIG. 12 is a diagram of the flip-flop circuit shown in FIG. As shown in FIG. 12, the FF 19 receives a control signal D based on a pre-stage latch circuit 20 and a post-stage latch circuit 21, clocks CK and CKB having opposite phases by the clock CLK, and a test mode switching signal DTC.
It is composed of inverters IV15 to IV18 for generating T and DTB. These latch circuits 20 and 21 include transfer gates T11, T12, T17 and T18 and inverters IV11 and IV12 each composed of a CMOSFET, as in FIG.
13, T14 and inverters IV13, IV14, and each transfer gate has a clock CK, CK.
B or control signals DT and DTB.

In these latch circuits 20, 21, the transfer gates T17, T18 are turned on / off at opposite timings, and similarly, the transfer gates T1 and T18 are turned on and off.
5, T16 also perform on / off operations at the opposite timing.

Here, when the control signal DT is at the active level (1 level), the latch circuits 20 and 21 directly connect the input values RIN11 and RIN12 to the output regardless of the clock signal CK. That is, when viewed as FF19, the input value DI
It operates as a data through circuit that directly connects N to the output value DOT. If the control signal DT is at an inactive level (0 level), the FF 19 operates as a normal flip-flop circuit.

FIG. 13 is a diagram for explaining the truth values of the input / output signals of the flip-flop circuit shown in FIG. As shown in FIG. 13, when the DTC is at the 0 level, the FF 19 functions as a normal flip-flop circuit. When the DTC is at the 1 level, the FF 19 uses the input value DIN as the DOT output value without holding it as data.

FIG. 14 is a schematic block diagram for explaining the input / output relationship in FIG. As shown in FIG. 14, when the FF 19 in FIG. 12 is used for a semiconductor integrated circuit, a combinational circuit or another flip-flop (F
A loop may be formed via F). In a circuit for realizing a desired function, this loop is in a normal FF state, that is, when the DTC is at an inactive level, the FF
19, when the DIN input is propagated to the DOT output, T11 of the first-stage latch circuit 20 and T13 of the second-stage latch circuit 21 are exclusively turned on / off by the clock CLK.
It does not form loops and is therefore not a problem. However, when the DTC is at the active level, the FF 19 described above transmits the DIN input to the DOT output when the DTC input is transmitted to the DOT output.
Since there is a path of IN → T17 → IV11 → T15 → IV13 → DOT in principle, when the signal output from DOT returns to DIN through the above-mentioned loop, if the logic is inverted, the oscillation phenomenon occurs. And the FF 19 cannot be passed through.

That is, FIG.
In the case of a simple circuit as shown in FIG.
Reference numeral 1 denotes a model of the above-described combination circuit or another flip-flop, the first input of which is a DOT of the FF19.
When an output is input and the second input is inputting "1" from another combinational circuit or another FF circuit, an oscillation phenomenon occurs.

[0025]

The above-mentioned conventional method for testing a semiconductor integrated circuit is disclosed in the above-mentioned Japanese Patent Laid-Open Publication No. Hei 5-7229.
No. 0 publication etc.
In testing a semiconductor integrated circuit configured using F), if a loop circuit is used in which the FF circuit output is connected to the input terminal of its own FF circuit directly or through a combinational circuit, oscillation occurs. There is a drawback that a failure point cannot be detected and a normal test cannot be realized.

An object of the present invention is to reliably detect a faulty portion even when a loop circuit in which the output of a flip-flop circuit is supplied to its own input / output terminal directly or via a combinational circuit is formed. Another object of the present invention is to provide a method of testing a semiconductor integrated circuit that can easily and normally execute a test.

[0027]

A test method for a semiconductor integrated circuit according to the present invention comprises a plurality of signal input terminals and a plurality of signal output terminals, a plurality of normal input terminals and a plurality of normal output terminals, and a plurality of signal terminals operated by an internal clock. And a logic output such as the internal clock or internal data by an input signal supplied from outside through all or a part of the plurality of signal input terminals or an output from the normal output terminal of the FF circuit. A plurality of combinational circuits to be created, wherein the internal clock is input to the plurality of FF circuits via the plurality of combinational circuits.
A first clock terminal for inputting the internal clock; and a second clock terminal for inputting a test clock directly from an external test clock input terminal without passing through the plurality of FF circuits and the plurality of combinational circuits. Then, after giving a signal of a predetermined value to the plurality of signal input terminals and holding the same,
The plurality of FFs are supplied from the external test clock input terminal.
By supplying the test clock to the second clock terminal of the circuit, the plurality of FF circuits are sequentially operated from the input side, and the output values to the plurality of signal output terminals and an expected value prepared in advance are calculated. Configured to compare and test.

In the method for testing a semiconductor integrated circuit according to the present invention, the test clock supplied to the second clock terminal of the plurality of FF circuits includes the plurality of signal input terminals and the plurality of signal output terminals. The number of patterns corresponding to the number of the FF circuits in the path passing through the normal input terminal of the FF circuit and passing through the normal output terminal most frequently is input.

Further, the FF circuit according to the present invention comprises:
A pre-stage and a post-stage latch circuit and the pre-stage and the post-stage latch circuit are configured to be controlled only by the internal clock and the test clock.

[0030]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a semiconductor integrated circuit diagram for explaining a first embodiment of the present invention. FIG.
As shown in FIG. 1, a semiconductor integrated circuit (LSI circuit) 1 according to the present embodiment includes a combination circuit 2 having combination circuit sections 4A and 4B connected to external input terminals IN1 to IN6.
A and an FF 3A connected to outputs Q1, Q2 of the combinational circuit 2A and an external test clock terminal ITCK.
And a combinational circuit 2B having the normal output terminal DOT of the FF 3A as an input I1 and supplying outputs Q1 and Q2, and similar FFs 3B to 3D and a combinational circuit 2C. The outputs Q1 and Q2 of the combinational circuit 2C are External output terminal OUT
1 and OUT2. In addition,
The combination circuit 2C is different from the combination circuit 2B in that the output DOT of the FFs 3D and 3C is supplied to two inputs I1 and I2.

In the semiconductor integrated circuit 1, in the normal mode, the FFs 3A to 3D function as normal flip-flops that hold data fetched from the input terminal DIN according to a signal (different for each FF) supplied to the clock terminal CLK. Operate. On the other hand, in the test mode,
Each of the FFs 3A to 3D receives a waveform of (0 → 1 → 0 level) from the external test clock terminal ITCK and supplies the waveform to each test clock terminal TCK, whereby each F
F is forcibly operated.

A circuit operated by the same clock is called a one-phase synchronous circuit. On the other hand, as shown in FIG.
A circuit in which a logical operation is performed by a combinational circuit (other than an inverter and a buffer) having two outputs or more and is input to the clock of the FF is called an asynchronous circuit. Is not important.

In particular, in the test mode, a predetermined value prepared in advance (that is, a pattern for testing a semiconductor integrated circuit) is input from external input terminals IN1 to IN6 and fixed. In short, the input value is kept unchanged.

That is, the external test clock terminal IT
When a clock waveform is input from CK, each of the FFs 3A to 3D outputs the logical value supplied to the normal input terminal DIN to the normal output terminal DOT.
On the path from 1 to IN6 to the external output terminals OUT1 and OUT2, the external test clock terminal I for three stages of flip-flops on the path passing through the most flip-flops
By inputting the test clock terminal TCK from the TCK, the combinational circuit 2 is input from the external input terminals IN1 to IN6.
Data reaching the FFs 3A to 3C via A and 2B can be propagated to the external output terminals OUT1 and OUT2. For this reason, the entire semiconductor integrated circuit 1 can be regarded as having only the combinational circuits 2A to 2C, and the combinational circuit at the subsequent stage of the asynchronous circuit, that is, the output of another FF,
Alternatively, it is possible to operate the combination circuits 2B and 2C which input the outputs of the FFs 3A to 3C which are input to the FF clock CLK by performing a logical operation using a combination circuit having two or more inputs. Since the FF 3D is directly input from the external input terminal IN1, the FF 3D operates as a synchronization circuit, and this case is not included. Moreover, the third-stage combination circuit 2C
Are operated, the external output terminals OUT1, OUT2
Of the semiconductor integrated circuit 1 is detected by comparing the output value with a desired expected value.

In short, data is input from the external input terminals IN1 to IN6, and the external test clock terminals ITCK for the number n of flip-flops in the path which passes through the flip-flops most frequently to the external output terminals OUT1 and OUT2.
By inputting a clock waveform to the test clock terminal TCK, data reaching the FFs 3A to 3C from the external input terminals IN1 to IN6 via the combinational circuits 2A and 2B is propagated to the external output terminals OUT1 and OUT2. ,
The failure detection of the semiconductor integrated circuit is performed by comparing with the expected output value of the semiconductor integrated circuit obtained in advance.

FIG. 2 is an operation timing chart of each circuit in FIG. As shown in FIG. 2, in the normal mode (= t
In 1), for example, when "0" is input to the external input terminals IN1 and IN2 and "1" is input to the external input terminals IN3 to IN6, the outputs Q1 and Q2 of the combinational circuit 2A are output from the internal logic of the combinational circuit units 4A and 4B. It is assumed that both become “0”.
At this time, the input value of the circuit subsequent to the FF 3A is undefined.

Next, by supplying a clock waveform to the external test clock terminal ITCK in the data propagation mode (= t2), a clock is forcibly input from the outside to the FFs 3A to 3D, and the output Q1 of the combinational circuit 2A is output. The value can be propagated to the next stage, and the input terminal I1 of the combinational circuit 2B
And the normal input DIN of the FF 3D are both determined to be “0”. In the FFs 3B and 3C, the logical value of each normal input DIN is undefined, and the output value is not fixed. In addition, the combinational circuit 2B outputs “1” to the normal input DIN and “0” to the clock terminal CLK by the output DOT of the FF 3A.

Next, by supplying a clock waveform to the test clock terminal TCK in the data propagation mode (= t3), a clock is forcibly input from the outside to the FFs 3A to 3D, and the value "1" of the output DOT of the FF 3B is set to "1". , And the value of the normal input DIN of the FF3D can be propagated to the next stage, so that the input I1 of the combinational circuit 2C is determined to be "0". .

Further, by supplying a clock waveform to the test clock terminal TCK in the data propagation mode (= t4), a clock is forcibly input from the outside to the FFs 3A to 3D, and the value of the output DOT of the FF 3C is "1". , And the input I2 of the combinational circuit 2C is determined to be “1”. When the input of the combination circuit 2C is determined, the external output terminal OUT1 is determined to be “0” and OUT2 is determined to be “1”. A failure can be detected by comparing the determined values of OUT1 and OUT2 with expected output values.

FIG. 3 is a diagram of the flip-flop circuit shown in FIG. As shown in FIG. 3, the FF 3 includes a first latch circuit 5 as a preceding latch, a second latch circuit 6 as a subsequent latch, and internal clocks CKB and CK based on a clock input CLK and a test clock input TCK. , And an EX-NOR gate EX1 and an inverter IV5 as logic means for generating the first latch circuit 5.
Transfer gates T1 and T2 and ON / OFF controlled by clocks CKB and CK, and inverters IV1 and IV
2 and the second latch circuit 6 similarly supplies the clock CK
It includes transfer gates T3 and T4 whose on and off are controlled by B and CK, and inverters IV3 and IV4.

In the FF3, the normal input DIN inputs data to the first latch circuit 5 via the input terminal RIN1, and the first latch circuit 5 inputs data to the second latch circuit 6 via the input terminal RIN2. Then, the second latch circuit 6 outputs data from the normal output DOT.

FIGS. 4A to 4C are timing charts of the flip-flop of FIG. 3 in various modes. First, as shown in FIG. 4A, in the normal mode, for example, when the clock CLK is changed from (0 → 1 → 0) while the waveform of the test clock TCK is fixed at “0”, the internal The clock CK changes to (1 → 0 → 1), and the inverted clock CKB changes to (0 → 1 → 0).
The transfer gates in the first and second latches 5 and 6 are alternately turned on and off.

As shown in FIG. 4B, in the first data propagation mode, for example, the test clock TCK is set to (0) while the clock CLK is fixed at “0”.
→ 1 → 0), the internal clock CK becomes (1 →
0 → 1) and its inverted clock CKB is (0 → 1 →
0), and the transfer gates in the first and second latches 5 and 6 are alternately turned on and off.

Further, as shown in FIG. 4C, in the second data propagation mode, the clock CLK is set to "1".
When the test clock TCK is changed from (0 → 1 → 0), for example, the internal clock CK changes to (0 → 1 → 0) and the inverted clock CKB changes to (1 → 0).
→ 0 → 1), and the transfer gates in the first and second latches 5 and 6 are alternately turned on and off.

As described above, since the test clock can be input from the test clock terminal TCK regardless of the logic values "1" and "0" of the clock CLK of the FF3, the input is made to the normal input terminal DIN of the FF3. It is possible to generate a clock that propagates the set logical value to the normal output terminal DOT via the inside of the FF.

FIG. 5 is an operation timing chart of each circuit similar to that of FIG. 2 for explaining the second embodiment of the present invention. In the first embodiment described above, a method of performing logic verification on the assumption that the FFs 3A to 3D are indefinite has been described. However, as shown in FIG.
The expected values are compared after the values of the FFs 3A to 3D are determined in advance. That is, by using the data propagation method described in the first embodiment, a pattern to be initialized in advance is input from the external input terminals IN1 to IN6 and propagated to the external output terminals OUT1 and OUT2.
The values of F3A to 3D are determined. As shown in the normal mode in the period t10, each time TCK is input, the external output terminal OUT
A failure of the semiconductor integrated circuit is detected by comparing the output value of OUT1 and the output value of OUT2 with the expected output value of the semiconductor integrated circuit which has been obtained in advance.

First, in the normal mode (= t11),
For example, when "1" is input to IN1 to IN3 and "0" is input to IN4 to IN6, the outputs Q1, Q
2 is changed from “0” to “1” by the internal logic of the combinational circuit units 4A and 4B. At this time, FF3
The input value of the circuit after A is in the normal mode (= t10).
FF3A is “0”, FF3B is “1”,
3C is set to “1”, and FF3D is set to “0”.

Next, when a clock waveform is inputted to the test clock terminal TCK in the data propagation mode (= t12), a clock is forcibly inputted from the outside to the FF 3A, and the value of the output DOT is propagated to the next stage. Can be. Therefore, the input I1 of the combination circuit 2B is determined from “0” to “1”, and the normal input DIN of the FF 3D is determined from “0” to “1”. Outputs Q1, Q of this combinational circuit 2B
2 is determined by the output DOT of the FF 3A, and the external output terminal OUT1 changes from “1” to “0” and the external output terminal OU
T2 changes from “0” to “1”. As a result, a failure can be detected by comparing the values of the external output terminals OUT1 and OUT2 with the expected output values.

Next, by inputting a clock waveform to the test clock terminal TCK in the data propagation mode (= t13), a clock is forcibly input from the outside to the FF 3B, and the values of the outputs Q1 and Q2 of the combinational circuit 2B are output. To the next stage, and the normal input DIN of the FF3C is “1”.
To "0". Also, FF3 is forcibly applied from outside.
A clock is input to D, the value of the output DOT of the FF 3A can be propagated to the next stage, and the output Q1 of the combinational circuit 2C is output.
Is determined from “0” to “1”. As a result, a failure can be detected by comparing the values of the external output terminals OUT1 and OUT2 with the expected output values.

Next, by inputting a clock waveform to the test clock terminal TCK in the data propagation mode (= t14), a clock is forcibly input from the outside to the FF3C, and the value of the output DOT of the FF3B is transferred to the next stage. And the input I2 of the combinational circuit 2C changes from "1" to "0".
Confirm with. When the input of the combination circuit 2C is determined,
The external output terminal OUT1 is determined from “0” to “1”, and the external output terminal OUT2 is determined from “1” to “0”. As a result, a failure can be detected by comparing the values of the external output terminals OUT1 and OUT2 with the expected output values.

For example, the combination circuit 2C in the data propagation mode (= t14) outputs the output DOT of the FF 3D and the FF 3
Assuming that the output DOT of C is an input of the AND circuit and is output from the external output terminal OUT1, in the case of a failure in which the FF3D always outputs “0”, the expected value of the external output terminal OUT1 during the period (t13) The value does not match "1", and the failure can be detected. That is, each time the test clock terminal TCK is input, the external output terminals OUT1 and OU1 are output.
By comparing the change in the logical value of T2 with the expected output value, a failure can be detected. In short, in the present embodiment, it is possible to detect a failure that can be detected only by another test pattern in the first embodiment.

FIG. 6 is a semiconductor integrated circuit diagram for explaining a third embodiment of the present invention. As shown in FIG.
The LSI circuit 1 of the present embodiment is different from the circuit of FIG. 1 in that the output value of the FF 3A is supplied to the feedback input INF of the combinational circuit section 4A of the combinational circuit 2A. Others are the same.

In this embodiment, the external input terminal I
Data is input from N1 to IN6, and a clock waveform is supplied from the external test clock terminal ITCK to the test clock terminal TCK from the external test clock terminal ITCK for at least n FF stages in the path that passes through the flip-flops most in the path to the external output terminal. As a result, data reaching the FF from the external input terminals IN1 to IN6 via the combinational circuit can be transferred to the external output terminal O.
The signal is propagated to the UT1 and OUT2, and a failure of the LSI circuit 1 itself is detected by comparing with the expected output value of the LSI circuit 1 obtained in advance.

FIG. 7 is an operation timing chart of each circuit in FIG. As shown in FIG. 7, the normal mode (= t2
In 1), for example, when "0" is input to the external input terminals IN1 and IN2 and "1" is input to the external input terminals IN3 to IN6, the outputs Q1 and Q2 of the combinational circuits 2A and 2B are output from the combinational circuits 4A and 4B. It is assumed that each becomes “0” based on logic. At this time, the input value of a circuit subsequent to the FF 3A is undefined.

Next, in the data propagation mode (= t22), when a clock waveform is input to the test clock terminal TCK, a clock is forcibly input from the outside to the FF 3A, and the value of the input DIN of the FF 3A is changed to the FF 3A. Output D
Propagate to OT. That is, the value can be propagated to the input terminal I1 of the combination circuit 2B, so that the input I1 of the combination circuit 2B is determined to be “0” and the normal input DIN of the FF 3D is determined to be “0”. The combination circuit 2B is controlled by the output DOT of the FF 3A, and the output Q of the combination circuit 2B.
1 and Q2 become "1" and "0", respectively. Also, from the feedback loop that feeds back the output of the FF 3A, “0” is input to the feedback input terminal of the combination circuit unit 4A of the combination circuit 2A, and the output Q
1 becomes “1”.

Next, in the data propagation mode (= t23), when a clock waveform is input to the test clock terminal TCK, a clock is forcibly input from the outside to the FF 3B, and the value of the output Q1 of the combinational circuit 2B is changed. Since the signal can propagate to the next stage, the input DIN of the FF 3C is determined to be “1”.
Further, when a clock is forcibly input from the outside to the FF 3D, the value of the output DOT of the FF 3A can be propagated to the next stage, and the input I1 of the combination circuit 2C is determined to be “0”. Further, since the clock of the output DOT of the FF 3A is forcibly input from the outside, the value of the input DIN of the FF 3A in the data propagation mode (= t22) becomes “1”. "1" is input to the input feedback terminal INF of the combinational circuit 2A.
And its output Q1 becomes “0”. That is, the combination circuit 2A in the data propagation mode (= t22) described above.
Of the combinational circuit 2B can be propagated to the next stage.
1 is determined to be “1”, and the normal input DIN of the FF 3D is determined to be “1”. The outputs Q1 and Q2 of the combination circuit 2B are FF3A
Become "0" and "1" respectively by the output DOT.

Next, in the data propagation mode (= t24), when a clock waveform is inputted to the test clock terminal TCK, a clock is forcibly inputted from the outside to the FF3C, and the output DOT of the FF3B is propagated to the next stage. Therefore, the input I2 of the combinational circuit 2C is determined to be “1”. When the input of the combination circuit 2C is determined, the external output terminals OUT1 and OUT2 are determined to be "0" and "1", respectively. Further, as for the value of the output DOT of the FF 3A, a clock is forcibly input from the outside, and the value of the input DIN of the FF 3A in the data propagation mode (= t23) becomes “0”. "0" is applied to the input feedback terminal INF of the circuit 2A.
Is input, and the output Q1 of the combinational circuit 2A becomes “1”. That is, the output Q1 of the combination circuit 2A in the data propagation mode (= t23) can be propagated to the next stage, the input I1 of the combination circuit 2B is "0", and the normal input DIN of the FF3D.
Is determined to be “0”. The outputs Q1,
Q2 is "1" and "1" by the output DOT of FF3A, respectively.
It becomes "0". Thereafter, the external output terminals OUT1, OU
A failure can be detected by comparing the value of T2 with the expected output value.

Next, in the data propagation mode (= t25), when a clock waveform is inputted to the test clock terminal TCK, a clock is forcibly inputted from the outside to the FF3C, and the above-described data propagation mode (= t24) FF
Since the value of the output DOT of 3B can be propagated to the next stage, the input I2 of the combinational circuit 2C is determined to be “0”. When the input of the combination circuit 2C is determined, the external output terminal O
UT1 is determined to be “1” and OUT2 is determined to be “0”.

As described above, in the present embodiment, the value held by the FF is "0", the data is fed back, the data is inverted to the FF, and "1" is input. In such a case, that is, the data to be fed back after the data input from the external input terminal sequentially passes through the FFs, the input data corresponds to the number of FF stages n of the FFs in the path that passes through the FFs most from the external input terminal to the external output terminal. As described above, the clock waveform is input to the external input test clock terminal ITCK, and the external output terminals OUT1 and O
By comparing the change in the logical value of UT2 with the expected value,
The LSI circuit 1 can be verified.

[0060]

As described above, in the method of testing a semiconductor integrated circuit according to the present invention, the flip-flop (FF) takes in data in synchronization with a clock waveform and oscillates using the function of retaining the data. The test can be performed correctly even if there is a loop circuit in which the output of the FF circuit is connected to the input of its own FF circuit directly or through a combinational circuit. Has the effect of being able to accurately detect.

[Brief description of the drawings]

FIG. 1 is a semiconductor integrated circuit diagram for explaining a first embodiment of the present invention.

FIG. 2 is an operation timing chart of each circuit in FIG. 1;

FIG. 3 is a diagram of a flip-flop circuit shown in FIG. 1;

FIG. 4 is a timing chart in various modes of the flip-flop of FIG. 3;

FIG. 5 is an operation timing chart of each circuit similar to FIG. 2 for describing a second embodiment of the present invention.

FIG. 6 is a semiconductor integrated circuit diagram for explaining a third embodiment of the present invention.

FIG. 7 is an operation timing chart of each circuit in FIG. 6;

FIG. 8 is a semiconductor integrated circuit diagram for explaining an example of the related art.

FIG. 9 is a flip-flop circuit diagram in FIG.

FIG. 10 is a semiconductor integrated circuit diagram for explaining another conventional example.

11 is an operation timing chart of each circuit in FIG. 10;

FIG. 12 is a flip-flop circuit diagram shown in FIG.

13 illustrates a truth value of an input / output signal of the flip-flop circuit illustrated in FIG. 12;

FIG. 14 is a schematic block diagram for explaining an input / output relationship in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit (LSI circuit) 2A-2C combination circuit 3A-3D flip-flop (FF) 4A, 4B combination circuit part 5, 6 Latch circuit IN1-IN6 External input (terminal) OUT1, OUT2 External output (terminal) ITCK External Test clock input (terminal) T1 to T4 Transfer gate IV1 to IV5 Inverter EX1 EX-NOR gate INF Feedback input (terminal)

Claims (3)

[Claims] 1. A plurality of flip-flop circuits comprising a plurality of signal input terminals and a plurality of signal output terminals, a normal input terminal and a normal output terminal, and operating by an internal clock, and all or a plurality of the signal input terminals A plurality of combinational circuits for creating a logical output such as the internal clock or internal data based on an input signal supplied from outside through a part or an output from the normal output terminal of the flip-flop circuit; Wherein the plurality of flip-flop circuits are input to the plurality of flip-flop circuits via the plurality of combinational circuits, wherein each of the plurality of flip-flop circuits includes a first clock terminal for inputting the internal clock; An external test is performed without passing through the plurality of flip-flop circuits and the plurality of combinational circuits. A second clock terminal for directly inputting a test clock from a clock input terminal for
After applying and holding a signal of a predetermined value to the plurality of signal input terminals, supplying the test clock from the external test clock input terminal to the second clock terminals of the plurality of flip-flop circuits. A test method for a semiconductor integrated circuit, wherein the plurality of flip-flop circuits are sequentially operated from an input side, and a test is performed by comparing output values to the plurality of signal output terminals with an expected value prepared in advance. 2. The test clock supplied to the second clock terminal of the plurality of flip-flop circuits is the largest among the paths between the plurality of signal input terminals and the plurality of signal output terminals. 2. The test method for a semiconductor integrated circuit according to claim 1, wherein the number of patterns corresponding to the number of the flip-flop circuits on the path passing through the normal output terminal via the normal input terminal of the flip-flop circuit is input. 3. The test method for a semiconductor integrated circuit according to claim 1, wherein said flip-flop circuit controls a front-stage and a rear-stage latch circuit and said front-stage and rear-stage latch circuits only by said internal clock and said test clock.