JPH11191620A - Insulting gate field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce manufacturing man-hours. SOLUTION: An insulating gate field effect transistor is constituted of a first conductivity-type semiconductor substrate 1, a second conductivity-type well region 2 provided along one main surface of the semiconductor substrate 1, a first conductivity-type source region 3 and a drain region 4 separately provided in the well region 2, an insulating film 9 on the semiconductor substrate 1, a gate electrode 10 provide on a side opposite to the source region 3 and the drain region 4 as well as a source electrode and a drain electrode respectively provided, connecting to the source region 3 and the drain region 4. Here the gate electrode 10 is connected to a conductive film 12 which is provided to be electrostatically capacity-coupled with the semiconductor substrate 1 to pinch an outer insulating film 13 as the insulting film 9 at a position outside the well region 2 as viewed in an orthogonal direction with respect to the one main surface of the semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor.

[0002]

2. Description of the Related Art An insulated gate field effect transistor of this type is disclosed in Japanese Patent Application Laid-Open No. 61-259571. As shown in FIGS. 20 and 21, a semiconductor substrate A of a first conductivity type (N-type) and a second conductivity type (P-type) provided along one main surface of the semiconductor substrate A are provided.
⁺ Type, P ⁻ type well region B; a first conductive type (N ⁺ type) source region C and a drain region D provided in the well region B separately from each other; Diffusion region E of the first conductivity type (N ⁺ type) provided along the surface
, A gate electrode F connected to the diffusion region E, a source electrode G provided to be connected to the source region C, and a drain electrode H provided to be connected to the drain region D.

More specifically, since the gate electrode F is connected to the diffusion region E at the periphery of the semiconductor chip J constituting the present insulated gate field effect transistor,
Cross point J ₁ shown in, are cross-wired, it is taking gate signal.

In this device, although its gate electrode F is cross-wired on a semiconductor chip J, this semiconductor chip J has an oxygen-doped semi-insulating poly-oxide having a high oxygen concentration as shown in FIG. Since the silicon layer K, the oxygen-doped semi-insulating polysilicon layer L having a low oxygen concentration, the silicon nitride film layer M and the silicon oxide film layer N are provided, the well region B and the semiconductor are formed by the cross wiring portion in the gate electrode F 1. This eliminates the possibility that the breakdown voltage of the PN junction with the substrate A decreases.

[0005]

In the above-mentioned conventional insulated gate field effect transistor, its gate electrode
Since F is cross-wired on the semiconductor chip J, in order to eliminate the possibility that the withstand voltage of the PN junction between the well region B and the semiconductor substrate A is reduced, the oxygen-doped semi-insulating polymer having a high oxygen concentration is bothersome. A silicon layer K, an oxygen-doped semi-insulating polysilicon layer L having a low oxygen concentration, a silicon nitride film layer M, and a silicon oxide film layer N must be provided, and there is a problem that the production is troublesome.

The present invention has been made in view of the above points, and an object of the present invention is to provide an insulated gate field effect transistor which requires no trouble in manufacturing.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device having a first conductivity type and a first conductivity type semiconductor substrate. A second conductivity type well region, a first conductivity type source region and a drain region separately provided in the well region, an insulating film provided on the semiconductor substrate, and an insulating film provided on the semiconductor substrate. A gate electrode provided on a side opposite to the source region and the drain region, a source electrode provided to be connected to the source region, and a drain electrode provided to be connected to the drain region; The electrode is provided so as to be capacitively capacitively coupled to the semiconductor substrate with an external insulating film, which is the insulating film, at a position located outside the well region when viewed from a direction orthogonal to the one main surface. Connected to the conductive film It is the adult.

According to a second aspect of the present invention, in the first aspect, an adjacent region of a second conductivity type or a first conductivity type having an impurity concentration different from that of the semiconductor substrate is in contact with the well region. It is configured to be provided on a side opposite to the conductive film with the external insulating film interposed therebetween in a separated state.

According to a third aspect of the present invention, in the first aspect of the present invention, the gate electrode is a semiconductor film.

According to a fourth aspect of the present invention, in the third aspect, the conductive film is a semiconductor film of the same conductivity type as the gate electrode.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects of the present invention, the outer insulating film is provided at a position between the gate electrode and the semiconductor substrate. The thickness is substantially the same as that of the gate insulating film.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

Reference numeral 1 denotes a semiconductor substrate having a first conductivity type (N) having an impurity concentration of, for example, about 1 × 10 ¹⁴ (1 / cm ³ ).
^- has a type). The semiconductor substrate 1 is provided with a well region 2 of the second conductivity type (P type) having an impurity concentration of about 1 × 10 ¹⁸ (1 / cm ³ ) along one main surface thereof. The well region 2 has an impurity concentration of about 1 × 10 ^20.
(1 / cm ³ ) source region of the first conductivity type (N ⁺ type)
3 and the drain region 4 are provided separately from each other. This source region 3 is connected to a source electrode 5 and provided with a source contact 6. Further, the drain region 4 is connected to the drain electrode 7 and a drain contact 8 is provided. Reference numeral 9 denotes an insulating film made of a silicon nitride film having a thickness of 0.5 μm or less, preferably
It is not more than 0.05 μm and is provided on one main surface of the semiconductor substrate 1. Note that the insulating film 9 may be made of a silicon oxide film.

Reference numeral 10 denotes a gate electrode, which is formed of an aminium film and has a source region 3 and a drain region 4 with an insulating film 9 interposed therebetween.
And on the opposite side. Between the gate electrode 10 and the region from the source region 3 to the drain region 4, the insulating film 9 is locally formed to be thin to form the gate insulating film 11.

Reference numeral 12 denotes a conductive film, which is made of aluminum and sandwiches the external insulating film 13, which is the insulating film 9 located outside the well region 2 when viewed from a direction perpendicular to one main surface of the semiconductor substrate 1. In, the semiconductor substrate 1, more specifically, the semiconductor substrate
1 indicates that when a high potential is applied to the source electrode 5,
It is provided integrally with the gate electrode 10 and is connected to the gate electrode 8 so as to be capacitively capacitively coupled to the depletion layer 14 generated in the semiconductor substrate 1.

FIG. 3 shows an equivalent circuit diagram of the capacitor 15 in which the gate electrode 10, the external insulating film 13 and the semiconductor substrate 1 are capacitively coupled. Note that this capacitor 15
Let C _{1 be} the capacitance of the transistor, Cgs be the capacitance between the gate and source of the insulated gate field effect transistor, Vg be the gate potential, and HV be the potential of the semiconductor substrate 1.
Is obtained by the equation (1). When the potential of the semiconductor substrate 1 increases with an increase in HV and the value becomes equal to or higher than the threshold value Vth of the present insulated gate field effect transistor, conduction between the drain and source is established.

Vg = HV × C ₁ / (C ₁ + Cgs) (1) As shown in the equation (1), the external insulating film 13 may be thinned,
With by increasing the dielectric constant of the outer insulating film 13, a larger capacitance C ₁ of the capacitor 15, it is possible to increase the gate potential Vg.

In such an insulated gate field-effect transistor, the gate electrode 10 is an insulating film 9 located outside the well region 2 when viewed from a direction orthogonal to one main surface of the semiconductor substrate 1. With the insulating film 13 interposed therebetween, the semiconductor substrate 1, more specifically, is capacitively coupled to a depletion layer 14 generated in the semiconductor substrate 1 when a high potential is applied to the source electrode 5. Is electrically coupled to the semiconductor substrate 1 via the conductive film 12 by being connected to the conductive film 12 provided so as to be connected to the semiconductor substrate 1 as in the conventional example. Therefore, it is not necessary to provide a wiring structure that reduces the PN junction between the well region 2 and the semiconductor substrate 1 by being directly connected to the semiconductor substrate 1, thereby preventing the PN junction from being reduced. Bother to configure It is not necessary to provide
Production becomes easier.

In general, the gate electrode 10 and the semiconductor substrate
The gate insulating film 1 which is the insulating film 9 located between
1 is to increase the capacitance between the gate and the source,
Since the outer insulating film 13 is formed to be extremely thin, the outer insulating film 13 has substantially the same thickness as the gate insulating film 11,
It is possible to increase the capacitance C ₁ for capacitive coupling.

Next, a second embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those of the first embodiment are denoted by the same reference numerals, and only the differences from the first embodiment will be described. In the first embodiment, both the gate electrode 10 and the conductive film 12 are made of aluminum. In the present embodiment, the gate electrode 10 and the conductive film 12 are made of a semiconductor film made of a polysilicon of the second conductivity type (P type). I have.

More specifically, the gate electrode 10 and the conductive film 12
Each of them has a thickness of 0.5 μm and their sheet resistance is 20 (Ω / m ² ).

In such an insulated gate field effect transistor, since the semiconductor film is formed relatively easily by a semiconductor process, the manufacture is further facilitated.

The conductive film 12, which is a semiconductor film of the same conductivity type as the gate electrode 10, causes polarization together with the connected gate electrode 10, so that the conductive film 12 may be made of a metal such as aluminum. in comparison, it is possible to increase the capacitance C ₁ for capacitive coupling.

Since there is no work function difference between the gate electrode 10 and the well region 2, it is not necessary to consider the blood band voltage when designing the threshold value of the insulated gate field effect transistor.

Next, a third embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those of the second embodiment are denoted by the same reference numerals, and only the portions different from those of the first embodiment will be described. In the second embodiment, both the gate electrode 10 and the conductive film 12 are of the second conductivity type (P
In the present embodiment, the semiconductor film is made of a first conductivity type (N-type) polysilicon semiconductor film.

In such an insulated gate field effect transistor, the same effects as in the second embodiment can be obtained.

Next, a fourth embodiment of the present invention will be described below with reference to FIGS. Parts having substantially the same functions as those of the first embodiment are denoted by the same reference numerals,
Only different points from the first embodiment will be described. In this embodiment,
Basically the same as the first embodiment, but the well region 2
Adjacent region 16 of the second conductivity type (P type) formed similarly to
However, the difference lies in that the outer insulating film 12 is provided on the opposite side to the conductive film 12 with the outer insulating film 12 interposed therebetween while being spaced from the well region 2.

In this embodiment, the capacitance C ₂ for capacitive coupling is represented by the following equation (2). Incidentally, C ₁ is the capacitance as described above, Cd is the junction capacitance of the PN junction between the adjacent regions 16 the semiconductor substrate 1. The diode 17 formed of the PN junction is shown in the equivalent circuit diagram of FIG.

C ₂ = Cd × C ₁ / (Cd + C ₁ ) (2) In such an insulated gate field effect transistor, in addition to the effect of the first embodiment, the semiconductor substrate 1 is connected to the source electrode 5. When a high potential is applied, the semiconductor substrate
The depletion layer 14 generated at 1 is not only the well region 2 but also
Since the region also occurs around the adjacent region 16, the region of the semiconductor substrate 1 that is capacitively capacitively coupled to the conductive film 12 is expanded, and the area of the region that is capacitively capacitively coupled to the conductive film 12 is large. since it is possible to increase the capacitance C ₂ for capacitive coupling.

Next, a fifth embodiment of the present invention will be described with reference to FIGS.
This will be described below based on No. 10. Parts having substantially the same functions as in the fourth embodiment are denoted by the same reference numerals,
Only different points from the fourth embodiment will be described. In the fourth embodiment, the adjacent region 16 is provided separately from the well region 2, whereas in the present embodiment, the adjacent region 16 is provided in contact with the well region 2.

In such an insulated gate field effect transistor, the same effects as in the fourth embodiment can be obtained.

Next, a sixth embodiment of the present invention will be described below with reference to FIG. The portions having substantially the same functions as those of the fourth embodiment are denoted by the same reference numerals, and only the differences from the fourth embodiment will be described. In the fourth embodiment, the adjacent region 16 has the second conductivity type (P type), whereas in the present embodiment, the adjacent region 16 has the first conductivity type (N ^- has a type). For more information,
The impurity concentration of the adjacent region 16 is about 1 × 10 ¹³ (1 / c
m ³ ).

In such an insulated gate field effect transistor, the same effects as in the fourth embodiment can be obtained.

Next, a seventh embodiment of the present invention will be described below with reference to FIG. The portions having substantially the same functions as those of the sixth embodiment are denoted by the same reference numerals, and only the differences from the sixth embodiment will be described. In the sixth embodiment, the adjacent region 16 is provided apart from the well region 2, whereas in the present embodiment, the adjacent region 16 is provided in contact with the well region 2.

With such an insulated gate field effect transistor, the same effects as in the sixth embodiment can be obtained.

Next, an eighth embodiment of the present invention will be described below with reference to FIG. The portions having substantially the same functions as those of the fourth embodiment are denoted by the same reference numerals, and only the differences from the fourth embodiment will be described. In the fourth embodiment, both the gate electrode 10 and the conductive film 12 are made of aluminum, whereas in the present embodiment, as in the second embodiment,
It is made of a semiconductor film made of polysilicon of the second conductivity type (P type).

In such an insulated gate field effect transistor, in addition to the effects of the fourth embodiment, as in the second embodiment, the fabrication becomes easier and the capacitance C ₂ for capacitive coupling is increased. Can be increased, and it is not necessary to consider the blood band voltage when designing the threshold value of the insulated gate field effect transistor.

Next, a ninth embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those of the eighth embodiment are denoted by the same reference numerals, and only portions different from the eighth embodiment will be described. In the eighth embodiment, both the gate electrode 10 and the conductive film 12 are of the second conductivity type (P
In the present embodiment, the semiconductor film is made of a first conductivity type (N-type) polysilicon semiconductor film.

With such an insulated gate field effect transistor, the same effects as in the eighth embodiment can be obtained.

Next, a tenth embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those of the eighth embodiment are denoted by the same reference numerals, and only portions different from the eighth embodiment will be described. In the eighth embodiment, the adjacent region 16 is provided apart from the well region 2, whereas in the present embodiment, the adjacent region 16 is provided in contact with the well region 2.

In such an insulated gate field effect transistor, the same effects as in the eighth embodiment can be obtained.

Next, an eleventh embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those in the tenth embodiment are denoted by the same reference numerals, and only differences from the tenth embodiment will be described. In the tenth embodiment, both the gate electrode 10 and the conductive film 12 are of the second conductivity type (P
In this embodiment, as in the sixth embodiment, the semiconductor film is made of a first conductivity type (N-type) polysilicon semiconductor film, while the semiconductor film is made of a polysilicon semiconductor film. .

With such an insulated gate field effect transistor, the same effects as in the ninth embodiment can be obtained.

Next, a twelfth embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those of the eighth embodiment are denoted by the same reference numerals, and only portions different from the eighth embodiment will be described. In the eighth embodiment, the adjacent region 16 has the second conductivity type (P type), whereas in the present embodiment, as in the sixth embodiment, the adjacent region 16 is different from the semiconductor substrate 1 in the impurity concentration. It has a small first conductivity type (N ⁻ type).

With such an insulated gate field effect transistor, the same effects as in the eighth embodiment can be obtained.

Next, a thirteenth embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those in the twelfth embodiment are denoted by the same reference numerals, and only differences from the twelfth embodiment will be described. In the twelfth embodiment, both the gate electrode 10 and the conductive film 12 are of the second conductivity type (P
(Type) made of polysilicon semiconductor film, adjacent region 16
Is provided separately from the well region 2, while
In the present embodiment, the gate electrode 10 and the conductive film 12 are both made of a semiconductor film made of polysilicon of the first conductivity type (N type), and the gate electrode 10 and the conductive film 12 are in contact with the well region 2. It is configured to be provided.

Such an insulated gate field effect transistor has the same advantages as the twelfth embodiment.

In the second and third embodiments and the eighth to thirteenth embodiments, the conductive film 12 is a semiconductor film of the same conductivity type as the gate electrode 10. When C ₁ and the capacitance C ₂ can be secured, for example, as shown in FIG.
As shown in FIG. 3, only the gate electrode 10 has the second conductivity type (P
In the (type) semiconductor film, the conductive film 12 may be a metal film such as aluminum.

In the first to thirteenth embodiments, the outer insulating film 13 has substantially the same thickness as the gate insulating film 11. For example, the outer insulating film 13 has a sufficient capacitance C ₁ , If C ₂ can be ensured, it may be formed thicker than the gate insulating film 11.

In the twelfth embodiment, the adjacent area 16
Although provided separately from the well region 2, the well region
Even when provided in contact with 2, the same effect can be obtained.

In the thirteenth embodiment, both the gate electrode 10 and the conductive film 12 are made of a semiconductor film made of polysilicon of the first conductivity type (N-type). )
A similar effect can be obtained even with a semiconductor film made of polysilicon.

In the first to thirteenth embodiments, the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type is P-type and the second conductivity type is P-type. Even if the type is N-type, the same effect can be obtained.

[0053]

According to the first aspect of the present invention, the gate electrode comprises:
A semiconductor substrate, more specifically, a semiconductor substrate, specifically, a semiconductor substrate having a high potential with respect to a source electrode, with an external insulating film that is an insulating film located outside the well region when viewed from an orthogonal direction orthogonal to one main surface of the semiconductor substrate. Is connected to a conductive film that is provided so as to be capacitively capacitively coupled to a depletion layer generated in the semiconductor substrate when is applied, so that the semiconductor substrate is capacitively capacitively coupled through the conductive film. Since it is not directly connected to the semiconductor substrate as in the conventional example, the wiring is connected directly to the semiconductor substrate to reduce the PN junction between the well region and the semiconductor substrate. Since it is not necessary to provide a configuration, it is not necessary to provide a configuration for preventing the PN junction from being lowered, and the manufacturing is facilitated.

According to a second aspect of the present invention, in addition to the effect of the first aspect, when a high potential is applied to the semiconductor substrate with respect to the source electrode, a depletion layer generated in the semiconductor substrate is Since it occurs not only in the well region but also in the periphery of the adjacent region, the region of the semiconductor substrate that is capacitively capacitively coupled to the conductive film is expanded, and the area of the region that is capacitively capacitively coupled to the conductive film is increased. , The capacitance for capacitive coupling can be increased.

According to the third aspect of the present invention, since the semiconductor film is relatively easily formed by the semiconductor process, the effect of the first aspect of the present invention, which facilitates the production, can be further exhibited.

According to a fourth aspect of the present invention, in addition to the effect of the third aspect, the conductive film which is a semiconductor film of the same conductivity type as the gate electrode causes polarization together with the connected gate electrode. As compared with the case where the conductive film is formed of a metal such as aluminum, for example, the capacitance for capacitive coupling can be increased.

According to a fifth aspect of the present invention, in addition to the effect of any one of the first to fourth aspects of the present invention, in general, a gate which is an insulating film at a position located between a gate electrode and a semiconductor substrate. Since the insulating film is formed extremely thin in order to increase the capacitance between the gate electrode and the source electrode, the outer insulating film has substantially the same thickness as the gate insulating film. Thus, the capacitance for capacitive coupling can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a plan view of the same.

FIG. 3 is an equivalent circuit diagram of the above.

FIG. 4 is a sectional view of a second embodiment of the present invention.

FIG. 5 is a sectional view of a third embodiment of the present invention.

FIG. 6 is a sectional view of a fourth embodiment of the present invention.

FIG. 7 is a plan view of the same.

FIG. 8 is an equivalent circuit diagram of the above.

FIG. 9 is a sectional view of a fifth embodiment of the present invention.

FIG. 10 is a plan view of the same.

FIG. 11 is a sectional view of a sixth embodiment of the present invention.

FIG. 12 is a sectional view of a seventh embodiment of the present invention.

FIG. 13 is a sectional view of an eighth embodiment of the present invention.

FIG. 14 is a sectional view of a ninth embodiment of the present invention.

FIG. 15 is a sectional view of a tenth embodiment of the present invention.

FIG. 16 is a sectional view of an eleventh embodiment of the present invention.

FIG. 17 is a sectional view of a twelfth embodiment of the present invention.

FIG. 18 is a sectional view of a thirteenth embodiment of the present invention.

FIG. 19 is a cross-sectional view of a structure in which a gate electrode made of a semiconductor film and a conductive film made of aluminum are provided.

FIG. 20 is a sectional view of a conventional example.

FIG. 21 is a plan view of the same.

[Explanation of symbols]

 1 semiconductor substrate 2 well region 3 source region 4 drain region 5 source electrode 7 drain electrode 9 insulating film 10 gate electrode 11 gate insulating film 12 conductive film 13 external insulating film 16 adjacent region

Claims (5)

[Claims] A first conductive type semiconductor substrate; a second conductive type well region provided along one main surface of the first conductive type semiconductor substrate; A first conductivity type source region and a drain region provided;
An insulating film provided on the semiconductor substrate, a gate electrode provided on a side opposite to the source and drain regions with the insulating film interposed therebetween, a source electrode provided connected to the source region, and a source electrode connected to the drain region; A drain electrode provided, and wherein the gate electrode sandwiches an external insulating film that is the insulating film at a position located outside the well region when viewed from an orthogonal direction orthogonal to the one main surface. An insulated gate field effect transistor connected to a conductive film provided so as to be capacitively capacitively coupled to a semiconductor substrate. 2. The conductive film sandwiching the external insulating film in a state where an adjacent region of a second conductive type or a first conductive type having a different impurity concentration from the semiconductor substrate is in contact with or separated from the well region. 2. The insulated gate field effect transistor according to claim 1, wherein said transistor is provided on a side opposite to said side. 3. The insulated gate field effect transistor according to claim 1, wherein said gate electrode is a semiconductor film. 4. The insulated gate field effect transistor according to claim 3, wherein said conductive film is a semiconductor film of the same conductivity type as said gate electrode. 5. The semiconductor device according to claim 1, wherein the outer insulating film has substantially the same thickness as a gate insulating film which is the insulating film at a position located between the gate electrode and the semiconductor substrate. An insulated gate field effect transistor according to claim 4.