JPH11191593A - Device for generating mask pattern data, method for generating mask pattern, and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce labor on the layout design of a circuit, and to prevent man-made mistake by specifying two integrated circuit formation regions on a substrate, by forming a conductive-type MOS transistor, and by generating the mask pattern of conductive-type bottom well formation over the entire portion of the integrated circuit formation region. SOLUTION: On a P-type semiconductor substrate, two logic circuit formation regions 101 and 102 and a memory circuit formation region 301 are arranged. In the circuit formation region 101, each of P-type and N-type well regions is continuously arranged, and a plurality of sets of P-type and N-type MOS transistors are combined. In the circuit formation region 102, the N-type and P-type transistors are constituted in the P-type and N-type well being arranged based on a logic core. Over the enter portion of the logic circuit formation regions 101 and 201, a master pattern is generated, where the master pattern forms each bottom well and well wall of N-type potential isolation regions 108 and 208 being positioned under the P-type and N-type wells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having, for example, a logic circuit and a memory circuit, and further relates to a method and apparatus for generating mask pattern data in designing a circuit pattern of the semiconductor integrated circuit device. Things.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a semiconductor integrated circuit device capable of achieving high performance, small size, and low power consumption for advanced data processing accompanying digital signal processing. As such a semiconductor integrated circuit device, a DRAM-integrated semiconductor integrated circuit device in which a random logic circuit and a dynamic random memory circuit (hereinafter, referred to as a DRAM circuit) are formed on one semiconductor substrate has been proposed.

[0003]

The following problems arise when such a semiconductor integrated circuit device with a built-in DRAM is designed using a conventional automatic wiring technique, that is, a mask pattern data generation method. That is, DRAM
In the circuit, for example, an N-type M
The substrate potential of the OS transistor is set to a negative potential (for example, about-
1V) (hereinafter referred to as an N-type MOS to which a negative potential is applied as a substrate potential including this N-type MOS transistor).
S transistors are collectively referred to as memory-side N-type MOS transistors). On the other hand, in the random logic circuit, the substrate potential of the N-type MOS transistor is set to the ground potential so as not to hinder the speeding up (hereinafter, referred to as a logic-side N-type MOS transistor).

In order to stabilize a memory-side N-type MOS transistor, a substrate of a memory-side N-type MOS transistor is provided on a P-type semiconductor substrate on which a DRAM circuit and a random logic circuit are formed. When the same negative potential as the potential is applied, it is necessary to electrically separate the substrate potential applied to the logic-side N-type MOS transistor from the P-type substrate.

In such a case, a logic-side N-type MOS transistor is formed in a P-type well region (hereinafter, referred to as a P-type well), and the P-type well and the P-type substrate are separated from each other by an N-type well potential separation region. (Hereinafter, referred to as an N-type isolation region).

However, when designing such a semiconductor integrated circuit device with a built-in DRAM using a conventional automatic placement and routing technique, the information of the N-type isolation region is included in the logic information describing the operation of the random logic circuit. Because there is no
After designing a random logic circuit and a DRAM circuit using an automatic placement and routing technique, manually, that is,
There has been a problem that an N-type isolation region has to be manually arranged on a mask pattern data generation device (also called a layout editor) which is a circuit design computer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can reduce the labor required for circuit layout design by automatically generating a mask pattern for a well potential separation region. It is another object of the present invention to provide a mask pattern data generation device which can eliminate human error. It is another object of the present invention to provide a mask pattern data generation device which automatically generates wirings, contact holes, and the like necessary for supplying power to a well potential separation region to reduce labor and eliminate human error. And Further, the present invention provides a semiconductor integrated circuit device in which noise is prevented from entering between the first integrated circuit and the second integrated circuit by stably supplying a voltage to the well potential separation region. Aim.

[0008]

In a mask pattern data generating apparatus according to the present invention, a MOS transistor of a second conductivity type is formed in a first well region of a first conductivity type to which a first substrate potential is applied. A second conductive type MOS formed in a first integrated circuit forming region and a first conductive type second well region to which a second substrate potential different from the first substrate potential is applied. The second where the transistor is formed
Area designating means for designating a first integrated circuit forming area and a second integrated circuit forming area with respect to a surface of a first conductivity type semiconductor substrate having a first integrated circuit forming area; Bottom well pattern generation means for generating a mask pattern for forming a second conductivity type bottom well located below the first well area over the entire circuit formation area; The first integrated circuit formation region formed in the first integrated circuit formation region based on the information of the first integrated circuit formation region and the information of the bottom well in the mask pattern generated by the bottom well pattern generation means.
And a well wall pattern generating means for generating a mask pattern for forming a second conductivity type well wall reaching the bottom well from the surface of the semiconductor substrate.

A mask pattern data generating apparatus according to the present invention has a first integrated circuit forming area where a first integrated circuit is formed and a second integrated circuit forming area where a second integrated circuit is formed. , The first integrated circuit is constituted by a plurality of cells designed in units of logic levels, and the cells are formed in a first well region of a first conductivity type to which a first substrate potential is applied. And a second integrated circuit is formed in a second well region of a first conductivity type to which a second substrate potential having a potential different from the first substrate potential is applied. Region designating means for designating a first integrated circuit formation region and a second integrated circuit formation region on a surface of a first conductivity type semiconductor substrate at least partially constituted by a second conductivity type MOS transistor A cell arrangement designating means for designating the arrangement of a plurality of cells based on logical information describing the operation of the first integrated circuit in the first integrated circuit formation area; Wiring position specifying means for specifying a wiring position based on logic information describing the operation of the first integrated circuit and cell information for a plurality of cells; Bottom well pattern generation means for generating a mask pattern for forming a second conductivity type bottom well located below one well region;
The first integrated circuit formed in the first integrated circuit formation region is calculated by performing an operation using the information of the integrated circuit formation region of the above and the information of the bottom well in the mask pattern generated by the bottom well pattern generation means. And a well wall pattern generating means for generating a mask pattern for forming a second conductivity type well wall reaching the bottom well from the surface of the semiconductor substrate.

[0010] In the method of generating mask pattern data according to the present invention, the first conductive type first to which the first substrate potential is applied.
A first integrated circuit formation region in which a MOS transistor of the second conductivity type is formed in the well region of the first conductivity type; and a first conductivity type to which a second substrate potential different from the first substrate potential is applied. The first integrated circuit forming region and the second integrated circuit forming region are formed on the surface of the first conductive type semiconductor substrate having the second integrated circuit forming region where the second conductive type MOS transistor formed in the second well region is formed. An area specifying step of specifying an integrated circuit forming area of the second type and forming a bottom well of the second conductivity type located below the first well area over the entire area of the first integrated circuit forming area of the semiconductor substrate. A bottom well pattern generating step for generating a mask pattern, information on a first integrated circuit formation region specified in the region specifying step, and a mask generated in the bottom well pattern generating step Based on the information of the bottom wells in turn, the first formed in the first integrated circuit formation region
And a well wall pattern generating step of generating a mask pattern for forming a second conductivity type well wall reaching the bottom well from the surface of the semiconductor substrate.

[0011] A mask pattern data generating method according to the present invention has a first integrated circuit forming region in which a first integrated circuit is formed and a second integrated circuit forming region in which a second integrated circuit is formed. , The first integrated circuit is constituted by a plurality of cells at a logic gate level, and the cells are formed in a first well region of a first conductivity type to which a first substrate potential is applied. The second integrated circuit is formed at least in part in the second well region of the first conductivity type to which a second substrate potential having a potential different from the first substrate potential is applied. Conductive MO
An area designating step of designating a first integrated circuit formation area and a second integrated circuit formation area on a surface of a first conductivity type semiconductor substrate at least partially constituted by S transistors; A cell arrangement designating step of designating the arrangement of a plurality of cells based on logical information describing the operation of the first integrated circuit in the circuit formation region;
A wiring position specifying step for specifying a wiring position based on logic information describing the operation of the first integrated circuit and cell information on a plurality of cells, for the integrated circuit formation region of
The first integrated circuit is formed over the entire first integrated circuit forming region of the semiconductor substrate.
Forming a mask pattern for forming a bottom well of the second conductivity type located below the well region of the second well type, information of the first integrated circuit formation region designated in the region designation step, and The first integrated circuit formed in the first integrated circuit formation region is surrounded by performing an operation using the information of the bottom well in the mask pattern generated in the bottom well pattern generation step, and the first integrated circuit is formed from the surface of the semiconductor substrate. Generating a mask pattern for forming a second conductivity type well wall reaching the bottom well.

A semiconductor integrated circuit device according to the present invention has, on its surface, a first integrated circuit formation region in which a first integrated circuit is formed and a second integrated circuit formation region in which a second integrated circuit is formed. A first conductivity type semiconductor substrate; a first conductivity type first well region formed in a first integrated circuit formation region of the semiconductor substrate; and a first integrated circuit formed in the first well region. MO of the second conductivity type forming part of the circuit
An S transistor, a second well region of a first conductivity type formed in a second integrated circuit formation region of the semiconductor substrate, and a part of the second integrated circuit formed in the second well region MOS transistor of the second conductivity type, a bottom well of the second conductivity type located under the first well region over the entire first integrated circuit formation region of the semiconductor substrate, and the first integrated circuit formation region A well potential isolation region surrounding the first integrated circuit formed on the semiconductor substrate and having a second conductivity type well wall reaching the bottom well from the surface of the semiconductor substrate; A first wiring layer electrically connected at a surface of the well region and transmitting a first potential to the first well region; and a first wiring layer provided on a surface of the semiconductor substrate and provided at a surface of the second well region. Electrically connected to a first potential and A second wiring layer for transmitting a different second potential to the second well region; and a second wiring layer provided on a surface of the semiconductor substrate and electrically connected to a surface of the well potential separation region. And a third wiring layer for transmitting a third potential for applying a reverse bias to the PN junction to the substrate to the well potential separation region.

A semiconductor integrated circuit device according to the present invention has a P-type semiconductor substrate having a logic circuit formation region in which a logic circuit is formed, a memory circuit formation region in which a memory circuit is formed on a surface, and a P-type semiconductor substrate. A P-type first well region formed in the logic circuit formation region, an N-type MOS transistor formed in the first well region and forming a part of the logic circuit, and a logic circuit formation region of a semiconductor substrate An N-type third well region, a P-type MOS transistor formed in the third well region and forming a part of a logic circuit, and a memory circuit formation region of a semiconductor substrate. A P-type second well region, an N-type MOS transistor formed in the second well region and forming a part of a memory circuit, and a memory of a semiconductor substrate. Fourth N type formed in the road formation region
A P-type MOS transistor formed in the fourth well region and forming a part of the memory circuit, and a P-type MOS transistor formed in the first and third well regions over the entire logic circuit formation region of the semiconductor substrate. A semiconductor region surrounding a logic circuit formed in a logic circuit formation region, an N-type bottom well located below, and an N-type well wall reaching the bottom well from the surface of the semiconductor substrate; A first wiring layer provided on a surface of the substrate, electrically connected at a surface of the first well region, and transmitting a ground potential to the first well region; and a first wiring layer provided on a surface of the semiconductor substrate; A second wiring layer electrically connected to a surface of the second well region and transmitting a negative potential to the second well region; and a second wiring layer provided on a surface of the semiconductor substrate and provided on a surface of the third well region. At A third wiring layer that is electrically connected and transmits a positive potential to the third well region, is provided on the surface of the semiconductor substrate, is electrically connected to the surface of the fourth well region, and A fourth transmitting the potential to the fourth well region
And a fifth wiring layer provided on the surface of the semiconductor substrate, electrically connected to the surface of the well potential separation region, and transmitting a positive potential to the well potential separation region. is there.

A semiconductor integrated circuit device according to the present invention is managed as a first logic circuit formation area in which a first logic circuit arranged and designed based on cells designed in units of logic levels is formed, as a design resource. Logic circuit formation region arranged and designed based on a core, a P-type semiconductor substrate having a memory circuit formation region in which a memory circuit is formed on the surface, and a first logic circuit formation region of the semiconductor substrate A first P-type well region formed at
An N-type MOS transistor formed in the first well region and constituting a part of the first logic circuit, and an N-type third well region formed in the first logic circuit formation region of the semiconductor substrate And a P-type MOS formed in the third well region and constituting a part of the first logic circuit.
A transistor, a P-type second well region formed in a memory circuit formation region of the semiconductor substrate, and an N-type M region formed in the second well region and constituting a part of the memory circuit.
An OS transistor, an N-type fourth well region formed in a memory circuit formation region of the semiconductor substrate, a P-type MOS transistor formed in the fourth well region and forming a part of the memory circuit, A P-type fifth well region formed in the second logic circuit formation region of the semiconductor substrate;
An N-type MOS transistor formed in the fifth well region and constituting a part of the second logic circuit, and an N-type sixth well region formed in the second logic circuit formation region of the semiconductor substrate And a P-type MOS formed in the sixth well region and constituting a part of the second logic circuit.
A transistor, an N-type first bottom well located under the first and third well regions over the entire first logic circuit formation region of the semiconductor substrate, and a transistor formed in the first logic circuit formation region A first well potential isolation region surrounding the first logic circuit and having an N-type first well wall reaching the first bottom well from the surface of the semiconductor substrate; and a second logic of the semiconductor substrate. Surrounding an N-type second bottom well located below the fifth and sixth well regions over the entire circuit formation region, and a second logic circuit formed in the second logic circuit formation region;
A second well potential isolation region having an N-type second well wall reaching the second bottom well from the surface of the semiconductor substrate; and a surface of the first well region provided on the surface of the semiconductor substrate. A first wiring layer electrically connected to the first well region for transmitting a ground potential to the first well region, provided on a surface of the semiconductor substrate, and electrically connected to a surface of the second well region; A second transmitting a negative potential to the second well region;
Is provided on the surface of the semiconductor substrate, and is electrically connected to the surface of the third well region.
A third wiring layer that is provided on the surface of the semiconductor substrate and is electrically connected to the surface of the fourth well region to transmit a positive potential to the fourth well region; A fourth wiring layer provided on the surface of the semiconductor substrate, electrically connected to the surface of the fifth well region, and transmitting a ground potential to the fifth well region; A sixth wiring layer electrically connected at the surface of the sixth well region and transmitting a positive potential to the sixth well region; and a sixth wiring layer provided on the surface of the semiconductor substrate, First
A seventh wiring layer electrically connected to the surface of the well potential separation region for transmitting a positive potential to the first well potential separation region; and a second well potential provided on the surface of the semiconductor substrate. And an eighth wiring layer electrically connected to the surface of the isolation region and transmitting a positive potential to the second well potential isolation region.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. First, a semiconductor integrated circuit device with a built-in DRAM according to the first embodiment will be described with reference to FIGS. 3 and 4, reference numeral 101 denotes an AND gate, an OR gate,
In a first logic circuit formation region in which a first logic circuit is formed, which is configured by combining a plurality of cells such as an exclusive gate and a flip-flop, the first logic circuit includes the plurality of cells. The layout is designed by an automatic wiring arrangement device or the like in combination.

In the first logic circuit formation region 101 of a P-type semiconductor substrate (hereinafter, referred to as a P-type substrate) 100, an N-type well region (hereinafter, referred to as a P-type substrate) is formed in the vertical direction of FIG. , N-type well), P-type well region (hereinafter referred to as P-type well), P-type well, N-type well, N-type well, P-type well,. . . Formed in each of the well regions which are continuously arranged without gaps as shown in FIG.
A plurality of cells each including a type MOS transistor (hereinafter, referred to as a P-type transistor) and an N-type MOS transistor (hereinafter, referred to as an N-type transistor) are combined.

An N-type transistor and a P-type transistor constituting the first logic circuit are formed as shown in FIG. In FIG. 5, reference numeral 102 denotes a P-type well (first well region) formed in the first logic circuit formation region 101. This P-type well 102 is electrically connected on the surface thereof, and has a first ground line (first wiring layer) 10 provided on the surface of a P-type substrate (semiconductor substrate) 100.
At 3, a ground potential (VSS, for example, 0 V) is applied.
Reference numeral 104 denotes an N-type well (second well region) formed in the first logic circuit formation region 101, which is regularly formed in the first logic circuit formation region 101 with the P-type well 102.
That is, NPPNPNPNP. . . It is juxtaposed like. The N-type well 104 is electrically connected at the surface thereof, and is connected to a power supply line (second wiring layer) 105 provided on the surface of the P-type substrate 100 at a power supply potential (VDD, in the first embodiment). Is, for example, 5 V).
The P-type substrate 100 has a negative potential (for example, about -1 V).
Is applied.

Reference numeral 106 denotes an N formed in the P-type well 102.
A pair of N-type source / drain regions 106a and 106b formed on the surface of a P-type well 102 via a channel region, and a gate electrode 106c formed on the channel region via a gate oxide film 106d. Is formed by

Reference numeral 107 denotes a P formed in the N-type well 104.
A pair of P-type source / drain regions 107a and 107b formed on the surface of an N-type well 104 via a channel region, and a gate electrode 107c formed on the channel region via a gate oxide film 107d. Is formed by

In FIG. 5, the N-type transistor 1
06 and the P-type transistor 107, the pair of source / drain regions 10 are arranged in the juxtaposition direction (the horizontal direction in the drawing) of the P-type well 102 and the N-type well 104.
7a and 107b are shown, but actually, the P-type well 1
02 and a pair of source / drain regions 1 in a direction perpendicular to the juxtaposition direction of the N-type well 104 (a direction perpendicular to the plane of the drawing).
07a and 107b are arranged. In addition, the gate electrode 106c of the N-type transistor 106 and the gate electrode 107c of the P-type transistor 107 are actually arranged in the longitudinal direction in the left-right direction in FIG.
06 and the gate electrode of the P-type transistor 107 are arranged on a straight line.

Reference numeral 108 denotes an N-type bottom well 108a located under the P-type well 102 and the N-type well 104 over the entire first logic circuit formation region 101 of the P-type substrate 100; A P-type substrate 100 surrounding the first logic circuit formed in the region 101;
And an N-type well potential separation region (hereinafter, referred to as an N-type separation region) having an N-type well wall 108b reaching the surface of the bottom well 108a from the surface of the bottom well 108a. The N-type isolation region 108 is electrically connected at a plurality of locations on the surface of the well wall 108 b, and is a power supply line (third wiring layer) 109 serving as a connection wiring portion provided on the surface of the P-type substrate 100.
At the power supply potential (VDD, in the first embodiment,
For example, 5V) is applied.

As described above, the power supply potential is applied to the N-type isolation region 108 at a plurality of locations on the surface of the well wall 108b and the power supply potential is applied through the N-type well 104. There is almost no potential difference over the entire region 108, and the potential is substantially set to the power supply potential.

Further, since a power supply potential is applied to the N-type isolation region 108 and a negative potential is applied to the P-type substrate 100, a reverse PN junction is formed between the N-type isolation region 108 and the P-type substrate 100. Bias is applied. Therefore, the N-type isolation region 1
Reference numeral 08 functions as an electrical isolation region between the P-type substrate 100 and electrically isolates the P-type substrate 100 from the P-type well 102.

Referring back to FIGS. 3 and 4, reference numeral 201 denotes a second logic circuit formation area in which a second logic circuit arranged and designed based on a logic core already managed as a design resource is formed.

In the second logic circuit formation region 201 of the P-type substrate 100, the second logic circuit includes an N-type transistor and a P-type transistor formed in each of a P-type well and an N-type well arranged based on a logic core. It is constituted by a type transistor.

The N-type transistor and the P-type transistor constituting the second logic circuit are formed as shown in FIG. In FIG. 6, reference numeral 202 denotes a P-type well (first well region) formed in the second logic circuit formation region 201. The P-type well 202 is electrically connected on the surface thereof, and is connected to a ground potential (VS) by a ground line (first wiring layer) 203 provided on the surface of the P-type substrate 100.
S, for example, 0 V). Reference numeral 204 denotes an N-type well (second well region) formed in the second logic circuit formation region 201. The N-type well 204 is electrically connected on the surface thereof, and is connected to a power supply line (second wiring layer) 205 provided on the surface of the P-type substrate 100 by a power supply potential (VDD, in the first and second embodiments). For example, 5 V is applied.

Reference numeral 206 denotes an N formed in the P-type well 202.
A pair of N-type source / drain regions 206a and 206b formed on the surface of a P-type well 202 via a channel region, and a gate electrode 206c formed on the channel region via a gate oxide film 206d. Is formed by

Reference numeral 207 denotes a P formed in the N-type well 204.
A pair of P-type source / drain regions 207a and 207b formed on the surface of an N-type well 204 via a channel region, and a gate electrode 207c formed on the channel region via a gate oxide film 207d. Is formed by

Reference numeral 208 denotes an N-type bottom well 208a located below the P-type well 202 and the N-type well 204 over the entire area of the second logic circuit formation region 201 of the P-type substrate 100; Surrounding the second logic circuit formed in the region 201, and
And an N-type well potential separation region (hereinafter, referred to as an N-type separation region) having an N-type well wall 208b reaching the surface of the bottom well 208a from the surface of the bottom well 208a. The N-type isolation region 208 is electrically connected at a plurality of locations on the surface of the well wall 208b, and is connected to a power supply line (VDD, VDD, Is, for example, 5 V).

As described above, the power supply potential is applied to the N-type isolation region 208 at a plurality of locations on the surface of the well wall 208b and the power supply potential is applied via the N-type well 204. There is almost no potential difference over the entire region 208, and the potential is substantially set to the power supply potential.

Further, since a power supply potential is applied to the N-type isolation region 208 and a negative potential is applied to the P-type substrate 100, a reverse PN junction is formed between the N-type isolation region 208 and the P-type substrate 100. Bias is applied. Therefore, the N-type isolation region 2
08 functions as an electrical isolation region between the P-type substrate 100 and electrically isolates the P-type substrate 100 from the P-type well 202.

Referring back to FIGS. 3 and 4, reference numeral 301 denotes a memory circuit forming area in which a memory circuit arranged and designed based on a memory core already managed as a design resource is formed.

This memory circuit is a DRAM in the first embodiment, and as is generally known, one N
A memory cell array composed of a plurality of type MOS transistors and one capacitor, a memory cell array arranged in a matrix of a plurality of rows and a plurality of columns, a sense amplifier provided in each bit line pair of a bit line pair arranged in a plurality of columns, A row decoder for selecting a word line arranged in a predetermined row from word lines arranged in a row; a column decoder for selecting a predetermined bit line pair from a bit line pair arranged in a plurality of columns; It comprises a substrate potential generating circuit for applying a negative substrate potential (for example, about -1 V in the first embodiment) to the substrate 100 and a desired P-type well, and other peripheral circuits.

In order to stabilize against external noise and stabilize, for example, the substrate potential of the N-type MOS transistor forming the memory cell is set to a negative potential (for example, about -1 V) ( Hereinafter, an N-type MOS transistor to which a negative potential is given as a substrate potential including this N-type MOS transistor is generally referred to as an N-type transistor (negative). In addition, for example, in a row decoder, a column decoder, a substrate potential generating circuit, and the like, the substrate potential of the N-type MOS transistor is set to the ground potential in order not to hinder high-speed operation (hereinafter, an N-type MOS transistor (ground)).
).

The N-type transistor (ground), the N-type transistor (negative) and the P-type transistor constituting this memory circuit are formed as shown in FIG.

In FIG. 7, reference numerals 302a and 302b denote P-type wells (first well regions) formed in the memory circuit formation region 301. The P-type well 302a is electrically connected on the surface thereof, and a ground potential (VSS, for example, 0 V) is applied to a ground line (first wiring layer) 303a provided on the surface of the P-type substrate 100. P-type well 3
02b is electrically connected to the surface of the P-type substrate 1
A negative potential (VBB, for example, about -1 V) is applied from the substrate potential generating circuit via a second ground line (second wiring layer) 303b provided on the surface of the substrate 00.

Reference numerals 304a and 304b denote N-type wells (second well regions) formed in the memory circuit formation region 301. N-type wells 304a and 304b are electrically connected at their surfaces, and are provided with power supply lines (second wiring layers) 305a and 305 provided on the surface of P-type substrate 100.
A power supply potential (VDD, for example, 5 V in the first embodiment) is applied at b.

Reference numeral 306a denotes an N-type transistor (ground) formed in the P-type well 302a, and a pair of N-type source / drain regions 306aa and 306ab formed on the surface of the P-type well 302a via a channel region; The gate electrode 306ac is formed on the channel region via the gate oxide film 306ad. 306
b denotes an N-type transistor (negative) formed in the P-type well 302b, and a pair of N-type source / drain regions 3 formed on the surface of the P-type well 302b via a channel region.
06ba, 306bb and a gate electrode 306bc formed on the channel region via a gate oxide film 306bd
Is formed by

Reference numeral 307a denotes a P-type transistor formed in the N-type well 304a. A pair of P-type source / drain regions 307aa and 307ab formed on the surface of the N-type well 304a via the channel region, And a gate electrode 307ac formed via a gate oxide film 307ad. Reference numeral 307b denotes a P-type transistor formed in the N-type well 304b, and a pair of P-type source / drain regions 307ba, 307 formed on the surface of the N-type well 304b via a channel region.
7bb and a gate electrode 307bc formed on the channel region via a gate oxide film 307bd.

Reference numeral 308 denotes an N located below the P-type well 302a and the N-type well 304a over the entire area of the circuit formed of the N-type transistor (ground) formed in the memory circuit formation region 301 of the P-type substrate 100. N-type well potential isolation region (hereinafter referred to as N-type isolation) having a bottom well 308a of a mold type and an N-type well wall 308b surrounding the circuit and reaching the surface of the bottom well 308a from the surface of the P-type substrate 100. Area). A power supply potential is applied to the N-type isolation region 308 via the N-type well 304a.

Referring back to FIG. 3, reference numeral 401 denotes a P-type substrate 1
A power supply wiring layer (only a part is shown in the drawing) made of, for example, an aluminum layer formed on the semiconductor integrated circuit device over the power supply potential pad and connected to a power supply potential pad from outside the semiconductor integrated circuit device. In the first embodiment, 5 V) is applied. The power supply wiring layer 401 is a wiring layer for applying the power supply potential VDD to the first and second circuits and the memory circuit. The power supply wiring layer 401 is formed in the first logic circuit formation region 101 as shown in FIG.
The mold separation region 108 always has a portion that intersects with the surface of the well wall 108b.
Corresponds to the power supply line 109 shown in FIG.

Then, the power supply line 109 and the well wall 10
8b, the power line 109 and the well wall 10
8b is formed to electrically connect the contact cell 8b to the contact cell 8b. The contact cell 402 corresponds to a contact hole provided in an insulating layer interposed between the surface of the P-type substrate 100 and the power supply line 109 of the power supply wiring layer 401.

As shown in FIG. 8, the power supply wiring layer 401 always has a portion that intersects with the surface of the well wall 208b of the N-type isolation region 208 formed in the second logic circuit formation region 201. The wiring portion located at the intersection corresponds to the power supply line 209 shown in FIG. At the intersection of the power supply line 209 and the surface of the well wall 208b, a contact cell 403 for electrically connecting the power supply line 209 and the well wall 208b is formed. Contact cell 403
Are the power supply lines 2 on the surface of the P-type substrate 100 and the power supply wiring layer 401.
09 corresponds to a contact hole provided in an insulating layer interposed therebetween.

A power supply potential is applied to the N-type isolation region 208 and a negative potential is applied to the P-type substrate 100.
A reverse bias is applied to the PN junction between the mold separation region 208 and the P-type substrate 100. Therefore, the N-type isolation region 208 functions as an electrical isolation region with the P-type substrate 100,
The P-type substrate 100 and the P-type well 202 are electrically separated.

Next, the DRAM shown in FIGS.
N-type isolation regions 108 and 2 in first and second logic circuit formation regions 101 and 201 of a built-in semiconductor integrated circuit
An apparatus and method for generating a mask pattern data for dynamically generating a mask pattern for the bottom well 108a and the well wall 108b for forming the mask 08 will be described with reference to FIGS.

FIG. 1 is a flowchart showing the operation of the mask pattern data generation device according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes information on a wafer process for manufacturing a semiconductor integrated circuit device, that is, a manufacturing process, and 2 denotes logic information describing the operation of the first and second integrated circuits and the memory circuit, which is stored in a logic information storage means. ing. Reference numeral 3 denotes cell information of cells such as AND gates, OR gates, exclusive OR gates, and flip-flops prepared in advance, core information of logic cores already managed as design resources, and cores of memory cores already managed as design resources. The information is stored in the cell core information storage means.

ST1 denotes first and second logic circuit forming regions 101 and 201 in which first and second integrated circuits and memory circuits are formed, and memory forming region 301.
In a region specifying step of specifying (referred to as a cell arrangement region) on the surface of the P-type substrate 100, the process information 1 of the wafer, the logical information 2 from the logical information storage unit, and the cell
The cell information 3 and the core information 3 from the core information storage means are specified by the area specifying means of the automatic placement and routing apparatus.

In this region designation step ST1, the positions of the first and second logic circuit formation regions 101 and 201 and the memory circuit formation region 301 on the surface of the P-type substrate 100 are determined, and the second logic circuit and the second logic circuit are formed. Components such as transistors that constitute the memory circuit include:
In each of the second logic circuit formation region 201 and the memory circuit formation region 301, the arrangement is entirely determined.

ST2 is a cell arrangement designating step for automatically arranging the cells constituting the first logic circuit on the surface of the first logic circuit formation region 101. The automatic arrangement and wiring is performed by the cell information 3 from the cell / core information storage means. It is specified by the cell arrangement specifying means of the device. In the cell arrangement designating step ST2, the arrangement of the cells constituting the first logic circuit, and finally the components such as the transistors constituting the cells, is determined in the first logic circuit formation region 101.

ST3 is a wiring position designating step for designating wiring positions in the first and second logic circuits and the memory circuit and wiring positions between the circuits. The configuration of transistors and the like in the first logic circuit is performed. The wiring position between the elements is specified by the wiring position specifying means of the automatic placement and routing apparatus based on the logical information 2 describing the operation of the first logic circuit from the logical information storing means and the cell information 3 from the cell / core information storing means. The wiring positions between components such as transistors and the wiring positions between the circuits in the respective circuits of the second logic circuit and the memory circuit describe the operation of the second logic circuit and the memory circuit from the logical information storage means. Based on the logical information 2 and the core information 3 from the cell / core information storage means, the wiring position specifying means of the automatic placement and routing apparatus It is specified Te. In the wiring position designation step ST3, the first ground lines 103, 20
3, 303a, the second ground line 303b, and the power line 1
The arrangement positions of 05, 109, 205, 209, 305a, and 305b are also specified.

ST4 is the first logic circuit formation region 10
1, the bottom well 108a of the N-type isolation region 108
And the bottom well 20 of the N-type isolation region 208 in the well wall 108b and the second logic circuit formation region 201
This is a separation region pattern generation step of generating a mask pattern for forming the 8a and the well wall 208b. In the separation area pattern generation step ST4, the bottom well pattern generation means of the automatic placement and routing apparatus performs the first generation based on the information of the first and second logic circuit formation areas 101 and 201 specified in the area specification step ST1. N-type isolation region 108 located under P-type well 102 and N-type well 104 over the entire first logic circuit formation region 101 where the logic circuit is formed.
Of the bottom well 108a and the second logic circuit formation region 201 where the second logic circuit is formed.
A mask pattern for forming the bottom well 208a of the N-type isolation region 208 located below the mold well 202 and the N-type well 204 is generated.

Further, the well wall pattern generating means of the automatic placement and routing apparatus generates the information of the first and second logic circuit forming areas 101 and 201 specified in the area specifying step ST1 and the bottom well pattern generating means. Wells 108a and 208a in the mask pattern
Is performed by using the information of the first well and the first well formed in the first logic circuit forming region 101 and surrounding the first well from the surface of the P-type substrate 100.
08 a of the N-type isolation region 108
b and an N-type isolation region 208 surrounding the second logic circuit formed in the second logic circuit formation region 201 and reaching the bottom well 208a from the surface of the P-type substrate 100
A mask pattern for forming the well wall 208b is generated.

ST5 is a separation area pattern generation step S
This is a layout verification step for verifying whether the contents of the mask pattern created up to T4 do not violate the wafer process information 1 or match the logic information 2. 4 is the layout data of the final mask pattern,
It is stored in the layout storage means.

FIG. 2 shows a specific step in the separation region pattern generation step ST4 of FIG.
13 is a flowchart showing whether to generate a mask pattern of FIGS. In FIG. 2, ST41 denotes bottom wells 108a, 20 of N-type isolation regions 108, 208.
In the bottom well pattern generation step of automatically generating the mask pattern data 8a, the first and second logic circuit formation areas 101 and 201 specified in the area specification step ST1 by the bottom well pattern generation means.
Bottom wells 108a, 20 having a planar shape slightly larger than the planar regions of the first and second logic circuit formation regions 101, 201 on the entire circumference based on the information of FIG.
8a for forming the bottom wells 108a and 208a
Is generated.

ST42 is a well wall pattern generation step for automatically generating a mask pattern for the well walls 108b and 208b of the N-type isolation regions 108 and 208. The first is specified by the well wall pattern generation means in the area specification step ST1. And second logic circuit formation region 10
The bottom well 108 in the mask pattern generated by the information of 1,201 and the bottom well pattern generating means
By performing an operation using the information of the bottom wells 108a and 208a, the first
And well walls 10b for forming well walls 108b, 208b each having a planar shape corresponding to a protruding region around the entire periphery of second logic circuit forming regions 101, 201.
8b and 208b mask patterns are generated. In the above calculation, the information indicating the outer circumference of the bottom wells 108a and 208a is defined as the outer circumference, and the information indicating the outer circumference of the first and second logic circuit formation regions 101 and 201 is defined as the inner circumference. Is an operation to be performed.

In step ST43, the distance between the well wall 108b generated in the well wall pattern generation step ST42 and each of the N-type wells 104 formed in the first logic circuit formation region 101 is checked in the planar shape. If this interval is greater than 0 and less than a predetermined value (corresponding to the minimum width of the components constituting the first logic circuit), the correction information is output as graphic data and generated in the well wall pattern generation step ST42. Well wall 2
The gap in the planar shape between the 08b and each of all the N-type wells 204 formed in the second logic circuit formation region 201 is checked, and this gap exceeds 0 and has a predetermined value (the configuration of the second logic circuit). If it is less than the minimum width of the element), an interval check step of outputting correction information as graphic data is processed by an interval check unit of the automatic placement and routing apparatus.

ST44 is an interval check step ST43.
The well walls 108b, 20 generated in the well wall pattern generation step ST42 based on the correction information obtained in
In a well wall pattern correction step of adding a well wall corresponding to the correction information to the 8b and automatically generating a corrected mask pattern of the well walls 108b and 208b, the well wall pattern correction unit of the automatic placement and routing apparatus performs processing. You.

In the first embodiment, N-type wells 104 formed in first and second logic circuit formation regions 101 and 201 and memory circuit formation region 301 are formed.
Since the well walls 108b and 208b are formed simultaneously with the well walls 204b and 208b, the corrected mask pattern of the well walls 108b and 208b originally has the cell information 3 for the first and second logic circuits and the memory circuit. Is synthesized with the well mask pattern based on the information of the N-type wells 104, 204, 304a, 304b and the well wall 308b which were in the core information 3.

ST45 is a step of correcting the well wall patterns 108b, 2 generated in the well wall pattern correction step ST44.
Well wall 108 corrected by mask pattern 08b
In an overlap detection step of detecting an overlap between the information of b and 208b and the wiring arrangement of the power supply wiring designated in the wiring position designation step ST3, the overlap detection means of the automatic placement and routing apparatus performs arithmetic processing.

In ST46, the P-type substrate 1 prepared in advance is placed at the overlap position detected in the overlap detection step ST45.
In a contact cell arranging step of automatically arranging contact cells for electrically connecting the surface of the P. 00 and the power supply wiring layer, the arrangement is designated by the contact cell arrangement designating means of the automatic arrangement and wiring device.

Next, a method of generating mask pattern data will be described. First, wafer process information 1, first
And logic information 2 describing the operation of the second integrated circuit and the memory circuit, cell information 3 of the first logic circuit,
The core information 3 of the logic circuit and the memory circuit is prepared in advance. As such information, information defined conventionally may be used as it is. Then, by using these pieces of information, in the area specifying step ST1 shown in FIG. 1, the arrangement positions of the first and second logic circuit formation areas 101 and 102 and the memory circuit formation area 301 are designated to perform automatic arrangement. Then, in the cell arrangement designating step ST2 shown in FIG.
The automatic placement is performed by designating the placement positions of the cells constituting the logic circuit. In the wiring position specification step ST3 shown in FIG. 1, the wiring positions of all the wirings are specified and automatically arranged.

Next, the first and second logic circuit formation regions 101, 1 designated in the region designation step ST1
A graphic operation is performed to oversize the information No. 02 by a value suitable for the design reference value of the wafer process. Based on the information of the oversized area, the bottom well 10
The mask patterns 21 of 8a and 208a are obtained (bottom well pattern generation step ST41 in FIG. 2). The mask pattern 21 is formed, for example, as shown in FIG. 9, so that light is irradiated on a region 21a indicated by oblique lines on the surface of the P-type substrate 100.

Bottom well pattern generation step ST4
1 in the mask patterns 21 of the bottom wells 108a and 208a obtained in
A graphic operation of subtracting the information of the first and second logic circuit formation regions 101 and 102 designated in the region designation step ST1 from the information of a is performed, and the well walls 108b and 208 are obtained.
The mask pattern 22 of b is obtained (well wall pattern generation step ST42 in FIG. 2). This mask pattern 22
Is formed, for example, as shown in FIG. 10, so that light is applied to a region 22b indicated by oblique lines on the surface of the P-type substrate 100.

Then, a well wall pattern generation step S
The information of the well walls 108b and 208b of the mask pattern 22 of the well walls 108b and 208b obtained at T42 and the first and second logic circuits originally set in the cell information 3 and the core information 3 are formed. Information of all the N-type wells 104 and 204, the distance between the well wall 108b and the N-type well 104, the well wall 208
The distance between b and the N-type well 204 is calculated, and the calculation result is compared with a predetermined value to obtain correction information and obtain graphic information (the interval check step ST4 in FIG. 2).
3). The graphic information based on the correction information is, for example, as shown in FIG.
As shown in FIG. 5, when the distance between the well wall 108b (208b) and the N-type well 104 (204) is smaller than a predetermined value, the well wall 108b (208b) and the N-type well 104
This is information on a plane figure that fills the space between the sides facing (204). This graphic information is converted into a well wall pattern generation step ST.
The corrected mask pattern of the well walls 108b, 208b is obtained by adding to the well walls 108b, 208b generated in 42 (well wall pattern correction step S in FIG. 2).
T44).

Then, the corrected well walls 108b, 2
Well walls 108b and 208b of the mask pattern 08b
Calculation of the information of the N-type wells 104, 204, 304a, 304b and the well wall 308b which were originally included in the cell information 3 and the core information 3 for the first and second logic circuits and the memory circuit. Is performed to obtain a combined well mask pattern for simultaneously forming the well wall and the N-type well.

Thereafter, the well wall pattern correction step S
The corrected well walls 108b and 20 generated in T44
Well wall 108 corrected by mask pattern 8b
The logical product of the information of the power lines b and 208b and the information of the wiring position of the power supply wiring designated in the wiring position designation step ST3 is subjected to a graphic operation to detect the overlap between the well walls 108b and 208b and the power supply wiring (the overlap in FIG. 2). Detection step ST45).
Then, the contact cell 402 is provided at the overlap position detected in the overlap detection step ST45 based on the information of the contact cell for electrically connecting the surface of the P-type substrate 100 and the power supply wiring layer prepared in advance. , 403 are automatically arranged.

Thereafter, layout verification step ST in FIG.
After verifying the layout in step 5, if there is no problem, the layout data obtained in the above steps (of course, the mask patterns 21 and 22 for forming the N-type isolation regions 108 and 208) are stored in the layout storage means. (Including data) and is used when manufacturing a semiconductor integrated circuit with a built-in DRAM.

As described above, according to the first embodiment, the conventionally defined information 1 of the wafer process, the logical information 2 describing the operation of the first and second integrated circuits and the memory circuit, the second Cell information 3 of the first logic circuit, core information 3 of the second logic circuit and the memory circuit
, Mask patterns 21 and 22 for forming N-type isolation regions 108 and 208 can be designed based on an automatic placement and routing apparatus. In other words, N-type isolation regions 108 and 208 can be designed.
8 can be automatically set for the P-type substrate. This has the effect of eliminating design effort and human error due to manual work.

Since the supply of the power supply potential to the N-type isolation regions 108 and 208 is performed through the N-type wells 104 and 204 and from a plurality of locations on the surface of the well walls 108b and 208b, the N Mold separation area 1
Since the potential distributions of the transistors 08 and 208 become nearly uniform, the electrical isolation effect of the N-type isolation regions 108 and 208 is improved.

In the first embodiment, a P-type semiconductor substrate is used as the semiconductor substrate.
A similar effect can be obtained by using an N-type semiconductor substrate. In this case, sectional views of main parts in the first and second logic circuit forming regions 101 and 201 and the memory circuit forming region 301 are shown in FIGS.

At this time, the first power supply potential (VDD1, in this embodiment 1, applied from the substrate potential generation circuit formed in the memory circuit formation region 301, for example, 6 V) is applied to the N-type semiconductor substrate 100. The ground potential (V) is applied to the P-type well 102 formed in the first logic circuit formation region 101.
SS, for example, 0 V), the first logic circuit formation region 10
1 is connected to the second power supply potential (V
DD2, for example, 5V, is applied to the ground potential (VS) in the P-type well 102 formed in the second logic circuit formation region 201.
S, for example, 0 V) in the second logic circuit formation region 20
1 is connected to the second power supply potential (V
DD2 (for example, 5V) is applied to the P-type wells 302a and 302b formed in the memory circuit formation region 301, and the ground potential (VSS, for example 0V) is applied to the memory circuit formation region 30.
The second power supply potential (VDD2, for example, 5 V) is applied to the N-type well 304a formed in the memory circuit formation region 30.
The first power supply potential (VDD1, for example, 6 V) is applied to the N-type well 304b formed in the first.

Also in the semiconductor integrated circuit device with a built-in DRAM constructed as described above, mask pattern data can be created according to the flowcharts shown in FIGS.

Embodiment 2 FIGS. 15 to 18 show a second embodiment of the present invention. The second embodiment differs from the first embodiment in that a power supply potential is applied to N-type isolation regions 108 and 208 and an isolation region pattern is generated accordingly. Only the specific configuration of step ST4 is different,
The other points are the same.

Accordingly, the above differences will be mainly described below. 15 to 18, the same reference numerals as those in the first embodiment denote the same or corresponding parts.

First, the DRAM according to the second embodiment
N-type isolation regions 108 and 20 in embedded semiconductor integrated circuit
How the power supply potential is applied to 8 will be described with reference to FIG.

FIG. 15 shows the first logic circuit formation region 10.
N-type isolation region 108 (208) formed in first or second logic circuit formation region 201 and power supply potential (VD
D is a diagram mainly showing a relationship with a power supply line 109 (209) for applying 5 V in the second embodiment).
Since the method of applying the power supply potential to the N-type isolation regions 108 and 208 is based on the same concept, the description is complicated. Therefore, the method of applying the power supply potential to the N-type isolation region 108 will be described.

In FIG. 15, reference numeral 108 denotes a P-type substrate 100
N located below the P-type well 102 and the N-type well 104 over the entire first logic circuit formation region 101 of FIG.
A bottom well 108a of the mold and an N-type well wall 108b surrounding the first logic circuit formed in the first logic circuit formation region 101 and reaching the surface of the bottom well 108a from the surface of the P-type substrate 100; Is an N-type isolation region having The outer periphery of the well wall 108b is formed so as to be located outside the outer periphery of the bottom well 108a.

Reference numeral 401 denotes a power supply wiring layer (only a part is shown in the drawing) formed of, for example, an aluminum layer formed on the P-type substrate 100 via an insulating layer. A power supply potential (VDD, 5 V in the second embodiment) is applied from the outside. The power supply wiring layer 401 is a wiring layer for applying the power supply potential VDD to the first and second circuits and the memory circuit. The power supply wiring layer 401 is electrically connected to a plurality of sub power supply wiring layers 404 formed in the first logic circuit formation region 101, and supplies a power supply potential to the first logic circuit. In the second embodiment, the sub power supply wiring layer 404 is
1 and is electrically connected to the power supply wiring layer 401 via the contact cell 405.

Reference numeral 109 denotes a well wall 1 of the N-type isolation region 108
A power supply line is disposed on the surface of the first semiconductor chip 08b so as to face the first logic circuit, and is electrically connected to the power supply wiring layer 401. In the second embodiment, power supply line 109 is integrally formed of the same aluminum layer as power supply wiring layer 401. Power line 109 and well wall 108b
Electrical connection to the surface is made by a plurality of contact cells 402 arranged at a predetermined interval. The contact cell 402 corresponds to a contact hole provided in an insulating layer interposed between the surface of the P-type substrate 100 and the power supply line 109 of the power supply wiring layer 401.

Reference numeral 501 denotes a ground wiring layer formed on the P-type substrate 100 via an insulating layer (only a part is shown in the figure).
And the ground potential (VSS, 0 V in the second embodiment) connected to the ground potential pad from outside the semiconductor integrated circuit device.
Is applied. In the second embodiment, unlike the power supply wiring layer 401, the ground wiring layer 501
It is made of the same aluminum layer as that of the aluminum layer 04. The ground wiring layer 501 connects the ground potential VS to the first and second circuits and the memory circuit.
This is a wiring layer for giving S. This ground wiring layer 501
Is electrically connected to a plurality of sub-ground wiring layers 502 formed in the first logic circuit formation region 101 and supplies a power supply potential to the first logic circuit. Secondary ground wiring layer 502
Is formed of the same aluminum layer as the sub power supply wiring layer 404 unlike the power supply wiring layer 401 in the second embodiment.
It is formed integrally with the ground wiring layer 501. W1 is the well wall 1
The width 08b and the width W2 indicate the width of the bottom well 108a.

In the semiconductor integrated circuit device with a built-in DRAM configured as described above, power supply potential VDD supplied from power supply wiring layer 401 is applied to N-type well 104 via contact cell 405 and sub power supply wiring layer 404. And
The power supply line 1 is supplied to the bottom well 108a.
09 and the plurality of contact cells 402, the power supply potential VDD is also applied to the well wall 108b. Therefore,
The power supply potential VDD is supplied to the N-type isolation region 108 almost uniformly with almost no potential difference between the regions. As a result, the electrical isolation effect of the N-type isolation region 108 is further improved.

Next, the first and second logic circuit formation regions 1 of the DRAM integrated semiconductor integrated circuit shown in FIG.
01 and 201, the bottom well 108a and the well wall 108b for forming the N-type isolation regions 108 and 208
Referring to FIG. 16, a description will be given of a mask pattern data generating apparatus and method for automatically generating the mask pattern of FIG.

FIG. 16 is a flowchart showing a specific configuration of the separation region pattern generation step ST4 of the flowchart showing the operation of the mask pattern data generation device shown in FIG. 1. In FIG.
In the bottom well pattern generation step of automatically generating the mask pattern data of the bottom wells 108a and 208a of the first and second logic circuits 08 and 208, the first and second logic circuit formation areas specified in the area specification step ST1 by the bottom well pattern generation means. The first and second logic circuit forming regions 101,
A mask pattern for the bottom wells 108a and 208a for forming the bottom wells 108a and 208a having a planar shape slightly larger on the entire circumference with respect to the plane area 201 is generated.

ST41 'is the N-type isolation regions 108, 208
In the power supply wiring generation step for automatically generating a mask pattern of the power supply lines 109 and 209 for applying a power supply potential to the bottom wells 108a and 208a obtained by the bottom well pattern generation means by the power supply line pattern generation means
Wells 108a, 20a in the mask pattern of FIG.
A power supply line slightly larger than the plane area of the first and second logic circuit formation areas 101 and 201 over the entire circumference based on the information indicating the outer circumference of 8a and having a planar shape surrounding the first and second logic circuits. A mask pattern for the power supply lines 109 and 209 for forming 109 and 209 is generated. This mask pattern is combined with the mask pattern of the power supply wiring layer 401.

ST42 is a well wall pattern generation step for automatically generating a mask pattern for the well walls 108b and 208b of the N-type isolation regions 108 and 208.
By performing an operation using the information of the power supply lines 109 and 209 in the mask pattern of the power supply lines 109 and 209 obtained in 1 ′, the bottom well 108 in the planar shape is obtained.
a, 208a overlap the entire periphery of the first and second logic circuit formation regions 101, 201, and
Well wall 1 having a slightly larger planar shape on the outer periphery
08b, 208b to form well walls 108b,
A mask pattern 208b is generated.

In step ST43, the space between the well wall 108b generated in the well wall pattern generation step ST42 and all the N-type wells 104 formed in the first logic circuit formation region 101 is checked in a planar shape. If this interval is greater than 0 and less than a predetermined value (corresponding to the minimum width of the components constituting the first logic circuit), the correction information is output as graphic data and generated in the well wall pattern generation step ST42. Well wall 2
The gap in the planar shape between the 08b and each of all the N-type wells 204 formed in the second logic circuit formation region 201 is checked, and this gap exceeds 0 and has a predetermined value (the configuration of the second logic circuit). If it is less than the minimum width of the element), an interval check step of outputting correction information as graphic data is processed by an interval check unit of the automatic placement and routing apparatus.

ST44 is an interval check step ST43
The well walls 108b, 20 generated in the well wall pattern generation step ST42 based on the correction information obtained in
In a well wall pattern correction step of adding a well wall corresponding to the correction information to the 8b and automatically generating a corrected mask pattern of the well walls 108b and 208b, the well wall pattern correction unit of the automatic placement and routing apparatus performs processing. You. In the second embodiment, N-type wells 104 and 20 formed in first and second logic circuit formation regions 101 and 201 and memory circuit formation region 301 are formed.
4, 304a, 304b and the well wall 308b are simultaneously formed with the well walls 108b, 208b, so the corrected mask pattern of the well walls 108b, 208b is
Originally, it is synthesized into a well mask pattern based on the information of the N-type wells 104, 204, 304a, 304b and the well wall 308b in the cell information 3 and the core information 3 for the first and second logic circuits and the memory circuit.

ST45 'is the well walls 108b, 208b
In a connection point specifying step of specifying a plurality of connection points between the surface and the power supply lines 109 and 209, the corrected well wall 108b generated in the well wall pattern correction step ST44 by the connection point specifying means of the automatic placement and routing apparatus. , 2
Well wall 108 corrected by mask pattern 08b
b, 208b and power supply wiring generation step ST41 '
The arithmetic processing is performed according to the wiring positions of the power supply wirings 109 and 209 designated by.

ST46 is a connection point designation step ST4.
At the position designated by 5 ', the P substrate 10 prepared in advance
In a contact cell arranging step for automatically arranging contact cells for electrically connecting the surface of the power supply line 0 and the power supply wiring layer, the arrangement is designated by the contact cell arrangement designating means of the automatic arrangement and wiring apparatus.

Next, a method of generating mask pattern data will be described. First, similarly to Embodiment 1 described above,
Using wafer process information 1, logic information 2 describing the operation of the first and second integrated circuits and the memory circuit, cell information 3 of the first logic circuit, and core information 3 of the second logic circuit and the memory circuit In the area designation step ST1 shown in FIG. 1, the first and second logic circuit formation areas 101 and 201 and the memory circuit formation area 30
The automatic placement is performed by designating the placement position of FIG.
In the cell arrangement designating step ST2 shown in (1), automatic arrangement is performed by designating the arrangement position of the cells constituting the first logic circuit in the first logic circuit formation area 101. In the wiring position specification step ST3 shown in FIG. 1, the wiring positions of all the wirings are specified and automatically arranged.

Next, in the bottom well pattern generation step ST41 shown in FIG. 16, the first and second logic circuit formation regions 1 designated in the region designation step ST1
A graphic operation for oversizing the information of 01 and 201 by a value suitable for the design reference value of the wafer process is performed. The mask pattern 21 of the bottom wells 108a and 208a is obtained based on the information of the oversized region. The mask pattern 21 is formed, for example, as shown in FIG. 17, so that light is applied to a region 21a shown inside the frame on the surface of the P substrate 100.

Thereafter, the bottom wells 108a and 208a obtained in the bottom well pattern generation step ST41 are obtained.
Of the bottom well 108a in the mask pattern 21 of FIG.
With the information indicating the outer periphery of the 208a as a center line, a calculation process is performed according to the wafer process or based on the specified width, and based on the calculation result,
A mask pattern for the power supply lines 109 and 209 is obtained (FIG. 16).
Power supply wiring generation step ST41 ′). This mask pattern is, for example, as shown in FIG.
Is formed so that light is applied to a region 28a indicated by oblique lines on the surface of the device. The mask pattern of the power supply lines 109 and 209 is added to the mask pattern of the power supply wiring layer 401 arranged in the wiring position designation step ST3, and a corrected mask pattern of the power supply wiring layer 401 is obtained.

In the well wall pattern generation step ST42, the power supply line 10 in the mask pattern of the power supply lines 109 and 209 obtained in the power supply wiring generation step ST41 'is used.
The information of 9 and 209 is oversized according to the information of the wafer process to obtain the mask pattern 22 of the well walls 108b and 208b. For example, as shown in FIG. 18, the mask pattern 22 is formed in a region 29a (a region between the innermost frame and the outermost frame shown in FIG. 18) on the surface of the P-type substrate 100. It is formed so as to be irradiated with light.

Then, a well wall pattern generation step S
The information of the well walls 108b and 208b of the mask pattern 22 of the well walls 108b and 208b obtained at T42 and the first and second logic circuits originally set in the cell information 3 and the core information 3 are formed. Information from all the N-type wells 104 and 204, the distance between the well wall 108b and the N-type well 104, the well wall 2
The interval between the 08b and the N-type well 204 is calculated, and the calculation result is compared with a predetermined value to obtain correction information and obtain as graphic information (the interval check step ST in FIG. 16).
43).

The graphic information based on the correction information is, for example,
As shown in FIG. 11, when the distance between the well wall 108b (208b) and the N-type well 104 (204) is less than a predetermined value, the well wall 108b (208b) and the N-type well 104 (204) are opposed to each other. It becomes information of a plane figure that fills the space between sides. This graphic information is added to the well walls 108b and 208b generated in the well wall pattern generation step ST42, and corrected mask patterns of the well walls 108b and 208b are obtained (well wall pattern correction step ST44 in the figure).

Then, the corrected well walls 108b, 2
08b, the well walls 108b, 20 of the mask pattern 22
8b and the N-type wells 104, 204, 304a, 304b originally contained in the cell information 3 and the core information 3 for the first and second logic circuits and the memory circuit.
Then, a graphic operation of adding the information of the well wall 308b is performed to obtain a combined well mask pattern for simultaneously forming the well wall and the N-type well.

Thereafter, a connection point designation step ST45 '
The well walls 108b, 208b corrected by the mask pattern 22 of the corrected well walls 108b, 208b generated in the well wall pattern correction step ST44.
A plurality of connection points between the surfaces of the well walls 108b, 208b and the power supply lines 109, 209 are obtained based on the information of the power supply lines 109, 209 specified in the power supply line generation step ST41 '. Then, in a contact cell arrangement step ST46, a connection point designation step ST45 'is performed.
The contact cell 402, the contact cell for electrically connecting the surface of the P-type substrate 100 and the power supply wiring layer prepared in advance to each of the plurality of connection locations determined in the above. 403 is automatically arranged.

Thereafter, layout verification step ST in FIG.
After verifying the layout in step 5, if there is no problem, the layout storage means (including, of course, mask pattern data for forming the N-type isolation regions 108 and 208) is stored in the layout storage means. ) Is stored and used when manufacturing a semiconductor integrated circuit with a built-in DRAM.

As described above, according to the second embodiment, similarly to the first embodiment, N-type isolation regions 108 and 20 are formed.
8 can be designed based on an automatic placement and routing apparatus, in other words, the N-type isolation region 10 can be designed.
The arrangement of 8,208 with respect to the P-type substrate 100 can be automatically set. In addition, the arrangement of the power supply lines 109 and 209 for applying a power supply potential to the P-type substrate at a plurality of locations on the surfaces of the well walls 108b and 208b of the N-type isolation regions 108 and 208 can be automatically set. This has the effect of eliminating design effort and human error due to manual work.

The supply of the power supply potential to the N-type isolation regions 108 and 208 is performed through the N-type wells 104 and 204, and the wells are provided by the power supply lines 109 and 209 opposed to the surfaces of the well walls 108b and 208b. Wall 108
Since the process is performed from a plurality of locations on the surfaces of the b and 208b, the potential distribution of the N-type isolation regions 108 and 208 is substantially uniform, and the effect of further improving the electrical isolation effect by the N-type isolation regions 108 and 208 is improved. Have.

Embodiment 3 FIG. FIGS. 19 to 22 show a third embodiment of the present invention, which differs from the first embodiment only in the specific configuration of the separation region pattern generation step ST4, and is otherwise the same. Therefore, the above-described differences, particularly, the well wall pattern generation step ST42 will be mainly described below. FIG.
9 to 22, the same reference numerals as those in the first embodiment denote the same or corresponding parts.

Well Wall Pattern Generation Step ST42
Are N-type isolation regions 108 and 208 as shown in FIG.
Is a step of automatically generating the mask pattern 22 of the well walls 108b, 208b of the first and second logic circuit formation regions 101, 201 and the memory circuit designated in the region designation step ST1 by the well wall pattern generation means. By performing an operation using the information of the formation region 301, the well walls 108b, which have a planar shape corresponding to regions other than the first and second logic circuit formation regions 101 and 201 and the memory circuit formation region 301 in the planar shape, are obtained. Well wall 108 for forming 208b
b, 208b are generated.

Next, a method of generating mask pattern data will be described. First, similarly to Embodiment 1 described above,
Using wafer process information 1, logic information describing the operation of the first and second integrated circuits and the memory circuit 2, cell information 3 of the first logic circuit, and core information 3 of the second logic circuit and the memory circuit In the area designation step ST1 shown in FIG. 1, the first and second logic circuit formation areas 101 and 102 and the memory circuit formation area 30
The automatic placement is performed by designating the placement position of FIG.
In the cell arrangement designating step ST2 shown in (1), automatic arrangement is performed by designating the arrangement position of the cells constituting the first logic circuit in the first logic circuit formation area 101. Further, in the wiring position specifying step ST3 shown in FIG. 1, the wiring positions of all the wirings are specified and automatically arranged.
Bottom well pattern generation step ST41 shown in FIG.
(Bottom well pattern generation step ST shown in FIG. 19)
41), a mask pattern 21 for the bottom wells 108a and 208a is obtained.

Next, in the well wall pattern generation step ST42 of FIG. 19, the first and second logic circuit formation regions 10 designated in the region designation step ST1 are set.
By performing an operation using the information of the first and second logic circuit formation regions 101 and 201 and the memory circuit formation region 301, a planar shape corresponding to the region other than the first and second logic circuit formation regions 101 and 201 and the memory circuit formation region 301 is obtained. The mask pattern 22 of the well walls 108b, 208b for forming the well walls 108b, 208b to be formed is generated. In other words, the mask pattern 22 of the well walls 108b and 208b is formed by the first and second logic circuit formation regions 101 and 201 and the memory circuit formation region 301.
Becomes the inverted shape of the planar shape of The mask pattern 22
For example, as shown in FIG. 20, it is formed such that light is applied to a region 22a indicated by oblique lines on the surface of the P-type substrate 100.

Then, as in the first embodiment,
To obtain graphic information based on the correction information in the interval check step ST43, obtain the mask pattern 22 of the well walls 108b, 208b corrected in the well wall pattern correction step ST44, and simultaneously form the well wall and the N-type well. Is obtained.

Thereafter, in the overlap detection step ST45, the well walls 108b, 208b corrected by the mask pattern 22 of the corrected well walls 108b, 208b generated in the well wall pattern correction step ST44.
And the information on the wiring position of the power supply wiring designated in the wiring position designation step ST3 and a logical product thereof, and detects the overlap between the well walls 108b, 208b and the power supply wiring layer 401. Find the connection point of The information of the contact cell for electrically connecting the surface of the P-type substrate 100 and the power supply wiring layer 401 prepared in advance is also stored at each of the plurality of connection positions determined in the overlap detection step ST45. At this time, the contact cells 402 and 403 are automatically arranged.

In this manner, the power supply wiring layer 401 (with the power supply lines 109 and 209 inside) and the well walls 108b and 208
The electrical connection with b is as shown in FIGS. 19 and 20.

Thereafter, layout verification step ST in FIG.
After verifying the layout in step 5, if there is no problem, the layout storage means (including, of course, mask pattern data for forming the N-type isolation regions 108 and 208) is stored in the layout storage means. ) Is stored and used when manufacturing a semiconductor integrated circuit with a built-in DRAM.

As described above, according to the third embodiment, the same effects as in the first embodiment can be obtained.

[0110]

As described above, according to the present invention, the information of the first integrated circuit formation region designated by the region designation means and the bottom well in the mask pattern generated by the bottom well pattern generation means are provided. And forming a second conductivity type well wall surrounding the first integrated circuit formed in the first integrated circuit formation region and reaching the bottom well from the surface of the semiconductor substrate based on the information of So
Since the mask pattern of the well wall can be automatically generated, it is possible to reduce the design labor and eliminate human error, which has an effect of reducing manufacturing costs such as labor costs.

According to the present invention, the second conductive type bottom well located under the first well region and the first integrated circuit formation region over the entire first integrated circuit formation region of the semiconductor substrate are provided. A well potential isolation region surrounding the first integrated circuit to be formed and having a second conductivity type well wall reaching the bottom well from the surface of the semiconductor substrate; and electrically connected to the surface of the first well region at the surface of the first well region And the first potential is
A first wiring layer transmitting to the second well region and a second wiring layer electrically connected to a surface of the second well region and transmitting a second potential different from the first potential to the second well region. A third potential electrically connected to the wiring layer at the surface of the well potential separation region to apply a reverse bias to the PN junction between the well potential separation region and the semiconductor substrate to the well potential separation region. Since the configuration is such that the wiring layer is provided, there is an effect that the separation effect by the well potential separation region is further improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an operation of a mask pattern data generation device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a main part operation of the mask pattern data generation device according to the first embodiment of the present invention.

FIG. 3 is a schematic plan view showing a semiconductor integrated circuit device with a built-in DRAM according to the first embodiment of the present invention;

FIG. 4 is a schematic plan view showing a formation region of each circuit in the semiconductor integrated circuit device with a built-in DRAM according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view of a principal part in a first logic circuit formation region of the semiconductor integrated circuit device with a built-in DRAM according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view of a principal part in a second logic circuit formation region of the semiconductor integrated circuit device with a built-in DRAM according to the first embodiment of the present invention;

FIG. 7 is a cross-sectional view of a main part in a memory circuit formation region of the semiconductor integrated circuit device with a built-in DRAM according to the first embodiment of the present invention;

FIG. 8 is an enlarged view showing a region C in FIG. 3;

FIG. 9 is a diagram for explaining a mask pattern of a bottom well according to the first embodiment of the present invention.

FIG. 10 is a diagram for explaining a mask pattern of a well wall according to the first embodiment of the present invention.

FIG. 11 is a diagram for explaining a mask pattern for obtaining a well wall to be corrected according to the first embodiment of the present invention;

FIG. 12 is a cross-sectional view of a principal part in a first logic circuit formation region of the semiconductor integrated circuit device with a built-in DRAM in another example according to the first embodiment of the present invention;

FIG. 13 is a cross-sectional view of a principal part in a second logic circuit formation region of the semiconductor integrated circuit device with a built-in DRAM in another example according to the first embodiment of the present invention;

FIG. 14 is a cross-sectional view of a main part in a memory circuit formation region of a semiconductor integrated circuit device with a built-in DRAM in another example according to the first embodiment of the present invention;

FIG. 15 is a schematic plan view showing a main part of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 16 is a flowchart showing an operation of a main part of the mask pattern data generation device according to the second embodiment of the present invention;

FIG. 17 is a diagram illustrating a mask pattern of a bottom well and a power supply line according to a second embodiment of the present invention;

FIG. 18 is a diagram for illustrating a mask pattern of a bottom well, a power supply line, and a well wall according to the second embodiment of the present invention.

FIG. 19 is a flowchart showing an operation of a main part of the mask pattern data generation device according to the third embodiment of the present invention;

FIG. 20 is a diagram for explaining a mask pattern of a well wall according to the third embodiment of the present invention.

FIG. 21 is a schematic plan view showing a main part of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 22 is an enlarged view showing a region D in FIG. 21.

[Explanation of symbols]

100 P-type substrate (semiconductor substrate), 101 first logic circuit formation region, 102, 202, 302a, 302
b P-type well (first well region), 103, 20
3, 303a first ground line (first wiring layer), 10
4, 204, 304a, 304b N-type well (second well region), 105, 205, 305a, 305b
Power supply line (second wiring layer), 106, 206, 306a,
306b N-type transistors, 107, 207, 307
a, 307b P-type transistors, 108, 208, 3
08 well potential separation regions, 108a, 208a, 30
8a bottom well, 108b, 208b, 308b well wall, 109, 209 power supply line (third wiring layer), 2
01 second logic circuit formation region, ST1 region designation step, ST2 cell arrangement designation step, ST3 wiring position designation step, ST41 bottom well pattern generation step, ST42 well wall pattern generation step.

Continued on front page (72) Inventor Takao Sato 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Norihide Narutomi 3-1-1-17 Chuo, Itami-shi, Hyogo Mitsubishi Electric Inside System LSI Design Inc.

Claims (19)

[Claims] A first integrated circuit formation region in which a second conductivity type MOS transistor is formed in a first conductivity type first well region to which a first substrate potential is applied;
Second integrated circuit formation region in which a second conductivity type MOS transistor is formed in a first conductivity type second well region to which a second substrate potential having a potential different from the substrate potential is applied. Region designating means for designating the first integrated circuit formation region and the second integrated circuit formation region with respect to the surface of a first conductivity type semiconductor substrate having: a first integrated circuit formation region of the semiconductor substrate Bottom well pattern generation means for generating a mask pattern for forming a second conductivity type bottom well located below the first well area over the entire area; Based on the information on the first integrated circuit formation region and the information on the bottom well in the mask pattern generated by the bottom well pattern generation means, the first integrated circuit formation region is formed. And a well wall pattern generating means for generating a mask pattern for forming a second conductivity type well wall reaching the bottom well from the surface of the semiconductor substrate, surrounding the first integrated circuit to be formed. Pattern data generation device. 2. A semiconductor integrated circuit comprising: a first integrated circuit forming region in which a first integrated circuit is formed; and a second integrated circuit forming region in which a second integrated circuit is formed, wherein the first integrated circuit has a logic. It is constituted by a plurality of cells designed in units of level, and the cells are of the first conductivity type to which the first substrate potential is applied.
Of the second integrated circuit is formed at least in part by the second conductivity type MOS transistor formed in the well region of the second integrated circuit, and a second substrate potential different from the first substrate potential is applied to the second integrated circuit. The first integrated circuit formation region is formed on the surface of the first conductivity type semiconductor substrate at least partially constituted by the second conductivity type MOS transistor formed in the first conductivity type second well region. And area designating means for designating the second integrated circuit formation area; and, for the first integrated circuit formation area, the plurality of cells of the plurality of cells based on logical information describing the operation of the first integrated circuit. A cell arrangement designating means for designating an arrangement; and arranging the first integrated circuit forming region based on logic information describing an operation of the first integrated circuit and cell information on the plurality of cells. Wiring position specifying means for specifying a position; and a mask pattern for forming a second conductivity type bottom well located under the first well region over the entire first integrated circuit formation region of the semiconductor substrate. Using the information of the first integrated circuit formation area specified by the area specifying means and the information of the bottom well in the mask pattern generated by the bottom well pattern generating means. To form a second conductivity type well wall that surrounds the first integrated circuit formed in the first integrated circuit formation region and that reaches the bottom well from the surface of the semiconductor substrate by performing an arithmetic operation. And a well wall pattern generating means for generating the mask pattern. 3. A mask pattern for bottom well formation generated by the bottom well pattern generation means is information on a first integrated circuit formation area specified by an area specification means and information on a design reference value of a wafer process. Is generated so that the planar shape of the bottom well becomes a shape that oversizes the design standard value with respect to the planar shape of the first integrated circuit formation region, and the well wall generated by the well wall pattern generating means A mask pattern for formation is formed on the well wall based on information on the bottom well mask pattern determined by the bottom well pattern generation means and information on the first integrated circuit formation area specified by the area specification means. The planar shape is such that the outer periphery of the first integrated circuit formation region is the inner periphery and the outer periphery of the bottom well is the outer periphery. Mask pattern data generating apparatus according to claim 1 or claim 2, wherein the done. 4. A mask pattern for forming a well wall generated by a well wall pattern generating means includes information on a first integrated circuit forming area and a second integrated circuit forming area specified by an area specifying means. 3. The mask pattern data generating device according to claim 1, wherein the mask pattern data is generated based on the data. 5. The first integrated circuit formation region includes a first well formed in a third well region of a second conductivity type to which a third substrate potential different from the first and second substrate potentials is applied. A conductivity type MOS transistor is further formed, and the well wall pattern generation means includes a space between the well wall and the third well region based on information on the well wall and information on the third well region in the mask pattern of the well wall. Comparing with a predetermined interval value, adding a correction well wall corresponding to the correction information obtained from the comparison check result to the well wall, and obtaining a mask pattern for forming a corrected well wall. 3. The mask pattern data generation device according to claim 1, wherein: 6. The well wall pattern generating means is disposed to face the surface of the well wall, and has a well region, a semiconductor substrate, and a PN.
Generate a mask pattern for forming a potential transmission line for transmitting a potential for applying a reverse bias to the junction,
3. The mask pattern data generation device according to claim 1, wherein an arrangement of a plurality of contact cells for making electrical connection between the potential transmission line and the surface of the well wall at a plurality of locations is designated. 7. A first integrated circuit formation region in which a second conductivity type MOS transistor is formed in a first conductivity type first well region to which a first substrate potential is applied, and the first integrated circuit formation region.
Second integrated circuit formation region in which a second conductivity type MOS transistor is formed in a first conductivity type second well region to which a second substrate potential having a potential different from the substrate potential is applied. Specifying a first integrated circuit formation region and a second integrated circuit formation region with respect to a surface of a first conductivity type semiconductor substrate having: a first integrated circuit formation region of the semiconductor substrate A bottom well pattern generating step of generating a mask pattern for forming a second conductive type bottom well located below the first well region over the entire region; The first integrated circuit is formed based on information on a first integrated circuit formation region and information on a bottom well in a mask pattern generated in the bottom well pattern generating step. Forming a mask pattern for forming a second conductivity type well wall surrounding the first integrated circuit formed in the formation region and reaching the bottom well from the surface of the semiconductor substrate; and A mask pattern data generation method comprising: 8. A semiconductor device having a first integrated circuit formation region on which a first integrated circuit is formed and a second integrated circuit formation region on which a second integrated circuit is formed, wherein the first integrated circuit has a logic function. The cell is constituted by a plurality of cells at the gate level, and the cell is at least partially constituted by a MOS transistor of a second conductivity type formed in a first well region of a first conductivity type to which a first substrate potential is applied. A second conductive type MOS transistor formed in a first conductive type second well region to which a second substrate potential having a potential different from the first substrate potential is applied; An area designating step of designating the first integrated circuit formation area and the second integrated circuit formation area with respect to a surface of a first conductivity type semiconductor substrate at least partially constituted by the first and second integrated circuit formation areas; Integrated circuit type A cell arrangement designating step of designating an arrangement of the plurality of cells based on logical information describing an operation of the first integrated circuit in the area; A wiring position specifying step of specifying a wiring position based on logic information describing an operation of the integrated circuit and cell information for the plurality of cells; A bottom well pattern generation step of generating a mask pattern for forming a second conductivity type bottom well located below one well region; and the first integrated circuit formation region specified in the region specification step Is calculated by using the information of the bottom well and the information of the bottom well in the mask pattern generated in the bottom well pattern generation step. And a well wall pattern for generating a mask pattern for forming a second conductivity type well wall that reaches the bottom well from the surface of the semiconductor substrate and surrounds the first integrated circuit formed in the integrated circuit formation region. And a generating step. 9. The mask pattern for bottom well formation generated in the bottom well generation step includes information on a first integrated circuit formation region specified in the region specification step and information on a design reference value of a wafer process. Based on the well wall pattern generated in the well wall pattern generation step, the bottom well is generated such that the planar shape of the bottom well is oversized with the design reference value with respect to the planar shape of the first integrated circuit formation region. Pattern for the well wall is formed based on the information of the mask pattern of the bottom well determined in the bottom well pattern generation step and the information of the first integrated circuit formation region specified in the region specifying step. Has a shape in which the outer periphery of the first integrated circuit formation region is the inner periphery and the outer periphery of the bottom well is the outer periphery. Claim 7 or claim 8 mask pattern data generation method according to characterized in that it is produced in the. 10. The mask pattern for forming a well wall generated by the well wall pattern generating step,
9. The mask pattern data generating method according to claim 7, wherein the mask pattern data generating method is generated based on information of the first integrated circuit forming area and the second integrated circuit forming area specified in the area specifying step. . 11. The first integrated circuit formation region includes a first well formed in a third well region of a second conductivity type to which a third substrate potential different from the first and second substrate potentials is applied. A conductivity type MOS transistor is further formed, and the well wall pattern generating step includes the step of generating a distance between the well wall and the third well region based on the information of the well wall and the information of the third well region in the mask pattern of the well wall. Comparing with a predetermined interval value, adding a correction well wall corresponding to the correction information obtained from the comparison check result to the well wall, and obtaining a mask pattern for forming a corrected well wall. 9. The method of generating mask pattern data according to claim 7, wherein: 12. A well wall pattern generating step for forming a potential transmission line for transmitting a potential for applying a reverse bias to a well region, a semiconductor substrate, and a PN junction, which is disposed opposite to a surface of the well wall. 9. The mask pattern according to claim 7, wherein a mask pattern is generated and an arrangement of a plurality of contact cells for electrically connecting the potential transmission line to the surface of the well wall at a plurality of locations is designated. Data generation method. 13. A first integrated circuit forming region in which a first integrated circuit is formed and a second integrated circuit forming region in which a second integrated circuit is formed.
A first conductivity type semiconductor substrate having an integrated circuit formation region on a surface thereof, a first conductivity type first well region formed in a first integrated circuit formation region of the semiconductor substrate, and a first well A second conductivity type MOS transistor formed in a region and constituting a part of the first integrated circuit; a first conductivity type second well formed in a second integrated circuit formation region of the semiconductor substrate A MOS transistor of a second conductivity type formed in the second well region and constituting a part of the second integrated circuit; and a MOS transistor of a first integrated circuit formation region of the semiconductor substrate. A bottom well of the second conductivity type located below the first well region and a first integrated circuit formed in the first integrated circuit formation region, and from the surface of the semiconductor substrate to the bottom well; Reaching the second conductivity type c A well potential separation region having a first wall region, and a first potential region provided on a surface of the semiconductor substrate and electrically connected to a surface of the first well region to transmit a first potential to the first well region. A first wiring layer that is provided on the surface of the semiconductor substrate and is electrically connected to a surface of the second well region to apply a second potential different from the first potential to the second wiring layer. A second wiring layer transmitting to the well region; a second wiring layer provided on a surface of the semiconductor substrate, electrically connected to a surface of the well potential separation region; and a PN junction between the well potential separation region and the semiconductor substrate. A semiconductor integrated circuit device having a third wiring layer for transmitting a third potential for applying a reverse bias to the well potential separation region. 14. The semiconductor device according to claim 1, wherein the third wiring layer has a connection wiring portion located on the surface of the well potential separation region and electrically connected at a plurality of locations on the surface of the well potential separation region. 14. The semiconductor integrated circuit device according to claim 13, wherein: 15. The connection wiring section in the third wiring layer,
Surrounding the first integrated circuit formed in the first integrated circuit formation region, and being electrically connected to the surface of the well potential separation region at a plurality of locations along the periphery of the first integrated circuit. 15. The semiconductor integrated circuit device according to claim 14, wherein: 16. The circuit according to claim 13, wherein the first integrated circuit is a logic circuit arranged and designed based on cells designed in units of logic levels, and the second integrated circuit is a memory circuit. Semiconductor integrated circuit device. 17. The circuit according to claim 13, wherein the first integrated circuit is a logic circuit arranged and designed based on a core managed as a design resource, and the second integrated circuit is a memory circuit. Semiconductor integrated circuit device. 18. A P-type semiconductor substrate having a logic circuit formation region on which a logic circuit is formed and a memory circuit formation region on which a memory circuit is formed, and a P-type semiconductor substrate formed in the logic circuit formation region of the semiconductor substrate. P
An N-type MOS transistor formed in the first well region and forming a part of the logic circuit; and an N-type MOS transistor formed in a logic circuit formation region of the semiconductor substrate.
A third type well region, a P-type MOS transistor formed in the third well region and constituting a part of the logic circuit, and a P-type MOS transistor formed in a memory circuit formation region of the semiconductor substrate. A second well region; an N-type MOS transistor formed in the second well region and forming a part of the memory circuit; and an N-type fourth transistor formed in a memory circuit formation region of the semiconductor substrate. A P-type MOS transistor formed in the fourth well region and constituting a part of the memory circuit; and the first and third P-type MOS transistors throughout the logic circuit formation region of the semiconductor substrate. An N-type bottom well located below the well region and a logic circuit formed in the logic circuit formation region, and reaching the bottom well from the surface of the semiconductor substrate. A well potential isolation region and an N-type well wall, the provided on the semiconductor substrate on the surface, are electrically connected by the surface of said first well region, the ground potential first
A first wiring layer for transmitting to the well region of the semiconductor substrate; a first wiring layer provided on the surface of the semiconductor substrate;
A second wiring layer for transmitting to the well region of the semiconductor substrate; a second wiring layer provided on the surface of the semiconductor substrate; electrically connected to a surface of the third well region;
A third wiring layer for transmitting to a well region of the semiconductor substrate; a third wiring layer provided on a surface of the semiconductor substrate; electrically connected to a surface of the fourth well region;
A fourth wiring layer that transmits to the well region of the semiconductor substrate; and a fourth wiring layer that is provided on the surface of the semiconductor substrate and is electrically connected to the surface of the well potential separation region to transmit a positive potential to the well potential separation region. A semiconductor integrated circuit device comprising: a fifth wiring layer. 19. A layout design based on a first logic circuit formation area in which a first logic circuit layout-designed based on cells designed in units of logic levels is formed, and a core managed as a design resource P-type semiconductor substrate having on its surface a second logic circuit formation region to be formed and a memory circuit formation region on which a memory circuit is to be formed; and a P-type semiconductor substrate formed in the first logic circuit formation region of the semiconductor substrate. A first well region, an N-type MOS transistor formed in the first well region and constituting a part of the first logic circuit, and a first well region formed in the first logic circuit formation region of the semiconductor substrate. An N-type third well region to be formed; a P-type MOS transistor formed in the third well region and constituting a part of the first logic circuit; A P-type second well region formed in the circuit formation region; an N-type MOS transistor formed in the second well region and forming a part of the memory circuit; An N-type fourth well region formed in the region, a P-type MOS transistor formed in the fourth well region and constituting a part of the memory circuit, and a second logic circuit of the semiconductor substrate A fifth P-type well region formed in the formation region; an N-type MOS transistor formed in the fifth well region and forming a part of the second logic circuit; An N-type sixth well region formed in the second logic circuit formation region; a P-type MOS transistor formed in the sixth well region and forming a part of the second logic circuit; N located below the first and third well regions over the entire first logic circuit formation region of the semiconductor substrate.
N-type first bottom well surrounding the first bottom well of the mold and the first logic circuit formed in the first logic circuit formation region, and reaching the first bottom well from the surface of the semiconductor substrate. A first well potential isolation region having a well wall of N, and N located below the fifth and sixth well regions over the entire second logic circuit formation region of the semiconductor substrate.
An N-type second bottom well surrounding the second logic circuit formed in the second logic circuit formation region and reaching the second bottom well from the surface of the semiconductor substrate. A second well potential separation region having a well wall; a second well potential separation region provided on a surface of the semiconductor substrate, electrically connected to a surface of the first well region;
A first wiring layer for transmitting to the well region of the semiconductor substrate; a first wiring layer provided on the surface of the semiconductor substrate;
A second wiring layer for transmitting to the well region of the semiconductor substrate; a second wiring layer provided on the surface of the semiconductor substrate; electrically connected to a surface of the third well region;
A third wiring layer for transmitting to a well region of the semiconductor substrate; a third wiring layer provided on a surface of the semiconductor substrate; electrically connected to a surface of the fourth well region;
A fourth wiring layer for transmitting to the well region of the semiconductor substrate; and a fourth wiring layer provided on the surface of the semiconductor substrate, electrically connected to the surface of the fifth well region, and
A fifth wiring layer for transmitting to a well region of the semiconductor substrate; a fifth wiring layer provided on a surface of the semiconductor substrate; electrically connected to a surface of the sixth well region;
A sixth wiring layer for transmitting to the well region of the first well, provided on the surface of the semiconductor substrate, electrically connected to the surface of the first well potential separation region, and providing a positive potential to the first well. A seventh wiring layer for transmitting a potential to the potential separation region; a seventh wiring layer provided on the surface of the semiconductor substrate and electrically connected to a surface of the second well potential separation region to supply a positive potential to the second well; A semiconductor integrated circuit device comprising: an eighth wiring layer transmitting the potential to the potential separation region.