JP4800257B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device technology, and particularly to a technology effective when applied to a semiconductor integrated circuit device technology having a CMIS (Complimentary Metal Insulator Semiconductor) circuit.

  In recent years, various studies have been made on semiconductor integrated circuit devices in order to achieve high integration, high speed, low power consumption, and the like. In particular, in a semiconductor integrated circuit device having a MOS / FET (Metal Oxide Semiconductor Field Effect Transistor), it is necessary to miniaturize elements and wirings in order to improve element integration and operation speed, and the scaling of element dimensions is rapid. It is advanced to.

  By the way, the present inventor examined scaling in a semiconductor integrated circuit device. The following is a technique studied by the present inventor, and its outline is as follows.

  That is, there are two types of scaling of a semiconductor integrated circuit device such as an LSI (Large Scale Integrated Circuit), scaling with constant voltage and scaling with constant electric field.

  In a CMOS type semiconductor integrated circuit device having a CMOS-FET as a constituent element, scaling with a constant electric field is performed mainly from the viewpoint of ensuring the reliability of a gate oxide film. In this case, it is necessary to reduce the power supply voltage in proportion to the reduction of the element size from the viewpoint of ensuring the stability of the element characteristics.

  References relating to the manufacturing technology of a CMOS type semiconductor integrated circuit device include, for example, December 15, 1990, W. Mari published by Keigaku Publishing Co., Ltd., “Illustration Ultra LSI Engineering” p167-p191 (Non-patent Document 1). There is what is described in the reference).

  By the way, in order to truly establish the scaling law in the above-described CMOS type semiconductor integrated circuit device, it is necessary to reduce the threshold voltage in proportion to the element size. This is because the voltage component contributing to the circuit operation can be expressed by the equation (power supply voltage−threshold voltage).

  However, a decrease in threshold voltage leads to an increase in leakage current, so that a leakage current test (Iddq test) widely used in semiconductor integrated circuit device testing is not possible and the leakage current is reduced during an aging test. As the temperature rises due to the increase in temperature, the temperature increases so much that it causes thermal runaway.

  FIG. 29 shows the mechanism of thermal runaway during the aging test. In FIG. 29, the horizontal axis represents the set junction temperature (junction temperature Tj1) of the semiconductor integrated circuit device, and the vertical axis represents the temperature rise caused by the total leakage current of the semiconductor integrated circuit device generated by the junction temperature Tj1 added to the ambient temperature. It is temperature (joining temperature Tj2). Usually, the junction temperature Tj2 and the junction temperature Tj1 are stabilized at the same temperature. However, when the leakage current component increases, the temperature rise accompanying the leakage current becomes extremely large, leading to thermal runaway.

  In order to solve such a problem, a method of controlling the threshold voltage by applying a back bias to the well of the MOS • FET can be considered.

  However, in this method, a forward voltage is applied between the well and the source / drain due to noise during actual use (normal operation), and the well potential may fluctuate. Problems such as causing it may occur.

  A technique for reducing the leakage current using such a back bias is described in, for example, Japanese Patent Laid-Open No. 6-334010 (see Patent Document 1). A configuration is disclosed in which a substrate node of a threshold voltage field effect transistor is connected to a power supply line, and a pseudo power supply line connected to a logic circuit group is connected to the power supply line via a high threshold voltage field effect transistor. ing. In the case of this technology, during the normal operation of the semiconductor integrated circuit device, the field effect transistor having the substrate node connected to the power supply line is operated normally with a low threshold voltage by turning on the field effect transistor having a high threshold voltage. On the other hand, during the test period, by turning off the high threshold voltage field effect transistor and applying the test voltage to the pseudo power supply line, the low threshold voltage field effect The transistor can temporarily have a high threshold voltage.

Further, as a technique for controlling the threshold voltage of the MOS • FET, for example, Japanese Patent Laid-Open No. 8-17183 (see Patent Document 2) has a technology of providing a switch means for making the substrate potential of the MOS • FET variable. . In the case of this technique, the switching means switches the back gate bias potential of the MOS • FET to the first potential or the second potential, and switches the absolute value of the threshold voltage of the MOS • FET. The threshold current characteristic can be switched.
JP-A-6-334010 JP-A-8-17183 December 15th, 1990, W. Mari, published by Keigaku Publishing Co., Ltd. “Illustrated VLSI Engineering” p167-p191

  However, in the technique as described in Patent Document 1, since a field effect transistor having a high threshold voltage is interposed in series between a logic circuit group and a power supply, the impedance of the circuit increases. As a result, the semiconductor integrated circuit device There is a problem that the overall operation speed of the system is reduced.

  Further, in the technique as described in Patent Document 2, the source and n well of the p-channel type MOS • FET are short-circuited via the n-channel type MOS • FET switch. It is necessary to generate a higher voltage. (2) Since the high voltage of (1) above is applied to the MOS / FET, the gate oxide film of the MOS / FET must be thickened, and the device characteristics deteriorate. There is a problem.

  An object of the present invention is to provide a high-performance CMOS semiconductor integrated circuit device capable of preventing latch-up and a manufacturing technique thereof.

  Another object of the present invention is to provide a technique capable of preventing latch-up during normal operation and suppressing leakage current during testing in a CMOS type semiconductor integrated circuit device. .

  Another object of the present invention is to provide a technology capable of improving the reliability during normal operation and testing without causing a decrease in operation speed during normal operation in a CMOS type semiconductor integrated circuit device. There is to do.

  Another object of the present invention is to provide a technique capable of improving the reliability at the normal time and at the time of testing without causing deterioration of element characteristics in a CMOS type semiconductor integrated circuit device.

  Another object of the present invention is to provide a technique capable of improving the layout efficiency of a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the semiconductor integrated circuit device of the present invention is independent of the first power supply voltage line connected to the CMOSFET and the second power supply voltage line to which a voltage smaller than the first power supply voltage line is applied. 3 power supply voltage lines and a fourth power supply voltage line. The third power supply voltage line can supply power to the first conductivity type well as needed, and the fourth power supply voltage line is necessary for the second conductivity type well. The power can be supplied according to the condition.

  In the semiconductor integrated circuit device of the present invention, a first switch transistor made of a MOSFET is connected between the first power supply voltage line and the third power supply voltage line. A second switch transistor made of a MOSFET is connected between the fourth power supply voltage line, and the first power supply voltage line and the third switch transistor are operated as necessary by operating the first switch transistor. The power supply voltage line can be short-circuited, and the second power supply voltage line and the fourth power supply voltage line can be short-circuited by operating the second switch transistor as necessary.

  Thus, for example, during normal operation of the semiconductor integrated circuit device, the first switch transistor and the second switch transistor are turned on, and the first power supply voltage is applied to the first conductivity type well and the second conductivity type well, respectively. Further, by supplying the second power supply voltage, fluctuations in the substrate potential of the first conductivity type MOS • FET and the second conductivity type MOS • FET can be suppressed, so that latch-up caused by the variation can be prevented. Is possible.

  For example, when testing a semiconductor integrated circuit device, the first switch transistor and the second switch transistor are turned off, and a voltage suitable for the test is applied from the third power supply voltage line and the fourth power supply voltage line. By supplying the first conductivity type well and the second conductivity type well, respectively, the leakage current can be reduced, so that thermal runaway caused by the leakage current can be suppressed.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit device, comprising: forming a first conductivity type well and a second conductivity type well on a surface of a semiconductor substrate;
Forming a second conductive MOSFET constituting a CMOSFET in the first conductive well and a first switching transistor comprising a MOSFET different from the second conductive MOSFET;
Forming a first conductivity type MOSFET constituting a CMOSFET in the second conductivity type well and a second switching transistor comprising a MOSFET different from the first conductivity type MOSFET;
Forming a first power supply voltage line so as to be connected to a source of the second conductivity type MOSFET constituting the CMOSFET;
Forming a second power supply voltage line so as to be connected to the source of the first conductivity type MOSFET constituting the CMOSFET;
Forming a well feed line so as to connect to the drain of the first switch transistor and the first conductivity type well;
Forming a well feed line so as to be connected to the drain of the second switch transistor and the second conductivity type well;
Forming a control signal line to connect to the gate electrode of the first switch transistor;
Forming a control signal line so as to be connected to the gate electrode of the second switch transistor,
The source of the first switch transistor is disposed adjacent to the source of the second conductivity type MOSFET and is the same semiconductor region, and the source of the second switch transistor is the first conductivity type. The MOSFET is disposed adjacent to the source and is formed as the same semiconductor region.

  As a result, the area occupied by the first switch transistor and the second switch transistor can be reduced, and the layout efficiency can be improved.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit device, comprising: forming a first conductivity type well and a second conductivity type well on a surface of a semiconductor substrate;
Forming a second conductive MOSFET constituting a CMOSFET in the first conductive well and a first switching transistor comprising a MOSFET different from the second conductive MOSFET;
Forming a first conductivity type MOSFET constituting a CMOSFET in the second conductivity type well and a second switching transistor comprising a MOSFET different from the first conductivity type MOSFET;
Forming a first power supply voltage line so as to be connected to a source of the second conductivity type MOSFET constituting the CMOSFET;
Forming a second power supply voltage line so as to be connected to the source of the first conductivity type MOSFET constituting the CMOSFET;
Forming a well feed line so as to connect to the drain of the first switch transistor and the first conductivity type well;
Forming a well feed line so as to be connected to the drain of the second switch transistor and the second conductivity type well;
Forming a control signal line to connect to the gate electrode of the first switch transistor;
Forming a control signal line so as to be connected to the gate electrode of the second switch transistor,
Forming the well feed line so as to be connected to the drain of the first switch transistor and the first conductivity type well; and connecting to the drain of the second switch transistor and the second conductivity type well The step of forming the well power supply line is performed in the same process as
The step of forming the control signal line so as to be connected to the gate electrode of the first switch transistor and the step of forming the control signal line so as to be connected to the gate electrode of the second switch transistor It is performed by the same process.

  Thus, the first switch transistor, its well feed line and its control signal line, and the second switch transistor, its well feed line and its control signal line are formed in the same process, thereby producing A semiconductor integrated circuit device having a first switch transistor, a second switch transistor, a well power supply line, and a control signal line can be manufactured without causing a significant increase in the number of steps.

  In the semiconductor integrated circuit device of the present invention, the first switching transistor and the second switching transistor are provided in a ratio of one set to a plurality of logic gates. As a result, the total area occupied by the switching transistor can be reduced as compared with the case where the first switching transistor and the second switching transistor are provided for each logic gate. It is possible to suppress an increase in chip size and a reduction in element integration due to the above.

  Further, in the semiconductor integrated circuit device of the present invention, the third power supply voltage line and the fourth power supply voltage line are configured by conductor wiring, and for each cell region for disposing each of the plurality of logic gates, A connection portion for connecting the conductor wiring for the third power supply voltage line and the second conductivity type well is provided, and connecting the conductor wiring for the fourth power supply voltage and the first conductivity type well. A connection portion is provided.

  As a result, the well power supply voltage can be supplied from the vicinity of each logic gate, so that a stable potential can be supplied to each logic gate.

  In the semiconductor integrated circuit device of the present invention, the control signal in one control signal line is divided into two control signals having different potentials before the input of the first switch transistor and the second switch transistor. In addition, a switch control unit is provided for transmitting the control signals to the inputs of the first switch transistor and the second switch transistor, respectively. This makes it possible to use a single control signal line for controlling on / off of the switching transistor.

  In the semiconductor integrated circuit device of the present invention, the first switch transistor and the second switch transistor are provided in a vacant region where a power supply voltage line is disposed.

  As a result, the main surface of the semiconductor chip can be used effectively by providing the switching transistor in the arrangement area of the power supply voltage line, which is originally an empty area. It is possible to suppress an increase in area as compared with the case where a transistor is provided.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, since the area occupied by the first switch transistor and the second switch transistor can be reduced, the layout efficiency can be improved.

  In order to describe the present invention in more detail, it will be described with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  The CMOS type semiconductor integrated circuit device of the present embodiment will be specifically described with reference to FIGS.

  1 to 3 show regions of an inverter circuit when the logic gate in the CMOS type semiconductor integrated circuit device of the present embodiment is an inverter.

  Further, in this specification, symbols such as Vdd are used both for indicating a voltage that is a general display and for indicating a wiring to which the voltage is applied. In the figure, circles indicate electrodes such as pins provided at the ends of each wiring, and the squares with cross hatching are contact regions connecting different wiring layers. The region of the through-hole conductive layer embedded in the through-hole is shown.

  In addition, the schematic cross-sectional view showing the CMOS type semiconductor integrated circuit device of the present embodiment shown in FIG. 1 is shown in the CMOS type semiconductor integrated circuit of the present embodiment shown in FIG. In the schematic layout diagram showing the circuit device, various cross-sectional areas are connected.

  In the CMOS type semiconductor integrated circuit device of this embodiment, an n-type well 2 and a p-type well 3 are formed on a p-type semiconductor substrate 1.

  A field insulating film 4 is formed on the surface of the p-type semiconductor substrate 1 in the boundary region between the n-type well 2 and the p-type well 3.

  The n-type well 2 is provided with a p-channel MOS • FET transistor Tp which is a component of the inverter circuit and a p-channel MOS • FET which is a switching transistor Tps which is a feature of the present embodiment. The source 5 of the transistor for transistor Tps and the source 5 of the transistor for transistor Tp for the inverter circuit are arranged adjacent to each other to form the same p-type semiconductor region.

  Further, the p-type well 3 is provided with an n-channel MOS • FET transistor Tn which is a component of the inverter circuit and an n-channel MOS • FET which is a switching transistor Tns which is a feature of the present embodiment. The source 10 of the switching transistor Tns and the source 10 of the inverter circuit transistor Tn are arranged adjacent to each other and form the same n-type semiconductor region.

  Further, in the n-type well 2, the source 5 and the drain 6, which are high-concentration p-type semiconductor regions of the transistor Tp of the p-channel MOS • FET constituting the CMOS • FET, and the high-concentration p-type semiconductor region of the switching transistor Tps. A p-type semiconductor region 9 having a lower concentration than that of the source 5 and the drain 7 is formed, and a MOS • FET having an LDD (Lightly Doped Drain Structure) structure is formed.

  Further, in the p-type well 3, a source 10 and a drain 11 which are high-concentration n-type semiconductor regions of an n-channel MOS-FET transistor Tn constituting a CMOS-FET, and a high-concentration n-type semiconductor region of a switching transistor Tns. An n-type semiconductor region 14 having a lower concentration than that of the source 10 and the drain 12 is formed, thereby forming a MOS • FET having an LDD structure.

  In addition, a gate insulating film is formed below the gate electrode G in the various MOS • FETs described above, and a sidewall insulating film is formed on the side wall of the gate electrode G.

  The source 5 of the transistor Tp is connected to a first power supply voltage line Vdd to which a power supply voltage Vdd of about 5 V, for example, is applied, and the gate electrode G is connected to an input line IN. The drain 6 is connected to an output line OUT.

  For example, a power supply voltage Vss of 0 V (ground voltage) is applied to the source 10 of the transistor Tn (a second power supply voltage line (source line) Vss in a potential state lower than the first power supply voltage line). The gate electrode G is connected to the input line IN, and the drain 11 is connected to the output line OUT.

  A control signal line Cwl to which a control signal Cwl is applied is connected to the gate electrode G in order to control the switching transistor Tps.

  The n-type well 2 is connected to a well-feeding line Vwl to which a well-feeding voltage Vwl is applied via an n-type semiconductor region 13, and the well-feeding line Vwl is connected to the switching transistor Tps. Connected to the drain 7.

  On the other hand, a control signal line Csu to which a control signal Csu is applied is connected to the gate electrode G in order to control the switching transistor Tns.

  The p-type well 3 is connected to a well power supply line Vsu to which a well power supply voltage Vsu is applied via a p-type semiconductor region 8, and the well power supply line Vsu is connected to the switching transistor Tns. Connected to the drain 12. In this case, since the p-type well 3 and the p-type semiconductor substrate 1 have the same conductivity type, the well power supply line Vsu is in the form of a substrate power supply line of the p-type semiconductor substrate 1.

  In the above-described CMOS type semiconductor integrated circuit device according to the present embodiment, a switching transistor Tps is newly provided in the n-type well 2 and a switching transistor Tns is newly provided in the p-type well 3.

  Further, in order to control the switching transistor Tps, a control signal line Cwl is newly connected to the gate electrode G, and a well feed line Vwl is newly connected to the drain 7 thereof.

  A control signal line Csu is newly connected to the gate electrode G for controlling the switching transistor Tns, and a well power supply line Vsu is newly connected to the drain 12 thereof.

  Therefore, in order to control the threshold voltage ΔVthp of the p-channel MOS • FET in the n-type well 2 and the threshold voltage ΔVthn of the n-channel MOS • FET in the p-type well 3, the well power supply This can be done by adjusting the line Vwl and the well feed line Vsu.

  That is, the change ΔVthp in the threshold voltage of the p-channel MOS • FET in the n-type well 2 is expressed by the equation: ΔVthp = KBP {(Vwl−Vdd + 2ΦF) 1 / 2− (2ΦF) 1/2} It can be controlled by adjusting the power supply line Vwl.

  Further, the threshold voltage ΔVthn of the n-channel MOS • FET in the p-type well 3 is obtained from the equation: ΔVthn = KBN {(Vss−Vsu + 2ΦF) 1 / 2− (2ΦF) 1/2} It can be controlled by adjusting Vsu.

  In the above equation, KBP is the substrate effect constant of the p-channel MOS • FET, KBN is the substrate effect constant of the n-channel MOS • FET, and ΦF represents the built-in potential of the semiconductor.

  Here, FIG. 4 shows voltages applied to the well feed lines Vwl and Vsu and the control signal lines Cwl and Csu during a test such as an aging test of the semiconductor integrated circuit device according to the present embodiment and during a normal operation. In FIG. 4, VBB represents a positive predetermined reference voltage.

  First, in the aging test, Vwl (Vdd + ΔVBB) and Vsu (Vss−ΔVBB) are applied to the control signal lines Cwl and Csu, respectively, to turn off the switching transistors Tps and Tns. Then, Vdd + ΔVBB and Vss−ΔVBB are respectively applied to the well power supply lines Vwl and Vsu from the outside. As a result, the problem of leakage current during the aging test can be avoided, and the problem of thermal runaway caused by the leakage current can also be avoided.

  On the other hand, during normal operation, the switching transistors Tps and Tns are turned on by applying power supply voltages Vdd and Vss to the control signal lines Cwl and Csu, respectively. As a result, the power supply voltage lines Vdd and Vss and the well feed lines Vwl and Vsu are electrically connected to set the substrate potentials of the transistors Tp and Tn to the power supply voltages Vdd and Vss, respectively. As a result, fluctuations in the substrate potential of the transistors Tp and Tn can be suppressed, so that latch-up caused by fluctuations in the substrate potential can be prevented, and the operation reliability of the semiconductor integrated circuit device can be ensured. It has become.

  As described above, in the CMOS type semiconductor integrated circuit device according to the present embodiment, the switching transistors Tps and p formed in the n-type well 2 at the time of the leak current test and the aging test widely performed in the LSI test. The control signal line Cwl for controlling the switch transistor Tps and the first power supply voltage Vdd are made equal to bring the switch transistor Tns formed in the mold well 3 into an off state, that is, a non-connected state. The control signal line Csu for controlling the switch transistor Tns is set equal to the second power supply voltage Vss.

  Therefore, according to the CMOS type semiconductor integrated circuit device of the present embodiment, the switch transistor Tps formed in the n-type well 2 and the switch formed in the p-type well 3 during the leakage current test and the aging test. Since the transistor Tns is in the off state, that is, the non-connected state, the test can be performed in a normal state in which the latch-up is prevented and the leakage current is suppressed.

  In addition, according to the CMOS type semiconductor integrated circuit device of the present embodiment, the switching transistor Tps formed in the n-type well 2 is not in a normal operation but in a leak current test or an aging test. In addition, when the switching transistor Tns formed in the p-type well 3 is turned on, that is, connected, normal operation can be performed in a state in which latch-up or the like is prevented.

  Furthermore, according to the CMOS type semiconductor integrated circuit device of the present embodiment, a back bias can be applied to the n-type well 2 and the p-type well 3 as necessary, thereby reducing the threshold voltage of the MOS • FET. Since it can be controlled and the occurrence of latch-up can be prevented, a high-performance and highly reliable semiconductor integrated circuit device can be obtained.

  Further, according to the CMOS type semiconductor integrated circuit device of the present embodiment, the first power supply voltage in which the power supply voltage Vdd, which is a power supply system necessary for circuit operation, is applied to the n-type well 2 and the p-type well 3. The control signal line Vwl, the well power supply line Vwl, the control signal line Csu, and the well power supply line Vsu, which are independent power systems of the line Vdd and the second power supply voltage line Vss to which the power supply voltage Vss is applied, are provided. As a result, it is possible to control the threshold voltage of the MOS • FET and to connect a power supply system necessary for circuit operation and an independent power supply system via the switch transistor Tps and the switch transistor Tns as necessary. Can be short-circuited.

  As described above, according to the CMOS type semiconductor integrated circuit device of this embodiment, latch-up and the like can be prevented during a leak current test, an aging test, and a normal operation, so that it has high performance and high reliability. The semiconductor integrated circuit device can be obtained.

  The state of the aging test described above is schematically shown in FIG. The CMOS type semiconductor integrated circuit device SI is loaded in the aging furnace A in a state where one or a plurality of the CMOS type semiconductor integrated circuit devices SI are mounted on the aging wiring board LB.

  The power supply unit PWU is a component for supplying power supply voltages Vdd and Vss, well power supply voltages Vwl and Vsu, and well power supply control signals Cwl and Csu to the semiconductor integrated circuit device SI.

  The pattern generator PG generates a pulse signal and supplies the pulse signal to the semiconductor integrated circuit device SI as necessary, thereby performing a test with the internal circuit of the semiconductor integrated circuit device SI activated. It is a component for.

  In the aging test, the temperature in the aging furnace A in which the semiconductor integrated circuit device SI is accommodated is set to a predetermined temperature, and the state is maintained for a certain period of time, thereby screening the initial failure of the semiconductor integrated circuit device SI. Is supposed to do.

  Next, a manufacturing technique of the CMOS type semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS. 6 to 9 are schematic cross-sectional views showing manufacturing steps of the CMOS type semiconductor integrated circuit device of the present embodiment.

  First, as shown in FIG. 6, after preparing a p-type semiconductor substrate 1 and forming the n-type well 2 and the p-type well 3 on the surface of the p-type semiconductor substrate 1 by ion implantation using the prior art. Then, a field insulating film 4 made of, for example, a silicon oxide film is formed in a selective region on the surface.

  Next, as shown in FIG. 7, a p-channel MOS • FET transistor Tp constituting a CMOS • FET in the n-type well 2 and a p-channel MOS • FET serving as a switching transistor Tps, which is a feature of the present embodiment, Are formed by the same process.

  Further, an n-channel MOS • FET transistor Tn constituting a CMOS • FET and an n-channel MOS • FET serving as a switching transistor Tns, which is a feature of the present embodiment, are formed in the p-type well 3 in the same process.

  In this case, a gate insulating film is formed below the gate electrode G in the various MOS • FETs described above, and a sidewall insulating film is formed on the side wall of the gate electrode G.

  Further, the source 5 and the drain 6 which are high-concentration p-type semiconductor regions of the transistor Tp of the p-channel MOS • FET constituting the CMOS • FET are formed in the n-type well 2 by the same process as the process of forming by ion implantation. A p-type semiconductor region 8 is simultaneously formed in the source 5 and drain 7 and n-type well 3 of the transistor Tps.

  Further, the source 5 of the transistor Tp and the source 5 of the switching transistor Tps are arranged adjacent to each other and are formed as the same high-concentration p-type semiconductor region.

  Further, a p-type semiconductor region 9 having a lower concentration than that is formed in the above-described high-concentration p-type semiconductor region, which is formed as a MOS • FET having an LDD (Ligthly Doped Drain Structure) structure.

  On the other hand, in the p-type well 3, the source 10 and the drain 11 which are high-concentration n-type semiconductor regions of the n-channel MOS.FET transistor Tn constituting the CMOS.FET are formed by the same process as the ion implantation method. An n-type semiconductor region 13 is simultaneously formed in the source 11 and drain 12 of the transistor Tns and the p-type well 2.

  The source 10 of the transistor Tn and the source 10 of the switching transistor Tns are arranged adjacent to each other and are formed as the same high-concentration n-type semiconductor region.

  The n-type semiconductor region 14 having a lower concentration is formed in the above-described high-concentration n-type semiconductor region, and is formed as an LDD structure MOS FET.

  Next, as shown in FIG. 8, for example, a silicon oxide film is deposited on the p-type semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method to form an insulating film 15.

  Subsequently, a through hole is formed in a selective region of the insulating film 15 by using a photolithography technique and a selective etching technique.

  Thereafter, for example, an aluminum film is deposited on the p-type semiconductor substrate 1 by a sputtering method to form the wiring layer 16.

  Next, a patterned wiring layer 16 is formed by removing a selective region of the wiring layer 16 using a photolithography technique and a selective etching technique.

  Subsequently, as shown in FIG. 9, for example, a silicon oxide film is deposited on the p-type semiconductor substrate 1 by a CVD method to form an insulating film 17.

  Thereafter, a through hole is formed in a selective region of the insulating film 17 by using a photolithography technique and a selective etching technique.

  Next, for example, an aluminum film is deposited on the p-type semiconductor substrate 1 by a sputtering method to form a wiring layer 18.

  Subsequently, a patterned wiring layer 18 is formed by removing a selective region of the wiring layer 18 by using a photolithography technique and a selective etching technique.

  In this case, the wiring layer 16 and the wiring layer 18 form the first power supply voltage line Vdd, the second power supply voltage line Vss, the input line IN, and the output line OUT in the CMOS FET in the same process.

  Further, the control signal line Cwl for controlling the switching transistor Tps, the well power supply line Vwl connected to the drain of the switching transistor Tps and the n-type well 2 by the wiring layer 16 and the wiring layer 18, and the switching A control signal line Csu for controlling the transistor Tns and a well power supply line Vsu connected to the drain of the switching transistor Tns and the p-type well 3 are formed by the same process.

  Thereafter, a multilayer wiring layer is formed on the p-type semiconductor substrate 1 by using a multilayer wiring technique, and then a surface protection film is formed (not shown), whereby the manufacturing process of the CMOS type semiconductor integrated circuit device is completed. finish.

  The manufacturing process described above is an embodiment using the p-type semiconductor substrate 1, but using a n-type semiconductor substrate having a conductivity type opposite to that of the p-type semiconductor substrate 1, a well having a conductivity type opposite to that described above using the n-type semiconductor substrate. It can be set as the aspect which forms semiconductor regions, such as.

  In the above-described manufacturing technique of the CMOS type semiconductor integrated circuit device of the present embodiment, the p-channel MOS • FET transistor Tp constituting the CMOS • FET in the n-type well 2 and the switch transistor which is a feature of the present embodiment A p-channel MOS • FET of Tps is formed by the same process.

  In addition, an n-channel MOS • FET transistor Tn constituting a CMOS • FET and an n-channel MOS • FET serving as a switching transistor Tns, which is a feature of the present embodiment, are formed in the p-type well 3 in the same process. .

  Also, the wiring layer 16 and the wiring layer 18 form the first power supply voltage line Vdd, the second power supply voltage line Vss, the input line IN, and the output line OUT in the CMOS FET in the same process.

  Further, the control signal line Cwl for controlling the switching transistor Tps, the well power supply line Vwl connected to the drain of the switching transistor Tps and the n-type well 2 by the wiring layer 16 and the wiring layer 18, and the switching A control signal line Csu for controlling the transistor Tns and a well power supply line Vsu connected to the drain of the switching transistor Tns and the p-type well 3 are formed by the same process.

  Therefore, according to the manufacturing technology of the CMOS type semiconductor integrated circuit device of the present embodiment, the switching transistor Tps and the switching transistor Tns are connected to the control signal line CWl, the well power supply line Vwl, and the control signal line Csu. The well power supply line Vsu can be formed by the same process as the process of forming the CMOS FET and the first power supply voltage line Vdd, the second power supply voltage line Vss, the input line IN, and the output line OUT connected to the CMOS FET. They can be easily formed at the same time without adding a manufacturing process.

  In the above-described manufacturing technique of the CMOS type semiconductor integrated circuit device of the present embodiment, the source 5 of the transistor Tp and the source 5 of the switching transistor Tps are arranged adjacent to each other and have the same high concentration p-type. It is formed as a semiconductor region.

  The source 10 of the transistor Tn and the source 10 of the switching transistor Tns are arranged adjacent to each other and are formed as the same high-concentration n-type semiconductor region.

  Therefore, according to the above-described manufacturing technology of the CMOS type semiconductor integrated circuit device of the present embodiment, the switching transistor Tps and the switching transistor Tns can be formed in the region of the minimum area, thereby improving the layout efficiency. it can.

  Next, another embodiment of the present invention will be described with reference to FIGS. 10 to 17 are a schematic layout diagram showing a variation of the logic gate of the CMOS type semiconductor integrated circuit device according to another embodiment of the present invention and a circuit diagram corresponding to each layout diagram. 10 to 17, one logic gate is shown, and the switching transistors Tps and Tns described above are provided for each logic gate.

  FIG. 10 is a schematic layout diagram showing a CMOS type semiconductor integrated circuit device having a two-input NAND gate circuit NA1, and FIG. 11 is a circuit diagram thereof.

  In this 2-input NAND gate circuit NA1, two transistors Tp1 and Tp2 connected in parallel with each other and two transistors Tn1 and Tn2 connected in series with each other are electrically connected between power supply voltage lines Vdd and Vss. Connected and configured. The transistors Tp1 and Tp2 are made of p-channel MOS • FETs and are formed in the n-type well 2. The transistors Tn1 and Tn2 are made of n-channel MOS • FETs and are formed in the p-type well 3.

  The gate electrodes of the transistors Tp1 and Tn1 are electrically connected and further electrically connected to the input line IN1. The gate electrodes of the transistors Tp2 and Tn2 are electrically connected and further electrically connected to the input line IN2. The sources of the transistors Tp1 and Tp2 and the drain of the transistor Tn2 are electrically connected, and are further electrically connected to the output line OUT.

  FIG. 12 is a schematic layout diagram showing a CMOS type semiconductor integrated circuit device having a three-input NAND gate circuit NA2, and FIG. 13 is a circuit diagram thereof.

  The three-input NAND gate circuit NA2 includes three transistors Tp1, Tp2, Tp3 connected in parallel to each other and three transistors Tn1, Tn2, Tn3 connected in series with each other between power supply voltage lines Vdd, Vss. It is configured to be electrically connected. The transistors Tp1, Tp2, Tp3 are made of p-channel MOS • FETs and are formed in the n-type well 2. The transistors Tn1, Tn2, and Tn3 are made of n-channel MOS • FETs and are formed in the p-type well 3.

  The gate electrodes of the transistors Tp1 and Tn1 are electrically connected and further electrically connected to the input line IN1. The gate electrodes of the transistors Tp2 and Tn2 are electrically connected and further electrically connected to the input line IN2. The gate electrodes of the transistors Tp3 and Tn3 are electrically connected and further electrically connected to the input line IN3. The sources of the transistors Tp1 to Tp3 and the drain of the transistor Tn3 are electrically connected and further electrically connected to the output line OUT.

  FIG. 14 is a schematic layout diagram showing a CMOS type semiconductor integrated circuit device having a two-input NOR gate circuit NO1, and FIG. 15 is a circuit diagram thereof.

  This 2-input NOR gate circuit NO1 has two transistors Tp1 and Tp2 and two transistors Tn1 and Tn2 in the n-type well 2 and the p-type well 3, respectively.

  In the 2-input NOR gate circuit NO1, two transistors Tp1, Tp2 connected in series with each other and two transistors Tn1, Tn2 connected in parallel with each other are electrically connected between power supply voltage lines Vdd, Vss. Has been configured. The transistors Tp1 and Tp2 are made of p-channel MOS • FETs and are formed in the n-type well 2. The transistors Tn1 and Tn2 are made of n-channel MOS • FETs and are formed in the p-type well 3.

  The gate electrodes of the transistors Tp1 and Tn1 are electrically connected and further electrically connected to the input line IN1. The gate electrodes of the transistors Tp2 and Tn2 are electrically connected and further electrically connected to the input line IN2. The source of the transistor Tp2 and the drains of the transistors Tn1 and Tn2 are electrically connected, and further electrically connected to the output line OUT.

  FIG. 16 is a schematic layout diagram showing a CMOS type semiconductor integrated circuit device having a three-input NOR gate circuit NO2, and FIG. 17 is a circuit diagram thereof.

  This three-input NOR gate circuit NO2 includes three transistors Tp1, Tp2, Tp3 connected in series with each other, and three transistors Tn1, Tn2, Tn3 connected in parallel with each other between power supply voltage lines Vdd, Vss. It is configured to be electrically connected to.

  The transistors Tp1, Tp2, Tp3 are made of p-channel MOS • FETs and are formed in the n-type well 2. The transistors Tn1, Tn2, and Tn3 are made of n-channel MOS • FETs and are formed in the p-type well 3.

  The gate electrodes of the transistors Tp1 and Tn1 are electrically connected and further electrically connected to the input line IN1. The gate electrodes of the transistors Tp2 and Tn2 are electrically connected and further electrically connected to the input line IN2. The gate electrodes of the transistors Tp3 and Tn3 are electrically connected and further electrically connected to the input line IN3. The source of the transistor Tp3 and the drains of the transistors Tn1, Tn2, and Tn3 are electrically connected and further electrically connected to the output line OUT.

  As shown in FIGS. 10 to 17, as in the CMOS type semiconductor integrated circuit device of the first embodiment, the n-type well 2 and the p-type well 3 have switching transistors Tps, The control signal lines Cwl and Csu for controlling the switching transistors Tps and Tns, the well power supply line Vwl connected to the n-type well 2 and the well power supply connected to the p-type well 3 are arranged. By providing the line Vsu, latch-up can be prevented particularly during the normal operation of the semiconductor integrated circuit device, and a semiconductor integrated circuit device with high performance and high reliability can be obtained. In addition, it is possible to suppress a leakage current when testing the semiconductor integrated circuit device, and to suppress thermal runaway caused by the leakage current, thereby improving the yield and reliability of the semiconductor integrated circuit device. It has become.

  Next, another embodiment of the present invention will be described with reference to FIG. FIG. 18 is a diagram schematically showing the arrangement of power supply voltage lines and control signal lines in the semiconductor chip SC in the CMOS type semiconductor integrated circuit device according to the present embodiment.

  As shown in FIG. 18, the wiring layout of the CMOS type semiconductor integrated circuit device of this embodiment can be applied to a mode in which the wirings are arranged in a matrix. Pins 19 are formed at the ends of the wirings, and the power supply voltage Vdd and the power supply voltage Vss necessary for circuit operation are input through the plurality of pins 19.

  The well power supply line Vwl and the well power supply line Vsu are input to an internal circuit in the semiconductor chip SC through one specific pin 19 in the semiconductor chip SC.

  The control signal line Cwl and the control signal line Csu are also input to an internal circuit in the semiconductor chip SC through one specific pin 19 in the semiconductor chip SC.

  According to the CMOS type semiconductor integrated circuit device of the present embodiment, in normal operation, the test signal line Cwl and the well power supply line Vwl are tested in order to equalize the power supply voltage Vdd or the power supply voltage Vss. A high resistor or the like can be connected in advance between the pins 19 to which they are input at times. Further, in order to make the potential of the control signal line Csu and the well power supply line Vsu equal to the power supply voltage Vdd or the power supply voltage Vss, a high resistor or the like is connected in advance between the pins 19 to which they are input during testing. can do. In this way, in normal operation, by removing the high resistor used during testing, etc., it is possible to operate in a normal state, that is, in a state where nothing is connected between the pins 19. Can do. That is, at the time of testing the semiconductor integrated circuit device, the above-described high resistance is removed, and a predetermined signal or power supply voltage is supplied from the outside to the control signal lines Cwl, Csu and the well power supply lines Vwl, Vsu through the pin 19. To. On the other hand, during the normal operation of the semiconductor integrated circuit device, the control signal lines Cwl and Csu and the well feeding lines Vwl and Vsu are electrically connected to the power supply voltage lines Vdd and Vss through high resistors, respectively. The control signal lines Cwl and Csu and the well feeding lines Vwl and Vsu are fixed to a predetermined potential. Thus, during normal operation of the semiconductor integrated circuit device, a desired signal or voltage in the semiconductor integrated circuit device can be obtained without supplying a predetermined signal or voltage from the outside to the control signal lines Cwl, Csu and the well power supply lines Vwl, Vsu. Circuit operation can be performed.

  Next, another embodiment of the present invention will be described with reference to FIG. FIG. 19 shows a plan view of the main part of the semiconductor chip SC.

  In the semiconductor chip SC, the n-type well 2 and the p-type well 3 are formed in a state extending along the horizontal direction of FIG. 19, that is, along the arrangement direction of the cell regions CL.

  In FIG. 19, each of the n-type well 2 and the p-type well 3 is shown to be divided into a plurality of parts, but this indicates a partition of one cell region CL. Each of the p-type wells 3 is not divided into a plurality of parts, but is formed integrally, that is, in a state where the predetermined impurity distribution is electrically connected as a continuous semiconductor region.

  The cell region CL is a region where a group of elements necessary for forming a logic gate of a basic unit is disposed, and the range is set to include both the n-type well 2 and the p-type well 3. Has been.

  On the main surface of the semiconductor chip SC, power supply voltage lines Vdd and Vss, well power supply lines Vwl and Vsu, and control signal lines Cwl and Csu are arranged so as to surround the group of the cell regions CL described above. . On the main surface of the semiconductor chip SC, power supply voltage lines Vdd and Vss, well feed lines Vwl and Vsu, and control signal lines Cwl and Csu are arranged in a grid pattern. FIG. 19 shows the basic unit of the lattice.

  The power supply voltage line Vdd1, the well power supply line Vwl1, and the control signal line Cwl1 are arranged in the cell region CL so as to cross the cell regions CL in the vicinity of the end in the longitudinal direction of the cell region CL (upper side in FIG. 19). It is arranged in a state extending along the direction. The power supply voltage line Vdd1, the well feeding line Vwl1, and the control signal line Cwl1 are sequentially arranged along the direction from the center of the cell region CL toward the outer periphery.

  The power supply voltage line Vss1, the well power supply line Vsu1 and the control signal line Csu1 are arranged in the cell region CL so as to cross the cell regions CL in the vicinity of the end in the longitudinal direction of the cell region CL (downward in FIG. 19). It is arranged in a state extending along the direction. The power supply voltage line Vss1, the well power supply line Vsu1, and the control signal line Csu1 are sequentially arranged along the direction from the center of the cell region CL toward the outer periphery.

  These power supply voltage lines Vdd1, Vss1, well feed lines Vwl1, Vsu1 and control signal lines Cwl1, Csu1 are made of, for example, aluminum or aluminum alloy and are formed in the first wiring layer.

  On the other hand, the power supply voltage lines Vdd2 and Vss2, the well power supply lines Vwl2 and Vsu2, and the control signal lines Cwl2 and Cwl2 are arranged so as to extend perpendicular to the arrangement direction of the cell regions CL. The power supply voltage lines Vdd2 and Vss2, the well power supply lines Vwl2 and Vsu2 and the control signal lines Cwl2 and Cwl2 are sandwiched between the power supply voltage lines Vdd2 and Vss2 Arranged in a state.

  These power supply voltage lines Vdd2, Vss2, well feed lines Vwl2, Vsu2 and control signal lines Cwl2, Csu2 are made of, for example, aluminum or an aluminum alloy and are formed in the second wiring layer.

  The power supply voltage lines Vdd2, Vss2, the well power supply lines Vwl2, Vsu2 and the control signal lines Cwl2, Csu2 arranged in the second wiring layer are the power supply voltage lines Vdd1, Vss1, and the well power supply arranged in the first wiring layer, respectively. They are electrically connected through connection holes TH at the intersections of the lines Vwl1, Vsu1 and the control signal lines Cwl1, Csu1.

  By the way, in this Embodiment, it has the following structures. First, similarly to the above-described embodiment, one switching transistor Tps, Tns (see FIG. 3 and the like) is arranged for each cell region CL, that is, for each logic gate. Therefore, it is possible to obtain the same effect as the above embodiment.

  Secondly, the power supply voltage lines Vdd1 and Vss1, the well power supply lines Vwl and Vsu1 and the control signal lines Cwl and Csu1 are arranged immediately below the first wiring layer. That is, the power supply voltage lines Vdd1, Vss1, the well power supply lines Vwl1, Vsu1 and the control signal lines Cwl1, Csu1 are usually empty areas in which elements constituting the semiconductor integrated circuit device are not arranged. By providing the switching transistors Tps and Tns in the region, the main surface of the semiconductor chip SC can be used effectively. As a result, the area of the cell region CL can be reduced as compared with the case where the switching transistors Tps and Tns are provided in a region other than the empty region, so that the degree of element integration is improved and the overall area of the semiconductor chip SC is reduced. Reduction can be promoted.

  Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 20 shows a circuit diagram of the main part of the CMOS type semiconductor integrated circuit device according to the present embodiment.

  In the present embodiment, one switching transistor Tps, Tns is provided for each of a plurality of logic gates. FIG. 20 shows, for example, an inverter circuit INV, a 2-input NAND gate circuit NA, and a 2-input NOR gate circuit NO as logic gates. However, the types of logic gates are not limited to these and can be variously changed. In addition, the logic gate group in which one switching transistor is arranged is not limited to one composed of different types of logic gates, and can be applied to one composed of the same type of logic gates.

  The inverter circuit INV is configured by connecting transistors Tp1 and Tn1 in series between power supply voltage lines Vdd and Vss. The gate electrodes of the transistors Tp1 and Tn1 are electrically connected and further electrically connected to the input line IN.

  In the 2-input NAND gate circuit NA, two transistors Tp1, Tp2 connected in parallel to each other and two transistors Tn1, Tn2 connected in series to each other are electrically connected between power supply voltage lines Vdd, Vss. Has been configured. The gate electrodes of the transistors Tp1 and Tn1 are electrically connected and further electrically connected to the input line IN1. The gate electrodes of the transistors Tp2 and Tn2 are electrically connected and further electrically connected to the input line IN2. The sources of the transistors Tp1 and Tp2 and the drain of the transistor Tn1 are electrically connected.

  In the 2-input NOR gate circuit NO, two transistors Tp1, Tp2 connected in series with each other and two transistors Tn1, Tn2 connected in parallel with each other are electrically connected between power supply voltage lines Vdd, Vss. Has been configured. The gate electrodes of the transistors Tp1 and Tn1 are electrically connected and further electrically connected to the input line IN1. The gate electrodes of the transistors Tp2 and Tn2 are electrically connected and further electrically connected to the input line IN2. The source of the transistor Tp2 and the drains of the transistors Tn1 and Tn2 are electrically connected.

  The substrate potentials of the transistors Tp1, Tp2, Tn1, Tn2 and the switching transistors Tps, Tns of the inverter circuit INV, the 2-input NOR circuit NO, and the switching transistors Tps, Tns are supplied from the well power supply lines Vwl, Vsu. It has become.

  A switching transistor Tps is electrically connected between the well power supply line Vwl and the power supply voltage line Vdd. A switching transistor Tns is electrically connected between the well power supply line Vsu and the power supply voltage line Vss.

  That is, when testing the semiconductor integrated circuit device, the leakage current can be suppressed by turning off the switching transistors Tps and Tns and supplying a predetermined potential to the well power supply lines Vwl and Vsu. The thermal runaway caused by can be suppressed. As a result, the yield and reliability of the semiconductor integrated circuit device can be improved.

  In the normal operation of the semiconductor integrated circuit device, the switching transistors Tps and Tns are turned on to supply the power supply voltages Vdd and Vss to the well power supply lines Vwl and Vsu, respectively, thereby preventing latch-up. Therefore, it is possible to ensure the operational reliability of the semiconductor integrated circuit device.

  Next, FIG. 21 and FIG. 22 show layout examples of the circuit shown in FIG.

  FIG. 21 shows a case where the well power supply lines Vwl and Vsu are constituted by an n-type well 2 and a p-type well 3. That is, a structure is shown in which well supply voltages Vwl and Vsu are supplied to the wells of a plurality of logic gates through n-type well 2 and p-type well 3, respectively.

  FIG. 22 shows a case where the well power supply lines Vwl and Vsu are constituted by the wiring L. That is, a structure is shown in which the well power supply voltages Vwl and Vsu are supplied to the wells of a plurality of logic gates through the wiring L.

  The wiring L is electrically connected to the n-type well 2 and the p-type well 3 in the cell region CL of each logic gate through the connection hole TH. That is, the well power supply voltages Vwl and Vsu can be supplied from the vicinity of each logic gate. Therefore, in the structure of FIG. 22, the well power supply voltages Vwl and Vsu can be supplied to each logic gate in a more stable state than the structure of FIG.

  Next, FIG. 23 shows a plan view of the main part of the semiconductor chip when the structure of FIG. 22 is adopted. Further, cross-sectional views of the XXIV-XXIV line and the XXV-XXV line are shown in FIGS.

  In the semiconductor chip SC, the n-type well 2 and the p-type well 3 are formed in a state extending along the horizontal direction of FIG. 23, that is, along the arrangement direction of the cell regions CL.

  In FIG. 23, the n-type well 2 and the p-type well 3 are shown to be divided into a plurality of parts, but this indicates the separation of one cell region CL. Each of the mold wells 3 is not divided into a plurality of parts, but is formed integrally, that is, in a state where they are electrically connected as one semiconductor region in which a predetermined impurity distribution continues.

  The cell region CL is a region where a group of elements necessary for forming a logic gate of a basic unit is disposed, and the range is set to include both the n-type well 2 and the p-type well 3. Has been.

  On the main surface of the semiconductor chip SC, power supply voltage lines Vdd and Vss and well power supply lines Vwl and Vsu are arranged so as to surround the group of the cell regions CL described above. However, only the control signal lines Cwl and Csu that extend in the vertical direction of FIG. 23, that is, in the direction orthogonal to the arrangement direction of the cell regions CL are arranged. In the present embodiment, as will be described later, the switching transistors Tps, Tns (see FIG. 20 and the like) have power supply voltage lines Vdd2, extending in a direction orthogonal to the arrangement direction of the cell regions CL. Since Vss2, well feed lines Vwl2, Vsu2 and control signal lines Cwl2, Csu2 are formed immediately below, the control signal lines Cwl2, Csu2 are extended in the horizontal direction of FIG. 23, that is, in the arrangement direction of the cell regions CL. This is because there is no need to arrange them. For this reason, in the present embodiment, it is possible to reduce the vertical dimension in FIG. 23, that is, the dimension in the longitudinal direction of the cell region CL.

  On the main surface of the semiconductor chip SC, power supply voltage lines Vdd and Vss and well feed lines Vwl and Vsu are arranged in a grid pattern. FIG. 23 shows the basic unit of the lattice.

  The power supply voltage line Vdd1 and the well power supply line Vwl1 extend along the arrangement direction of the cell regions CL so as to cross the cell regions CL in the vicinity of the longitudinal end portion (upper side in FIG. 23) of the cell region CL. It is arranged in the existing state. The power supply voltage line Vdd1 and the well power supply line Vwl1 are sequentially arranged along the direction from the center of the cell region CL toward the outer periphery.

  The power supply voltage line Vss1 and the well power supply line Vsu1 extend along the arrangement direction of the cell regions CL so as to cross each cell region CL on the side near the end portion (downward in FIG. 23) in the longitudinal direction of the cell region CL. It is arranged in the existing state. The power supply voltage line Vss1 and the well power supply line Vsu1 are arranged in order along the direction from the center of the cell region CL toward the outer periphery.

  These power supply voltage lines Vdd1, Vss1 and well feed lines Vwl1, Vsu1 are made of, for example, aluminum or an aluminum alloy, and are formed in the first wiring layer.

  The power supply voltage lines Vdd2, Vss2, the well power supply lines Vwl2, Vsu2 and the control signal lines Cwl2, Cwl2 are arranged so as to extend perpendicular to the arrangement direction of the cell regions CL. The power supply voltage lines Vdd2, Vss2, the well feed lines Vwl2, Vsu2 and the control signal lines Cwl2, Cwl2 are sandwiched between the power feed lines Vwl2, Vsu2 and the control signal lines Cwl2, Cwl2. Arranged in a state.

  These power supply voltage lines Vdd2, Vss2, well feed lines Vwl2, Vsu2 and control signal lines Cwl2, Csu2 are made of, for example, aluminum or an aluminum alloy and are formed in the second wiring layer.

  The power supply voltage lines Vdd2 and Vss2, the well feed lines Vwl2 and Vsu2 and the control signal lines Cwl2 and Csu2 arranged in the second wiring layer are the power supply voltage lines Vdd1 and Vss1 and the well feed line arranged in the first wiring layer, respectively. They are electrically connected through connection holes TH at intersections of the lines Vwl1 and Vsu1 and the control signal lines Cwl and Csu1.

  As described above, in the present embodiment, the switching transistors Tps and Tns described above are arranged at a ratio of one set for each of the plurality of cell regions CL, that is, the plurality of logic gates, and the power supply voltage described above. They are arranged immediately below the lines Vdd2, Vss2, well feed lines Vw2, Vsu2 and control signal lines Cw2, Csu2. In other words, the power supply voltage lines Vdd2, Vss2, the well feed lines Vwl2, Vsu2 and the control signal lines Cwl2, Csu2 are usually empty areas in which elements constituting the semiconductor integrated circuit device are not arranged. By providing the switching transistors Tps and Tns in the region, the main surface of the semiconductor chip SC can be used effectively. As a result, it is possible to suppress an increase in area as compared with the case where the switching transistors Tps and Tns are provided in a region other than the empty region. Further, as described above, the dimension in the longitudinal direction of the cell region CL can be reduced. For this reason, it becomes possible to further promote the improvement of the element integration degree and the reduction of the overall area of the semiconductor chip SC.

  FIG. 24 is a sectional view of a switching transistor Tp made of a p-channel MOS • FET. The switching transistor Tp is formed in an active region surrounded by the field insulating film 4 in the n-type well 2 and has a semiconductor region 20pl, a gate insulating film 20pi, and a gate electrode G.

  The semiconductor region 20pl has a low concentration region 20pl1 and a high concentration region 20pl2. The low concentration region 20pl1 and the high concentration region 20pl2 contain, for example, p-type impurity boron, and the high concentration region 20pl2 is set to have a higher impurity concentration than the low concentration region 20pl1.

The gate insulating film 20pi is made of, for example, silicon dioxide (SiO ₂ ), and the gate electrode G is made of, for example, a single layer film of low resistance polysilicon or a laminated film in which silicide such as tungsten silicide is deposited on the low resistance polysilicon. Become.

Although the gate electrode G is divided into a plurality of parts in FIG. 24, these gate electrodes G are actually electrically connected to each other. A sidewall insulating film 21 made of, for example, SiO ₂ is formed on the side surface of the gate electrode G.

The switch transistor Tp is covered with an interlayer insulating film 22a. The interlayer insulating film 22a is made of, for example, SiO ₂ and the power supply voltage line Vdd1 for the first wiring layer is formed thereon. The power supply voltage line Vdd1 is covered with an interlayer insulating film 22b. The interlayer insulating film 22b is made of, for example, SiO ₂ , on which power supply voltage lines Vdd2, Vss2, well power supply lines Vwl2, Vsu2 and control signal lines Cwl2, Csu2 are formed. Note that a third layer wiring is formed on the upper layer via an interlayer insulating film, and the third layer wiring is covered with a surface protective film.

  FIG. 25 shows a sectional view of a switching transistor Tn made of an n-channel MOS • FET. The switching transistor Tn is formed in the active region surrounded by the field insulating film 4 in the p-type well 3, and has a semiconductor region 20nl, a gate insulating film 20ni, and a gate electrode G.

  The semiconductor region 20nl has a low concentration region 20nl1 and a high concentration region 20nl2. The low concentration region 20nl1 and the high concentration region 20nl2 contain, for example, an n-type impurity such as phosphorus or arsenic (As), and the impurity concentration of the high concentration region 20nl2 is set higher than that of the low concentration region 20nl1.

The gate insulating film 20ni is made of, for example, SiO _2, gate electrode G is made of, for example, laminated films, such was a silicide is deposited as tungsten silicide to low-resistance poly-silicon single layer film or a low-resistance poly-on silicon.

In FIG. 25, the gate electrode G is divided into a plurality of parts, but actually, these gate electrodes G are electrically connected to each other. A sidewall insulating film 21 made of, for example, SiO ₂ is formed on the side surface of the gate electrode G.

The switch transistor Tn is covered with an interlayer insulating film 22a. This interlayer insulating film 22a is made of, for example, SiO ₂ or the like, and a power supply voltage line Vss1 for the first wiring layer is formed thereon. The power supply voltage line Vss1 is covered with an interlayer insulating film 22b. The interlayer insulating film 22b is made of, for example, SiO ₂ , on which power supply voltage lines Vdd2, Vss2, well power supply lines Vwl2, Vsu2 and control signal lines Cwl2, Csu2 are formed. Note that a third layer wiring is formed on the upper layer via an interlayer insulating film, and the third layer wiring is covered with a surface protective film.

Thus, according to the present embodiment, the following effects can be obtained in addition to the effects obtained in the embodiment described with reference to FIG.
(1) By arranging one set of switching transistors Tps and Tns for a plurality of logic gates, the total area occupied by the switching transistors Tps and Tns in the semiconductor chip SC can be reduced. Become.
(2) By providing the switching transistors Tps and Tns directly below the wiring arrangement area such as the power supply voltage lines Vdd2 and Vss2, the main surface of the semiconductor chip SC can be used effectively. As compared with the case where the switching transistors Tps and Tns are provided in this region, it is possible to suppress an increase in area.
(3) Since the switching transistors Tps and Tns are provided immediately below the wiring arrangement region such as the power supply voltage lines Vdd2 and Vss2, it is not necessary to provide the control signal lines Cwl and Csu extending in the arrangement direction of the cell region CL. Accordingly, the area of the cell region CL in the longitudinal direction can be reduced.
(4) By the above (1) to (3), it is possible to suppress an increase in chip size due to the addition of the switching transistors Tps and Tns.
(5) By the above (1) to (3), it is possible to suppress the reduction in the degree of integration of the integrated circuit element due to the addition of the switching transistors Tps and Tns.

  Next, another embodiment of the present invention will be described with reference to FIG. FIG. 26 is a principal circuit diagram of the semiconductor integrated circuit device according to the embodiment of the present invention.

  This embodiment has substantially the same structure as the above-described embodiment described with reference to FIG. The difference is that a switch control unit STC for controlling the operation of the switching transistors Tps and Tns is provided before the switching transistors Tps and Tns.

  In the present embodiment, by providing the switch control unit STC, it is possible to provide a single control signal wiring for controlling on / off of the switching transistors Tps and Tns. This is a structure that takes into account that one of the control signal lines Cwl and Csu is at a high potential (High) and the other is at a low potential (Low), and has the following configuration.

  The switch control unit STC includes transistors Tpc1, Tpc2, Tnc1, and Tnc2, and an inverter circuit INVc. The transistors Tpc1 and Tpc2 are p-channel MOS • FETs, and the transistors Tnc1 and Tc2 are n-channel MOS • FETs.

  The control signal line C is electrically connected to the gate electrodes of the transistors Tpc1 and Tnc1 through the inverter circuit INVc, and is electrically connected to the gate electrodes of the transistors Tpc2 and Tnc2 without going through the inverter circuit INVc. Yes. That is, in the present embodiment, the control signal line C is divided into two wiring paths, one of which is electrically connected to the subsequent circuit through the inverter circuit INVc, and the other wiring path is It is configured to be electrically connected to a subsequent circuit without going through the inverter circuit INVc. Thus, two control signals having different potentials are generated from one control signal, and the two signals having different potentials are transmitted to the switching transistors Tps and Tns as control signals Cwl and Csu, respectively.

  One semiconductor region of the transistors Tpc1 and Tnc1 is electrically connected to the gate electrode of the switching transistor Tps. The other semiconductor region of the transistor Tpc1 is electrically connected to the well power supply line Vwl, and the other semiconductor region of the transistor Tnc1 is electrically connected to the well power supply line Vsu.

  On the other hand, one semiconductor region of the transistors Tpc2 and Tnc2 is electrically connected to the gate electrode of the switching transistor Tns. The other semiconductor region of the transistor Tpc2 is electrically connected to the well power supply line Vwl, and the other semiconductor region of the transistor Tnc2 is electrically connected to the well power supply line Vsu.

  Thus, according to the present embodiment, the following effects can be obtained in addition to the effects obtained in the embodiment described with reference to FIG. That is, it is possible to use one control signal line for controlling on / off of the switching transistors Tps and Tns.

  Next, another embodiment of the present invention will be described with reference to FIGS. In the present embodiment, a case will be described in which the present invention is applied to an SRAM (Static Random Access Memory) incorporated in a computer such as a desktop or laptop personal computer.

  FIG. 27 is a plan view of a semiconductor chip SC having an SRAM. Peripheral circuit regions P1, P2 are arranged in the center of the semiconductor chip SC and in the vicinity of one long side (the long side on the lower side in FIG. 27).

  A peripheral circuit such as a decoder circuit is formed in the central peripheral circuit region P1. A peripheral circuit such as a sense amplifier circuit or a write circuit is formed in the peripheral circuit region P2 near the long side.

  In the peripheral circuit regions P1 and P2, the switching transistors Tps and Tns (see FIG. 3, FIG. 20 and the like) are arranged as in the above embodiment. As for the arrangement method, one switching transistor may be arranged for each logic gate, or one switching transistor may be arranged for a plurality of logic gates. Therefore, the effects obtained in the above embodiment can be obtained also in the peripheral circuit of the semiconductor integrated circuit device.

  In the semiconductor chip SC, memory cell arrays M1, M2 are arranged on both sides of the central peripheral circuit region P1. In the memory cell arrays M1 and M2, a plurality of memory cells to be described later are regularly arranged in the vertical and horizontal directions in FIG.

  In the present embodiment, the switching transistor is also arranged in the memory cell arrays M1 and M2. The switching transistors are indicated by a plurality of black squares arranged regularly in the memory cell arrays M1 and M2.

  However, a plurality of switching transistors are not limited to be provided in each of the memory cell arrays M1 and M2, and one switching transistor may be provided in each of the memory cell arrays M1 and M2.

  Further, the arrangement of the switching transistors is not limited to the arrangement in the vertical and horizontal directions in FIG. 27. For example, the switching transistors may be arranged in only the vertical or horizontal directions in FIG.

  FIG. 28 shows a memory cell MC of this SRAM. The memory cell MC is configured based on, for example, a flip-flop circuit obtained by crossing and connecting two-stage inverters having a CMOS structure, for example, and is arranged near the intersection of the word line WL and the bit line BL.

  Each inverter includes transistors Tpm and Tnm, and the input and output of one inverter are electrically connected to the output and input of the other inverter, respectively. The transistor Tpm is composed of a p-channel MOS • FET, and the transistor Tnm is composed of an n-channel MOS • FET.

  The memory cell MC is electrically connected to the bit line BL via the transistor Tnms. The transistor Tnms is made of, for example, an n-channel MOS • FET, and its gate electrode is electrically connected to the word line WL. A plurality of such memory cells MC are regularly arranged in the memory cell array.

  In the present embodiment, the substrate potential of the transistors Tpm and Tnm and the substrate potential of the transistor Tnms in the memory cell MC can be controlled from the outside of the memory cell MC. That is, it has the following configuration.

  In the memory cell arrays M1, M2 (see FIG. 27), well power supply lines Vwl, Vsu extending in parallel with the word lines WL are formed so as to sandwich the memory cells MC. The well power supply lines Vwl and Vsu are electrically connected to the wells of the transistors Tpm and Tnm and the transistor Tnms of the memory cell MC, and are connected to the power supply voltage lines Vdd and Vss via the switching transistors Tps and Tns, respectively. Electrically connected.

  In the present embodiment, the switching transistors Tps and Tns are arranged in a ratio of one for a plurality of memory cells MC. As a result, it is possible to prevent a significant increase in chip size due to the provision of the switching transistors Tps and Tns in the memory cell arrays M1 and M2. The well feeding lines Vwl, Vsu and the wells of the transistors Tpm, Tnm, and transistor Tnms may be connected through wells or through wires as shown in FIG. 21 or FIG. Also good.

  In this embodiment, in the test of the semiconductor integrated circuit device, the switching transistors Tps and Tns in the memory cell arrays M1 and M2 are turned off, and the transistors Tpm, Tnm, and Tnms are connected from the well power supply lines Vwl and Vsu. A predetermined voltage is applied to the substrate potential. As a result, the problem of leakage current during the aging test can be avoided, and the problem of thermal runaway caused by the leakage current can also be avoided.

  On the other hand, during normal operation of the semiconductor integrated circuit device, the switching transistors Tps and Tns are turned on by applying the power supply voltages Vdd and Vss to the control signal lines Cwl and Csu, respectively. As a result, the power supply voltage lines Vdd and Vss and the well feed lines Vwl and Vsu are electrically connected to set the substrate potentials of the transistors Tp and Tn to the power supply voltages Vdd and Vss, respectively. As a result, fluctuations in the substrate potential of the transistors Tpm, Tnm, and Tnms can be suppressed, so that latch-up due to fluctuations in the substrate potential can be prevented, and operational reliability of the semiconductor integrated circuit device is ensured. Is possible.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the semiconductor substrate can be a so-called SOI (Silicon on Insulator) structure semiconductor substrate in which a thin semiconductor layer for forming an element is formed on an insulating layer. A semiconductor integrated circuit device having a circuit with a combination of various semiconductor elements such as FETs or bipolar transistors, and a manufacturing technique thereof.

  In the above description, the case where the invention made mainly by the present inventor is applied to the technology of the semiconductor integrated circuit device of the logic gate circuit or the semiconductor memory circuit alone, which is the field of use as the background, has been described. Instead, the present invention can be applied to a semiconductor integrated circuit device technology having a logic gate circuit and a semiconductor memory circuit on the same semiconductor substrate such as a one-chip microcomputer. The present invention can be applied to a semiconductor integrated circuit device having at least a CMIS (Complimentary Metal Insulator Semiconductor) structure. The semiconductor integrated circuit device of the present invention is suitable for use in a semiconductor integrated circuit device built in a small electronic device such as a mobile electronic device or a video camera, or a computer such as a desktop or laptop personal computer. It is a thing.

  The present invention can be applied to the manufacturing industry of semiconductor integrated circuit devices.

1 is a schematic sectional view showing a CMOS type semiconductor integrated circuit device according to an embodiment of the present invention. 1 is a schematic layout diagram showing a CMOS type semiconductor integrated circuit device according to an embodiment of the present invention; 1 is a schematic circuit diagram showing a CMOS type semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a graph showing potentials applied to a well feeding line and a control signal line during normal operation and test of the semiconductor integrated circuit device of FIG. 1. It is explanatory drawing of the aging test apparatus for demonstrating an aging test. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic layout figure which shows the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 11 is a circuit diagram of the logic gate of FIG. 10. It is a schematic layout figure which shows the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 13 is a circuit diagram of the logic gate of FIG. 12. It is a schematic layout figure which shows the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 15 is a circuit diagram of the logic gate of FIG. 14. It is a schematic layout figure which shows the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 17 is a circuit diagram of the logic gate of FIG. 16. It is explanatory drawing which showed typically the semiconductor chip of the semiconductor integrated circuit device which is other embodiment of this invention. It is a principal part top view of the semiconductor chip in the semiconductor integrated circuit device which is other embodiment of this invention. It is a principal part circuit diagram of the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 21 is a layout diagram showing an example of a layout of the semiconductor integrated circuit device of FIG. 20. FIG. 21 is a layout diagram showing an example of a layout of the semiconductor integrated circuit device of FIG. 20. FIG. 21 is a plan view of relevant parts of a semiconductor chip in the semiconductor integrated circuit device of FIG. 20. It is sectional drawing of the XXIV-XXIV line | wire of FIG. It is sectional drawing of the XXV-XXV line | wire of FIG. It is a principal part circuit diagram of the semiconductor integrated circuit device which is other embodiment of this invention. It is a top view of the semiconductor chip in the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 28 is a circuit diagram of a memory cell of the semiconductor integrated circuit device of FIG. 27. It is a graph for demonstrating the mechanism of the thermal runaway at the time of an aging test.

Explanation of symbols

1 p-type semiconductor substrate 2 n-type well 3 p-type well 4 field insulating film 5 source 6 drain 7 drain 8 p-type semiconductor region 9 p-type semiconductor region 10 source 11 drain 12 drain 13 n-type semiconductor region 14 n-type semiconductor region 15 Insulating film 16 Wiring layer 17 Insulating film 18 Wiring layer 19 Pin 20 pl Semiconductor region 20 pl 1 Low concentration region 20 pl 2 High concentration region 20 pi Gate insulating film 20 nl Semiconductor region 20 nl 1 Low concentration region 20 nl 2 High concentration region 20 ni Gate insulating film 21 Side wall insulating films 22 a and 22 b Interlayer insulating film Tp Transistors Tp1, Tp2, Tp3 Transistors Tps Switching transistors Tn Transistors Tn1, Tn2, Tn3 Transistors Tns Switching transistors G Gate electrodes IN, IN1, IN2, IN3 Input lines OUT Output lines SI Semiconductor integrated circuit device L Wiring board A Aging furnace PWU Power supply unit PG Pattern generator NA, NA1 2-input NAND gate circuit NA2 3-input NAND gate circuit NO, NO1 2-input NOR gate circuit NO2 3-input NOR gate circuit SC Semiconductor chip CL Cell region INV Inverter circuit TH connection hole STC switch control unit Tpc1, Tpc2, Tnc1, Tnc2 transistor INVc inverter circuit P1, P2 peripheral circuit region M1, M2 memory cell array MC memory cell WL word line BL bit line Tpm, Tnm transistor Tnms transistor Vdd, Vdd1, Vdd2 Voltage (power supply voltage line)
Vss, Vss1, Vss2 Power supply voltage (power supply voltage line)
Cwl, Cwl1, Cwl2 Control signal (control signal line)
Vwl, Vwl1, Vwl2 Well feed voltage (Well feed line)
Csu, Csu1, Csu2 Control signal (control signal line)
Vsu, Vsu1, Vsu2 Well supply voltage (well supply line)
L wiring

Claims (8)

A method for manufacturing a semiconductor integrated circuit device, comprising:
A first step of forming a first conductivity type region and a second conductivity type region on a surface of a semiconductor substrate;
A second step of forming, in the first conductivity type region, a first switch transistor comprising a second conductivity type MOS • FET constituting a CMOS • FET and a different MOS • FET;
A third step of forming, in the second conductivity type region, a first conductivity type MOS • FET constituting a CMOS • FET and a second switching transistor comprising a different MOS • FET;
Forming a first power supply voltage line for supplying a first power supply voltage so as to be connected to the source of the second conductivity type MOS • FET constituting the CMOS • FET and the source of the first switch transistor ; Process,
Forming a second power supply voltage line for supplying a second power supply voltage so as to be connected to the source of the first conductivity type MOS • FET constituting the CMOS • FET and the source of the second switch transistor ; Process,
A sixth step of forming a first power supply line to be connected to the drain of the first switch transistor and the first conductivity type region;
A seventh step of forming a second power supply line so as to be connected to the drain of the second switch transistor and the second conductivity type region;
An eighth step of forming a first control signal line to be connected to the gate electrode of the first switch transistor;
A ninth step of forming a second control signal line so as to be connected to the gate electrode of the second switch transistor;
A tenth step of applying the first power supply voltage to the first power supply voltage line and supplying the second power supply voltage to the second power supply voltage line;
An eleventh step of supplying a control signal for turning off the first and second switching transistors to the first and second control signal lines;
By applying a desired voltage to the first and second power supply lines, the threshold voltages of the first conductivity type MOS • FET and the second conductivity type MOS • FET are set to the first and second switch transistors. A threshold voltage control step of setting the threshold voltage higher than the threshold voltage of the first conductivity type MOS • FET and the second conductivity type MOS • FET when
After the threshold voltage control step, a test step of performing a test of the first conductivity type MOS • FET and the second conductivity type MOS • FET,
A method for manufacturing a semiconductor integrated circuit device, comprising: In claim 1,
The first conductivity type region is an n-type well;
The second conductivity type region is a p-type well;
The second power supply voltage is smaller than the first power supply voltage;
The threshold voltage control step includes
Supplying a third voltage higher than the first power supply voltage supplied to the first power supply voltage line to the first power supply line;
Supplying a fourth voltage lower than the second power supply voltage supplied to the second power supply voltage line to the second power supply line;
A method for manufacturing a semiconductor integrated circuit device, comprising: In claim 2,
The method of manufacturing a semiconductor integrated circuit device, wherein the third voltage and the fourth voltage are supplied to the semiconductor substrate from outside the semiconductor integrated circuit device. In claim 2,
The method for manufacturing a semiconductor integrated circuit device, wherein the test step is a leak current test. In claim 2,
The method of manufacturing a semiconductor integrated circuit device, wherein the test step is an aging test. In claim 1,
The source of the first switch transistor is disposed adjacent to the source of the second conductivity type MOS • FET and is the same semiconductor region, and the source of the second switch transistor is the first conductivity type. A method for manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is formed adjacent to a source in a MOS-FET and formed as the same semiconductor region. In claim 1,
Forming the first power feed line so as to connect to the drain of the first switch transistor and the first conductivity type region; and connecting to the drain of the second switch transistor and the second conductivity type region. In this way, the step of forming the second power feeding line is performed by the same step. In claim 1,
Forming the first control signal line so as to be connected to the gate electrode of the first switch transistor;
A method of manufacturing a semiconductor integrated circuit device, wherein the step of forming the second control signal line so as to be connected to the gate electrode of the second switch transistor is performed in the same step.

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