KR960008149Y1 - Semiconductor integrated circuit - Google Patents

Abstract

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Description

Semiconductor integrated circuit

1 is a block diagram showing part of an SRAM according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating a part of the memory cell array and the row decoder of FIG. 1. FIG.

FIG. 3 is a circuit diagram illustrating a modification of the memory cell array of FIG. 2. FIG.

4 is a circuit diagram showing another example of the Bi-NMOS type word line driver circuit shown in FIG.

Fig. 5 is a diagram showing an example of power-dependent characteristics of delay time per step of the Bi-NMOS type word line driving circuit and the conventional Bi-NMOS type word line driving circuit used in the present invention.

Fig. 6 is a diagram showing an example of a planar pattern of a Bi-NMOS type word line driver circuit used in the present invention.

7 is a cross-sectional view showing an example of the structure along the line B-B in FIG. 6;

Fig. 8 is a circuit diagram showing a conventional Bi-NMOS type word line driver circuit.

FIG. 9 is a diagram showing an example of a planar pattern of the word line driver circuit of FIG. 8; FIG.

10 is a cross-sectional view showing an example of the structure along the line B-B in FIG. 9;

* Explanation of symbols for main parts of the drawings

10: row decoder 11: word line selection circuit

12: word line driver circuit 41: emitter wiring connection portion

42 connection part of base wiring 43 connection part of collector wiring

50: P-type substrate 51: N + type buried layer

52: N-collector area (intrinsic collector area) 53: collector derived area

54: P-intrinsic base area (inner base area) 55: P + outer base area

56 emitter region 57 field oxide film

58: interlayer insulating film 59: noise prevention area

61 emitter wiring 62 base wiring

63: collector wiring (collector derived electrode) 101, 102: unit row decoder

111, 112: partial row decoder MA: memory cell array

MA1, MA2: partial cell array WL, WL1, WL2: word line

MWL1, MWL2: Main word line SWL1-SWL8: Side word line

Q: NPN transistor for word line potential pullup

TN: N-channel MOS transistor for word line potential pulldown

The present invention relates to a Bi-NMOS type semiconductor integrated circuit (IC) in which a bipolar (Bi) device and a complementary insulated gate type (CMOS) device are mixed. In particular, in an IC having a memory cell array, a word line of a memory cell array is provided. A word line driver circuit for driving.

Bi-NMOS type memory LSI (large scale integrated circuit), e.g., SRAM (Static Random Access Memory), is a word line driving circuit disposed adjacent to the memory cell array area to achieve high-speed driving. Drive circuit is used.

Fig. 8 shows one circuit configuration of a Bi-NMOS type word line driver circuit. Where Vcc is the power supply potential, Vss is the ground potential, WL is the word line of the memory cell array, Q1 is the NPN transistor for pull-up of the word line potential, Q2 is the NPN transistor for pull-down of the word line potential, and RD is a word line select signal (decoder output signal). ), TP is a P-channel MOS transistor for driving the pull-up NPN transistor Q1, TN is an N-channel MOS transistor for driving the pull-down NPN transistor Q2, and R1 and R2 are resistors.

The conventional Bi-NMOS type word line driver circuit arranges 1/2 bipolar transistors per cell pitch of a memory cell array.

FIG. 9 shows a planar pattern of a part of the region (mainly the region of the NPN transistor Q1 for word line potential pull-up) in which a plurality of Bi-NMOS type word line driver circuits are arranged and arranged.

FIG. 10 shows a cross-sectional structure along the line B-B in FIG. 9.

Where (80) is a semiconductor substrate (P-type silicon substrate), (81) is an N + type buried layer buried in the substrate, (82) an N-collector region consisting of an epitaxial growth layer formed on the buried layer, (83) Is a collector-derived region diffused into the buried layer continuously as part of the collector region, 84 is a P-intrinsic base region (inner base region) formed at a portion of the surface layer portion of the collector region, and 85 is a surface layer portion of the collector region. The P + outer base region formed at a portion of 86 is an emitter region formed at a portion of the surface layer portion of the inner base region. Reference numeral 87 denotes an element isolation region formed between bipolar transistors in the substrate, 88 an element isolation field oxide film formed on a part of the substrate surface, and 89 an interlayer insulating film formed on the substrate.

Reference numeral 91 is an emitter wiring made of metal wiring connected to the emitter region via a connection hole opened in the interlayer insulating film, and is connected to one word line in the memory cell array. Reference numeral 92 is a base wiring made of a metal wiring connected to the outer base region through a connection hole opened in the interlayer insulating film.

93 is a collector wiring which consists of metal wiring which connects to the said collector lead-out area | region through the connection hole opened to the said interlayer insulation film.

In Fig. 9, reference numeral 71 denotes a connecting portion of the emitter wiring, 72 denotes a connecting portion of the base wiring, and 73 denotes a connecting portion of the collector wiring. a is the clearance between the metal wiring and the connection hole opened in the interlayer insulating film, b is the size of the connection hole, c is the distance between the metal wirings, d is the size of the bipolar transistors, e is the distance between the bipolar transistors, and f is the base of the transistor. The separation region between the substrate and the substrate, g, is the distance between the base and the collector lead wire.

Therefore, the size (d) of the bipolar transistor is the sum of the minimum processing dimensions such as the connection margin (a) with the metal wiring, the size of the connection hole (b), and the metal wiring spacing (c) in the metal wiring connection portion of each electrode. It is prescribed | regulated by the bipolar transistor mutual distance e of the isolation | separation area | region f between a base and a board | substrate, and the distance g between wirings for base-collector derivation.

However, when the memory cell size decreases and the cell pitch decreases due to an increase in memory capacity and a reduction in processing dimensions, if one or one or two bipolar transistors of a word line driving circuit are to be disposed per cell pitch It is necessary to reduce the size d of the transistor.

However, in the conventional bipolar transistor having the structure as described above, it is difficult to reduce the size d including the device isolation region between the transistors equally to the size of the memory cell.

For example, using a design loop with 0.5 μm, a = 0.2 μm, b = 0.5 μm, c = 0.5 μm, e = 3.0 μm, f = 2.0 μm, g = 1.0 μm and d = 6a + 3b + c + g + f + e = 9.2 μm is the limit.

F is an N-type isolation region width between P-type regions, and e is a P-type isolation region width between N-type regions. Each of these separation region widths can be made smaller by increasing the N-type or P-type impurity concentration, respectively. As described above, however, increasing the impurity concentration increases the capacity between the base and the collector and the capacity between the collector and the substrate, thereby degrading the performance of the bipolar transistor.

Even if the design loop is reduced, the values of e, f, and g do not change, so d is not likely to be reduced to 6 μm or less. For example, in an SRAM of 4M bits, the longitudinal dimension of the memory cell is about 5 μm, so that the bipolar transistors of the word line driver circuit are to be arranged (for example, 1/2 cell pitch) for two cells. Even if it is impossible.

As described above, when the size of a memory cell decreases as the capacity of the memory increases and the size of the processing decreases, the size of the bipolar transistor of the Bi-CMOS type word line driver circuit may not be reduced as the size of the memory cell. There has been a problem that it is difficult to arrange one-half bipolar transistors per cell pitch of the memory cell array.

The present invention has been made to solve the above problems, and even when the size of the memory cell is reduced due to the increase in the capacity of the memory and the reduction in the processing dimensions, the size of the bipolar transistor of the word line driving circuit can be easily reduced as well as the size of the memory cell. An object of the present invention is to provide a semiconductor integrated circuit capable of easily disposing one or one half of the bipolar transistors per cell pitch of a memory cell array and greatly reducing the chip size.

The present invention is a semiconductor integrated circuit having a memory cell array formed on an integrated circuit chip and a plurality of driving circuits arranged adjacent to a memory cell array region, wherein each word line driving circuit pulls up a word line potential of the memory cell array. A Bi-NMOS type word line driver circuit having a bipolar transistor for forming and an N-channel MOS transistor for pulling down the word line, wherein each bipolar transistor collector layer of a plurality of arranged word line driver circuits is formed in common. do.

Since the collector layers of the bipolar transistors of the plurality of word line driver circuits are arranged in common, element isolation regions between the bipolar transistors can be omitted. Further, the collector derived electrode of the bipolar transistor can be formed in common in each group including at least two adjacent word line driver circuits among a plurality of word line driver circuits arranged in series.

Therefore, when the size of the memory cell is reduced due to the increase in the capacity of the memory and the reduction in the processing dimensions, the size of the bipolar transistor of the word line driver circuit can be easily reduced as well as the size of the memory cell. It is easy to place one or one-half per array cell pitch, resulting in a significant chip size reduction.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 shows a part of a Bi-CMOS type SRAM according to an embodiment of the present invention.

(MA) is a memory cell array formed on an IC chip, (10) is a row decoder provided at one end of a row direction of the memory cell array region, and (13) is a sense amplifier provided at one end of a column direction of the memory cell array region Thermal decoder.

FIG. 2 is a circuit diagram illustrating portions of the memory cell array MA and the row decoder 10 of FIG. 1.

In the memory cell array MA, the static memory cells MC1, MC2, ... are arranged in an m-row by n-row matrix, and here, two rows by two columns are representatively derived and displayed. (WL1, WL2) are word lines, (BL1 / BL1), and (BL2 / BL2) are bit line pairs.

The row decoder 10 is provided with unit row decoders 101, 102, ... corresponding to each row of the memory cell array MA. Each unit row decoder (101, 102, ...) has a word line selection circuit 11 for decoding a row selection address signal and a word in accordance with the output signal (word line selection signal) 12D of the word line selection circuit 11. A Bi-NMOS type word line driver circuit 12 for outputting a line drive signal is provided, and the word line driver circuit 12 is provided adjacent to one end of the row direction of the memory cell array MA region.

The Bi-NMOS type word line driver circuit 12 includes a CMOS inverter (consisting of a P-channel MOS transistor TP1 and an N-channel MOS transistor TN1) input by the word line selection signal RD, and the CMOS inverter. A word line potential pull-up NPN transistor Q in which a base is connected to an output node of the output node, a collector is connected to a power supply potential VCC node, and an emitter is connected to a word line, and the word line and ground potential Vcc. A word line potential pull-down N-channel MOS transistor TN is connected between nodes and inputs the word line select signal RD to the gate.

FIG. 3 is a circuit diagram illustrating a modification of the memory cell array MA of FIG. 2.

The memory cell array MA is divided into a plurality of blocks (partial cell arrays) MA1, MA2... In the row direction, and corresponding to the partial cell arrays MA1, MA2... Is provided, and the double word line method is adopted.

In this memory cell array MA, (MWL1, MWL2 ...) are the main word lines of each row selected by the main word line selection signals from the unit row decoders 101, 102 ....

In the first partial row decoder 111 ..., (G1, G2 ...) are a sub-word line selection gate which processes the logical product of the first main word line MWL1 and the signal and the block selection signal (section decode signal), (G1, G2 ...) is a word-line selection gate which processes the logical product of the signal of the second main word line MWL2 and the block selection signal. (SWL1, SWL2, ...) are sublines, which are output lines of the sub-line selection gates G1, G2, ..., and (SWL3, SWL4, ...) are sublines, which are output lines of the sub-line selection gates, G1, G2, .... It is good.

In the second partial row decoder 112.., (G5, G6...) Are a sub-line selection gate for processing the logical product of the signal of the first main word line MWL1 and the block selection signal, and the (G7, G8... Denotes a negative word line selection gate that processes the logical product of the signal of the second main word line MWL2 and the block selection signal. (SWL5, SWL6 ...) are the sublines of the output lines of the subwoofer selection gates G5, G6 ..., and (SWL7, SWL8 ...) are the sublines of the output lines of the subwoofer selection gates G7, G8 .... It is good.

Another example of the Bi-NMOS type word line driver circuit 12 in FIG. 2 of FIG. 4 is shown.

In the word line driver circuit 12 of FIG. 2, the word line select signal RD is input to the gate instead of the CMOS inverter, and the drain and the source are connected to the Vcc node and the word line potential pull-up NPN transistor. The P-channel MOS transistor TP1 connected between the base of (Q) and the base charge discharge resistor R connected between the base and the emitter of the NPN transistor Q are used. The same as the word line driver circuit 12 shown in FIG.

As the operating power supply potential Vcc of the Bi-NMOS type word line driver circuit 12 shown in FIG. 2 or 4, a potential (for example, 3.3V) in the range of 2V to 3.7V is supplied.

Fig. 5 shows an example of the power-dependent characteristic of the delay time in one phase of the Bi-NMOS type word line driving circuit used in this embodiment and the Bi-CMOS type word line driving circuit used in the conventional example.

As the element miniaturization of the SRAM progresses and the internal power supply voltage is lowered, the operation speed of the word line driver circuit is affected. That is, when the potential (for example, 3.3V) within the range of 2-3.7V is supplied as the operating power supply potential Vcc of the word line driving circuit, Bi is less than the Bi-CMOS type word line driving circuit as shown in FIG. -Since the operating speed of the NMOS type word line driving circuit becomes faster, the present embodiment is superior in word line driving speed than the conventional example. FIG. 6 shows a planar pattern of a part of the region (mainly the region of the word line potential pull-up NPN transistor Q...) Provided with a plurality of Bi-NMOS type word line driver circuits 12. .

Here, 41 is a connection part of the emitter wiring 61, 42 is the connection part 43 of the base wiring 62, and is a connection part of the collector wiring 63. As shown in FIG.

FIG. 7 shows a cross-sectional structure along the line B-B in FIG. 6.

Here, reference numeral 50 denotes a semiconductor substrate (P-type silicon substrate), 51 denotes an N + type buried layer buried in the substrate, and 52 denotes an N-collector region (intrinsic collector) formed of an epitaxial growth layer formed on the buried layer. Regions 53, 53 are collector-derived regions diffused so as to form the buried layer in a part of the collector region, and 54 are P-intrinsic base regions (inner base region) formed in a portion of the collector region surface layer portion, 55 Is a P + outer base region formed in a part of the collector layer surface layer portion, and 56 is an emitter region formed in a portion of the surface layer portion of the inner base region. Reference numeral 57 denotes a field oxide film for element isolation formed on a part of the substrate surface, and 58 an interlayer insulating film formed on the substrate.

Reference numeral 61 is an emitter wiring formed of a metal wiring connected to the emitter region through a connection hole opened in the interlayer insulating film, and is connected to the word line WL of the memory cell array MA.

Reference numeral 62 is a base wiring made of a metal wiring connected to the outer base region through a connection hole opened in the interlayer insulating film.

Reference numeral 63 denotes a collector lead electrode and a collector wiring made of a metal wiring connected to the collector lead-out area through a connection hole opened in the interlayer insulating film.

In this case, the collector derivation electrode 63 of the bipolar transistor Q is formed in common in each group of two adjacent word line driving circuits, and the collector derivation electrode 63 is common as described above. 2 word line driving circuits are repeatedly arranged in a direction (column direction) perpendicular to the row direction of the memory cell array MA, as shown in the circuit diagram of FIG. 2 or FIG.

In addition, when the memory cell array MA employs the double word line system as shown in Fig. 3, the main word lines MWL1, MWL2, ... correspond to the word lines WL.

In addition, one emitter wiring 61 may be provided for each of a plurality of word lines WL of the memory cell array MA.

In the SRAM of the above embodiment, the collector layers (N-collector regions 52) of the bipolar transistors Q of the plurality of arranged word line driver circuits 12... Are formed in common, and the bipolar transistors Q... The element isolation region (87 in Fig. 10) is omitted.

Further, the collector derivation electrode 63 of the bipolar transistor Q is formed in common in each of the plurality of word line driver circuits 12.

Therefore, even when the size of the memory cell decreases as the memory capacity increases and the process size decreases, it is easy to reduce the size of the bipolar transistor Q of the word line driving circuit as well as the size of the memory cell. It is easy to place one or one (Q) per cell pitch of the memory cell array, which can greatly reduce the chip size.

In the case where the bipolar transistor is arranged as described above, the size D of the bipolar transistor is determined by the separation distance h between the emitters in addition to the a, b, c, and d, so that D = 5a + 2.5B + c + g + 0.5h. do. Here, for example, in the case of using a design loop of 0.5 µm, a = 0.2 µm, b = 0.5 µm, c = 0.5 µm, e = 1.0 µm, h = 2.0 µm, and D = 4.75 µm. For example, in a 4M bit SRAM, the longitudinal dimension of the memory cell is about 5 mu m, so that one bipolar transistor of the word line driving circuit can be arranged per cell pitch.

In addition, since each emitter region 56 of each set of two word line driving circuits adjacent to each other in the collector region 52 faces each other, hot water generated immediately below each emitter region 56 is generated. There is a fear that noise due to carriers may occur. In order to prevent this, the noise preventing region 59 having a higher impurity concentration than the intrinsic collector region 52 between each emitter region 56 having two sets of word line driving circuits adjacent to each other in the collector region 52 is provided. It is good to form a diffusion. That is, the impurity concentration of the intrinsic collector region 52 is, for example, 10 ¹⁶ -10 ¹⁷ CM ^-3 and the impurity concentration of the noise prevention region 59 is, for example, 10 ¹⁸ -10 ²⁰ CM ^-3 . .

As such, the region 59 having a high impurity concentration exists between the emitter regions 56 so that the impact ionization current (that is, the impact ionization phenomenon) due to the synergistic effect of the collector current and the high field effect in the intrinsic collector region 52. The lifetime of the minority carriers occurring, in this case the holes), is drastically reduced in the high concentration region 59. Thus, they do not reach adjacent emitter regions 56 or base regions 54 and 55 and recombine with the majority carrier (electrons in this example).

Therefore, as shown in the above embodiment, even when the emitter regions 56 are adjacent to each other through the high concentration region 59 in the common collector structure, there is a fear that an operation defect due to noise may occur between the adjacent emitter regions 56. Disappears.

However, the impact ionization phenomenon depends on the operating conditions of the bipolar transistor of the word line driver circuit.

In addition, drawing reference numbers which refer to the respective configuration requirements of the claims of the present application are for facilitating the understanding of the present invention and do not limit the technical scope of the present invention to the embodiments shown in the drawings.

As described above, according to the present invention, even when the memory cell size is reduced due to the increase in memory capacity and the reduction in processing dimensions, the size of the bipolar transistor of the word line driving circuit can be easily reduced like the size of the memory cell. The bipolar transistors can be easily arranged by one or half of the cell pitch of the memory cell array, thereby realizing an IC that can greatly reduce the chip size.

Claims (12)

A semiconductor integrated circuit comprising: a substrate; A memory cell array formed on the substrate and having a plurality of memory cells, a plurality of word lines, and a plurality of bit lines arranged in a matrix; And a bi-polar transistor disposed adjacent to the memory cell array, each having a bipolar transistor having a collect layer formed of the same layer pulling up the potential of the word line, and an N-channel MOS transistor for pulling down the potential of the word line. A semiconductor integrated circuit comprising a plurality of word line driver circuits, which are NMOS circuits. 2. The semiconductor integrated circuit according to claim 1, wherein only one collector lead to the collector of the bipolar transistor of any two adjacent word line driving circuits is connected to the same collector lead extending perpendicular to the word line. . The semiconductor device according to claim 1, wherein each of the bipolar transistors for pulling up the potential of a word line is a semiconductor substrate of a first conductivity type, a collector layer buried in the semiconductor substrate as a second conductivity type opposite to the first conductivity type, A second conductive type intrinsic collector region formed on the collector layer, a collector lead region formed by impurity diffusion into a portion of the intrinsic collector region and connected to the collector layer, and formed in a surface of a portion of the intrinsic collector region An inner base region of a first conductivity type, an outer base region of a first conductivity type formed within a surface of a portion of the intrinsic collector region, and an emitter region of a second conductivity type formed on a surface of a portion of the inner base region; An emitter line extends parallel from the emitter region to the word line of the memory cell array; And the collector lead region is parallel to the emitter line in a direction opposite to the direction in which the emitter line extends. 4. The semiconductor integrated circuit according to claim 3, wherein only one collector lead for the collector of bipolar transistors of any two adjacent word line driving circuits is connected to the same collector lead extending perpendicular to the word line. . 4. The intrinsic collector region of claim 3, wherein a high impurity concentration region having an impurity concentration higher than that of the intrinsic collector region is located between emitter regions of bipolar transistors of any two adjacent word line driver circuits. And a semiconductor integrated circuit. 5. The intrinsic collector region of claim 4, wherein a high impurity concentration region having an impurity concentration higher than that of the intrinsic collector region is located between emitter regions of bipolar transistors of any two adjacent word line driver circuits. And a semiconductor integrated circuit. The method of claim 5, wherein the intrinsic collector region has an impurity concentration of 10 ¹⁶ to 10 ¹⁷ cm ^{31 3} , the high impurity concentration region comprises an impurity concentration of 10 ¹⁶ to 10 ²⁰ cm ^-3 Semiconductor integrated circuits. The method of claim 6, wherein the intrinsic collector region has an impurity concentration of 10 ¹⁶ to 10 ¹⁷ cm ^{31 3} , the high impurity concentration region comprises an impurity concentration of 10 ¹⁸ to 10 ²⁰ cm ^-3 Semiconductor integrated circuits. The semiconductor integrated circuit according to claim 1, wherein an operating power supply voltage of 2V to 3.7V is applied to the word line driver circuit. The semiconductor integrated circuit according to claim 1, wherein said memory cell array and said word line driver circuit are integrated in an SRAM integrated circuit. 11. The semiconductor integrated circuit according to claim 10, wherein the bipolar transistors for pulling up the potential of the word line include an emitter electrode connected to a word line of a memory cell array incorporated in the SRAM integrated circuit. 12. The bipolar transistor of claim 10, wherein the bipolar transistors for pulling up the potential of a double word line having a memory cell array having a main word line are connected to a main word line of a memory cell array of the SRAM integrated circuit. A semiconductor integrated circuit comprising an emitter electrode.