JPH09265792A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield in semiconductor memories, for example, static RAMs by relieving the failure of current in the mode flowing through the memory cell power source line. SOLUTION: Memory cell power source lines and power source lines for supplying the power source to a plurality of bit lines are connected in common to each normal memory cell group and memory cell power source lines are electrically separated between the normal memory cell groups. A means which electrically separates the above common connection lines set for each normal memory cell group from the power source line supplied from the power source PAD. For example when a failure that current flows to the memory cell 21 through the memory cell power source line occurs, the subblock 81 including the faulty memory cell is replaced by a spare subblock, and at the same time the power source separating circuit 2 is made non-conductive. Thereby the power source lines of all memory cells constituting the eliminated subblocks and the power source lines supplying power source to bit line loading circuit are made floating, interrupting the leakage current flowing path.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Further, the present invention relates to a technique for improving the yield, for example, a technique effectively applied to a static RAM (static random access memory).

[0002]

2. Description of the Related Art A technique of introducing redundancy into a chip to improve the yield of a semiconductor memory device is effective in repairing defects in a memory cell area and is a commonly used technique.

The redundant configuration will be briefly described below.

Conventionally, a spare element which replaces a defective bit is constructed by including a spare row or a spare row group (spare row) and a spare column or a spare column group (spare column) as a part of a memory cell array. . When performing defect relief, the position (address) of a defective cell is detected by a wafer probe test. A redundant program for replacing the defective bit with the defective relief bit is performed according to the detected address. Then, when an address to be relieved is supplied to the semiconductor memory device on which the redundant program has been performed, after the selection operation of the memory cell by the normal address decoder is prohibited, the addressing of the defect relief bit included in the spare row or the spare column is performed. Is performed by a preliminary decoder. For the redundant configuration, refer to “Nikkei Electronics”, pages 189 to 20, published on July 21, 1980.
It is described on page 1.

By using this general method, the function can be relieved. However, for example, in a current failure mode in which a current path to the ground line is formed via the bit line load MOS transistor, the current failure cannot be relieved, so that the DC leak current continues to flow. In particular, in a device having a battery backup function, the power supply current during standby becomes a problem.

A technique for solving such a problem is described in, for example, Japanese Patent Application Laid-Open No. 59-201298 (FIG. 17), and this conventional example shows bit lines 31 to 31.
4 and the bit line precharge transistors 11 to 14 are electrically connected to each other so as to cut off the power supply.
By providing 204, when a function failure is found, this route is cut off to attempt current relief. In addition, in this conventional example, 20
Numerals 1 to 204 are fuses made of polysilicon, which are cut by a means such as a laser.

As another conventional example, Japanese Patent Application Laid-Open No. 5-62 is known.
There is a technique described in Japanese Patent Publication No. 496 (FIG. 18), and in this conventional example, a sub-block (8
1, 82, etc.), an electric conduction means 2 capable of cutting off the power supply is provided in the path between the power supply line 1 and the bit line precharge transistors 11 to 14 which are supplied with a potential from the power supply pad, and in the corresponding sub-block. When a function failure is found in the above, the current path is cut off to attempt relief from the current failure. In this conventional example, the electrically conducting means 2 is the uppermost conductive layer or a conductive layer whose surface can be exposed by pad etching, and is cut by an etching process using a FIB device or the like. .

[0008]

Although the conventional technique described in FIG. 17 is effective for the mode in which the current flows through the bit line load transistor, it causes a short circuit between memory cell nodes and a memory cell node. There is a problem that a defective mode in which a current flows through a power supply line of a memory cell such as a short circuit between a cell power supply and a cell node and a leak between a memory cell node and a bulk (ground potential) cannot be relieved.

Further, the electrical conducting means is specifically a fuse provided for each bit line, but it is very difficult in terms of layout to provide such a fuse for each bit line. Even if the layout can be completed, there are problems that the layout area becomes very large, and that the fuse cut by the laser requires ultra-high accuracy.

Further, since the fuse is provided in series with the bit line, the parasitic resistance is equivalent to that added to the bit line, which adversely affects various characteristics such as the write recovery time.

The conventional technique described with reference to FIG. 18 has a problem that the defective mode in which current flows through the power supply line of the memory cell cannot be relieved as in the conventional example of FIG.

Further, the electrically conducting means is the uppermost wiring layer or a wiring layer capable of performing a wafer probe test, and is cut by an etching process using a FIB device or the like, and then the insulating film is deposited. Therefore, in mass production, there were problems such as poor throughput and complicated process.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of normal memory cell groups having a plurality of memory cells arranged in a matrix, a spare memory cell group, and the normal memory. In a semiconductor memory device having means for switching to the spare memory cell group in cell group units,
The memory cell power supply line is electrically commonly connected to each of the normal memory cell groups, and the memory cell power supply line is electrically separated between the normal memory cell groups, and the memory cells are provided for each of the normal memory cell groups. A means for electrically disconnecting the power supply line and the power line supplied with the potential from the power pad is provided.

According to the semiconductor memory device of the first aspect,
Since the means for electrically disconnecting the memory cell power supply line and the power supply line supplied with the potential from the power supply pad is provided, it is possible to relieve the current failure in the mode that flows through the power supply of the memory cell, which has been impossible in the past. It has the effect that

Further, the redundant replacement is performed in units of sub-blocks having a plurality of bit line pairs, and the memory cell power supply line is cut off in units of sub-blocks.
There is an effect that it is possible to avoid the problems such as the layout area becoming very large and the fuse cutting requiring super high precision as shown in the related art example.

A semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the memory cell power supply line provided for each of the normal memory cell groups includes:
Further, a bit line load circuit power supply line for supplying power to a plurality of bit line load circuits is electrically commonly connected, and a memory cell power supply line provided for each of the regular memory cell groups and the plurality of bit line loads. Means for electrically disconnecting a common connection line with a bit line load circuit power supply line for supplying power to the circuit and a power line supplied with a potential from a power pad are provided.

According to the semiconductor memory device of the second aspect,
Since the memory cell power supply line and the bit line load circuit power supply line for supplying power to a plurality of bit line load circuits are connected in common, the current failure in the mode flowing through the bit line precharge circuit is also caused. It has an effect that it can be relieved.

A semiconductor memory device according to claim 3 of the present invention is the semiconductor memory device according to claim 1 or 2, wherein the disconnecting means includes a program circuit including a fuse element, and the program circuit. And a switch circuit controlled by the output.

According to the semiconductor memory device of the third aspect,
Since the power supply disconnecting circuit is realized by an electronic circuit using a fuse element, a MOS transistor, etc., the throughput of the wafer process is lowered as in the conventional example shown in FIG.
This has the effect of avoiding the problem of complicated processes.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the switch circuit connects a first conductivity type transistor and a second conductivity type transistor in parallel. It is characterized in that it includes a transmission gate.

According to the semiconductor memory device of the fourth aspect,
Since the switch circuit uses the transmission gate, the potential of 3 (corresponding to 4 for the memory cell power supply line 3 in the second embodiment) responds to the fluctuation of the power supply voltage at high speed. Therefore, it is possible to stabilize the operation at the time of turning on the power supply, and to prevent bump access delay and the like. Finally, in addition to function relief, current relief is possible, which has the effect of improving yield.

According to a fifth aspect of the present invention, in a semiconductor memory device, a plurality of normal memory cell groups in which a plurality of memory cells are arranged in a matrix, a spare memory cell group, and a spare memory in units of the normal memory cell group are provided. A semiconductor memory device having a cell group and switching means, wherein a memory cell power supply line is electrically commonly connected for each normal memory cell group, and the memory cell power supply line is electrically connected between the normal memory cell groups. And a semiconductor memory device having means for electrically disconnecting the memory cell power supply line provided for each of the normal memory cell groups and the power supply line supplied with the potential from the power supply pad, or the normal memory cell For each group, electrically connect the bit line load circuit power supply lines for supplying power to the bit line load circuit in common, and then connect the bit line load circuit power supply line with the potential supplied from the power supply pad. Or a bit line power supply line for supplying power to a plurality of bit line load circuits in a semiconductor memory device provided with means for selectively disconnecting the memory cell power supply line provided for each normal memory cell group. Electrically connected in common, and a common connection line and a power supply line for supplying a power to the memory cell power supply line provided for each of the regular memory cell groups and a plurality of bit line load circuits. In a semiconductor memory device including means for electrically disconnecting a power supply line supplied with a potential from a pad, the memory cell group, the bit line load circuit group, and the power supply disconnection circuit group are arranged adjacently in this order. It is characterized by

According to the semiconductor memory device of the fifth aspect,
By arranging the power supply disconnection circuit, the bit line load circuit, and the memory cell adjacently and in this order,
The impedance from the power supply disconnecting circuit to the bit line load circuit and the memory cell power supply line can be minimized, and the effective memory cell power supply potential can be prevented from lowering due to an unnecessary potential drop of the power supply line. Further, by not providing the power supply disconnecting circuit in the redundant portion, it is possible to prevent an unnecessary decrease in yield. Further, it is possible to prevent the impedance of the switch forming the power supply disconnecting circuit from being added to the power supply line of the redundant section, and to prevent the effective memory cell power supply potential from being lowered due to an unnecessary potential drop of the power supply line in the redundant section. Have.

A semiconductor memory device according to a sixth aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the memory cell power supply line is electrically commonly connected to the center or substantially the center of the normal memory cell group. A semiconductor memory device comprising: a first region; and a second region for separating a memory cell power supply line between the normal memory cell groups.

According to the semiconductor memory device of the sixth aspect,
To provide a layout configuration in which a first region for electrically commonly connecting the memory cell power supply lines is provided in the center of the normal memory cell group and a second region for separating the memory cell power supply line is provided between the normal memory cell groups. At the same time that the circuit configuration according to claim 1 can be realized, by arranging a wiring region where the memory cell VDD lines are bundled at the center of the sub-block, the resistances of the VDD lines of the left and right memory cell arrays are made the same, and the wiring region is This has the effect of minimizing the resistance of the VDD line that is affected by the layout arrangement of 406.

A semiconductor memory device according to a seventh aspect of the present invention is the semiconductor memory device according to the sixth aspect, wherein the memory cell ground line is a ground line having a resistance lower than that of the memory cell ground line in the first region. It is characterized by electrically common connection.

According to the semiconductor memory device of the seventh aspect,
The semiconductor memory device according to claim 6, wherein a memory cell V
Since the wiring region 406 that bundles the memory cell VDD lines also serves as the lining of the SS lines, there is an effect that a low voltage operation margin can be secured at the same time without increasing the layout area (increasing the chip area).

A semiconductor memory device according to an eighth aspect of the present invention is the semiconductor memory device according to the sixth aspect, characterized in that a sub-potential of a memory cell region is applied in the first region.

According to the semiconductor memory device of the eighth aspect,
7. The semiconductor memory device according to claim 6, wherein the wiring region in which the VDD lines are bundled serves to secure the sub-potential, so that the back-gate effect is prevented and the latch-up is achieved by stabilizing the sub-potential without increasing the layout area. This has the effect of simultaneously preventing the above.

A semiconductor memory device according to a ninth aspect of the present invention is the semiconductor memory device according to the sixth aspect, wherein the memory cell ground line has a resistance lower than that of the memory cell ground line in the first region. It is characterized in that they are electrically commonly connected and a potential of a well region in which a memory cell is formed is applied.

According to the semiconductor memory device of the ninth aspect,
The semiconductor memory device according to claim 6, wherein a memory cell V
The memory cell VD is used to line the SS line and secure the sub-potential.
Since the wiring region that bundles the D lines also serves as a wiring region, it is possible to achieve a low-voltage operation margin, a back gate effect by stabilizing the sub-potential, and a latch-up at the same time without increasing the layout area. Have.

A semiconductor memory device according to a tenth aspect of the present invention is the semiconductor memory device according to the seventh aspect, wherein the memory cell power supply line and the memory cell power supply line provided for each memory cell group are the above-mentioned. The memory cell ground line and the memory cell ground line electrically connected in common in the first region are composed of a ground line having a resistance lower than that of the memory cell ground line and an upper conductive layer, or the memory The cell power line and the memory cell power supply line provided for each memory cell group are connected to the memory cell ground line and the memory cell ground line electrically connected in common in the first region. It is characterized in that it is composed of a low resistance ground line and a lower conductive layer.

According to the semiconductor memory device of the tenth aspect, in the semiconductor memory device of the seventh aspect, the wiring common memory cell power source (VDD) in which the memory cell VDD lines are bundled.
Since the supply line 410 is arranged above or below the wiring common memory cell ground line 411 that bundles the memory cell VSS lines, the layout area of the region 406 can be reduced.

A semiconductor memory device according to claim 11 of the present invention is the semiconductor memory device according to claim 8, wherein the memory cell power supply line and the memory cell power supply line provided for each memory cell group are the In the first region, the memory cell ground line is composed of a ground line having a resistance lower than that of the memory cell ground line electrically connected to each other and an upper conductive layer.

According to the semiconductor memory device of the eleventh aspect, in the semiconductor memory device of the eighth aspect, the common memory cell power supply line 410, which is a wiring in which the memory cell VDD lines are bundled, and the memory cell VSS line are bundled. Since the wiring is arranged on the common memory cell ground line 411 which is another wiring, the layout area of the wiring region 406 can be reduced.

According to a twelfth aspect of the present invention, in the semiconductor memory device according to the ninth aspect, the memory cell power supply line and the memory cell power supply line provided for each memory cell group are the memory cells. The memory cell ground line and the memory cell ground line in the first region are electrically connected in common to each other, and are composed of a ground line having a resistance lower than that of the memory cell ground line and an upper conductive layer.

According to the semiconductor memory device of the twelfth aspect, in the semiconductor memory device of the ninth aspect, the common memory cell power supply line 410, which is a wiring in which the memory cell VDD lines are bundled, is bundled in the memory cell VSS line. Since it is arranged on the common memory cell ground line 411 which is a wiring, there is an effect that the layout area of the wiring region 406 can be reduced.

A semiconductor memory device according to a thirteenth aspect of the present invention is the semiconductor memory device according to the seventh or eighth or ninth aspect, in which the memory cell power supply line provided for each memory cell group and the first memory cell are provided. In the region, a ground line having a resistance lower than that of the memory cell ground line electrically connected to the memory cell ground line in common is formed by another conductive layer.

According to the semiconductor memory device of the thirteenth aspect, in the semiconductor memory device of the seventh to ninth aspects, the common memory cell power supply line 410 and the common memory cell ground line 4 are provided.
Since 11 is composed of different layers, the layout area can be reduced, and at the same time, the short circuit between layers due to particles or the like can be prevented and the yield can be improved.

A semiconductor memory device according to a fourteenth aspect of the present invention is the semiconductor memory device according to the thirteenth aspect, which is lower than a memory cell ground line electrically connected in common in the first region. The sheet resistance value of the ground line of the resistor is smaller than the sheet resistance value of the memory cell power supply line provided for each memory cell group.

According to the semiconductor memory device of the fourteenth aspect, in the semiconductor memory device of the thirteenth aspect, the resistance of the memory cell ground line is lowered preferentially, so that the low voltage operation margin can be secured. There is.

A semiconductor memory device according to a fifteenth aspect of the present invention is the semiconductor memory device according to the fourteenth aspect, which is lower than a memory cell ground line electrically connected in common in the first region. The ground line of the resistor is a metal layer, and the memory cell power supply line provided for each memory cell group is a polycrystalline silicon layer or a polycrystalline silicon layer containing a refractory metal.

According to the semiconductor memory device of the fifteenth aspect, in the semiconductor memory device of the fourteenth aspect, the common memory cell ground line 411 is made of a metal conductive layer and the common memory cell power supply line 410 is made of polysilicon or polycide. By configuring, a metal wire having a low resistance is intentionally used for the common memory cell power supply line 410 and the common memory cell ground line 41.
Since it does not need to be used for both of No. 1 and No. 1, there is an effect that a low cost semiconductor memory device can be realized without adding a second layer metal wiring step. In addition, even if the metal two-layer wiring process is premised, the metal wiring of the first layer and the metal wiring of the second layer do not run in the same direction, which increases the degree of freedom of wiring in the memory cell region. Have.

A semiconductor memory device according to a sixteenth aspect of the present invention is the semiconductor memory device according to the fifteenth aspect, further comprising a static memory cell using a thin film transistor as a load, wherein each memory cell group is The memory cell power supply line provided in the memory cell is formed of the same conductive layer as the conductive layer forming the gate electrode of the thin film transistor.

According to the semiconductor memory device of the sixteenth aspect, in the semiconductor memory device of the fifteenth aspect, the wiring layer of the common memory cell power supply line 410 also serves as a polysilicon layer or a polycide layer forming the memory cell. Therefore, there is an effect that a low-cost semiconductor memory device can be realized without adding an additional step.

A semiconductor memory device according to a seventeenth aspect of the present invention is the semiconductor memory device according to the sixteenth aspect, wherein the source electrode and the drain electrode of the thin film transistor are of the first conductivity type and the gate is of the second conductivity type. In a semiconductor memory device having a second type memory cell, a memory cell power supply line provided for each memory cell group is formed of a second conductivity type polycrystalline silicon layer.

According to the semiconductor memory device of the seventeenth aspect, in the semiconductor memory device of the sixteenth aspect, the reverse diode which is parasitic in series with the memory cell power supply line is avoided so that an effective memory is obtained. The cell power supply voltage can be secured and good retention characteristics can be obtained.

A semiconductor memory device according to an eighteenth aspect of the present invention is the semiconductor memory device according to the sixth aspect, wherein the memory cell ground line has a resistance lower than that of the memory cell ground line in the second region. It is characterized by electrically common connection.

According to the semiconductor memory device of the eighteenth aspect, in the semiconductor memory device of the sixth aspect, the memory cell VSS line is lined by the isolation region sub-block isolation region 405 of the memory cell VDD line. Therefore, without increasing the layout area (increasing the chip area),
This has an effect that a low voltage operation margin can be secured at the same time.

A semiconductor memory device according to a nineteenth aspect of the present invention is the semiconductor memory device according to the sixth aspect, characterized in that a sub-potential of a memory cell region is applied in the second region.

According to the semiconductor memory device of the nineteenth aspect, in the semiconductor memory device of the sixth aspect, since the sub-potential is secured by the isolation region of the memory cell VDD line, the layout area is not increased. By stabilizing the sub-potential, the back gate effect and the latch-up can be prevented at the same time.

According to a twentieth aspect of the present invention, in the semiconductor memory device according to the sixth aspect, in the second region, the memory cell ground line is a ground line having a resistance lower than that of the memory cell ground line. It is characterized in that they are electrically commonly connected and a sub-potential of the memory cell region is applied.

According to another aspect of the semiconductor memory device of the present invention, in the semiconductor memory device of the sixth aspect, the memory cell VSS line is lined and the sub-potential is secured by the isolation region of the memory cell VDD line. Therefore, there is an effect that the back gate effect and the latch-up can be prevented at the same time by securing the low voltage operation margin and stabilizing the sub-potential without increasing the layout area.

[0054]

FIG. 7 shows a part of a static RAM according to an embodiment of the present invention. In the figure, 301 is a normal memory cell array consisting of a plurality of memory cell groups in which a plurality of memory cells are arranged in a matrix, 302 is a normal decoder circuit for selecting rows and columns of the normal memory cell array 301, and 303 is an address signal. An address buffer for fetching. 3
Reference numeral 04 is a spare memory cell group, reference numeral 305 is a spare decoder as a spare memory cell selecting means, and reference numeral 306 is a spare program circuit for performing a redundant program for replacing a defective bit with a defective relief bit.

In the above structure, when a defective portion is found in the normal memory cell array 1 by a wafer probe test or the like, the fuse provided in the spare program circuit 306 is cut so as to correspond to the defective address, and thereafter, the defective portion is defective. A spare memory cell group is selected instead of the memory cell group including the location.

<Regarding Semiconductor Memory Device><First Embodiment of Semiconductor Memory Device> Referring to FIG.
A first embodiment of a semiconductor memory device of the present invention will be described. FIG. 1 is a diagram showing a part of the normal memory cell array 301 shown in FIG. Sub blocks 81 to 8
3 will be described. The memory cell array portion includes a plurality of memory cells 21 to 24 arranged in a matrix and complementary bit lines 31 to 34 wired for each memory cell column.
Word lines (61, 62) provided for each memory cell row
And The memory cells 21 to 24 are static cells.

Each bit line is provided with column gate transistors 41 to 44 for transferring data. Further, bit line precharge transistors 11 to 14 are coupled to each bit line, and the bit line precharge transistors 11 to 14 form a bit line load circuit.

Reference numeral 1 is a main power supply line, that is, a power supply line supplied with a potential from a power supply pad, and is not particularly limited, and is formed of an aluminum wiring layer or the like. Memory cell power line 5
1, 52 are memory cell power supply lines 3 in the same block.
And a memory cell power line of another sub-block at the same time. Between the main power supply line 1 and the memory cell power supply line 3, a power supply disconnecting circuit 2 which is an electrically conducting means capable of cutting off power supply is provided.

A feature of the present invention is that the memory cell power supply lines 51 and 52 are bundled in sub-block units, the bundled line is used as the memory cell power supply line 3, and the memory cell power supply line 3 is disconnected from the power supply circuit. The configuration is such that it is connected to the main power supply line 1 via 2.

The sub-blocks 82 and 83 have the same structure as 81. It should be noted that this sub-block is a redundant switching unit. Therefore, for example, consider a case where the memory cell 21 has a defect in which a current flows through the memory cell power supply line 51. The sub-block 81 including the defective memory cell is replaced with the spare sub-block, and at the same time, the power supply disconnecting means 2 is turned off. By making the power supply disconnecting means 2 non-conductive, the power supplies of all the memory cells forming the unnecessary sub-block become floating, and the leak current path is cut off.

<Second Embodiment of Semiconductor Memory Device> A second embodiment of the semiconductor memory device of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing a part of the normal memory cell array 301 shown in FIG.

The structure of the sub blocks 81 to 83 will be described. The memory cell array portion includes a plurality of memory cells 21 to 24 arranged in a matrix, complementary bit lines 31 to 34 wired for each memory cell column, word lines 61 provided for each memory cell row, 62. The memory cells 21 to 24 are of static type.

Each bit line is provided with column gate transistors 41 to 44 for transferring data. Further, bit line precharge transistors 11 to 14 are coupled to each bit line. The main power supply line 1 is a power supply line supplied with a potential from a power supply pad, and is not particularly limited, but is formed of an aluminum wiring layer or the like.

The memory cell power supply lines 51 and 52 are commonly connected to the power supply line of the bit line load circuit composed of the memory cell power supply line and the transistors 11 to 14 which are electrically commonly connected in the same block. It is electrically commonly connected to the line 4 and at the same time is electrically separated from the memory cell power supply lines of other sub-blocks. A power supply line for supplying power to the bit line load circuit is also electrically commonly connected to the common connection line 4. A power supply disconnecting circuit 2 is provided between the main power supply line 1 and the common connection line 4.

A feature of the present invention is that the power supply lines for supplying the potentials to the memory cell power supply and the bit line load circuit are bundled in sub-block units, and the bundled common connection line 4 is separated by the means 2 for disconnecting the power supply line. It is configured to be connected to the main power supply line 1.

The sub-blocks 82 and 83 have the same structure as 81. It should be noted that this sub-block is a redundant switching unit. For example, the memory cell power line 5 may be connected to the memory cell 21.
Consider the case where there is a defect in which a current flows through 1. The sub-block 81 including the defective memory cell is replaced with the spare sub-block, and at the same time, the power supply disconnecting means 2 is turned off. By making the power supply disconnecting means 2 non-conductive, the power supply lines of all the memory cells forming the unnecessary sub-blocks and the power supply lines for supplying power to the bit line load circuits become floating, and the leak current path is cut off. .

<Regarding Power Supply Disconnecting Means><First Embodiment of Power Supply Disconnecting Means> Next, the power supply disconnecting means 2 which is means for disconnecting the power supply line will be described with reference to FIGS.
6 will be described. The power supply disconnecting means 2 includes a program circuit 110 including a fuse element and a switch circuit 111 controlled by the output of the program circuit.

First, a first embodiment of the power supply disconnecting means will be described with reference to FIG. The program circuit 110 is
Fuse elements 101 and 102 and P channel MOSF
A latch circuit 112 including an ET 103 and an N-channel MOSFET 104, and inverters 105 and 106
And a switch drive circuit. The switch circuit is composed of a P-channel MOSFET 107.

The fuses 101 and 10 of the latch circuit 112
The resistance value of 2 is sufficiently lower than the on resistance values of the P-channel MOSFET 103 and the N-channel MOSFET 104. With such a configuration, for example, when the fuse is not blown, the latch nodes 120 and 121 have a high level potential and a low level potential, respectively.

When there is no defect in the corresponding normal memory cell group, the fuses 101 and 102 are not cut. The node 121 becomes low potential, and the P-channel MOSFET1
The gate 122 of 07 is set to low potential. Therefore, the P-channel MOSFET 107 is turned on, and in the case of the first embodiment of the semiconductor memory device shown in FIG. 1, the power supply potential is supplied from the main power supply line 1 to the memory cell power supply line 3. In the case of the second embodiment of the semiconductor memory device shown in FIG. 2, the power supply potential is supplied from the main power supply line 1 to the common connection line 4. For convenience of explanation, the following description will be given using the case of the first embodiment of the semiconductor memory device. However, in the case of the second embodiment of the semiconductor memory device, the memory cell power supply line 3 is commonly connected. If the line 4 is replaced, the invention can be carried out in the same manner.

When there is a defect in the corresponding normal memory cell group, the fuses 101 and 102 are cut at the same time as the spare memory cell group is replaced as described above. The node 121 becomes a high level potential and the P channel MOSF
The gate 122 of the ET 107 has a high level potential. Therefore, the P-channel MOSFET 107 is turned off, and the potential supply from the main power supply line 1 to the memory cell power supply line 3 is cut off.

<Second Embodiment of Power Supply Disconnecting Means>
FIG. 4 shows a second embodiment of the power supply disconnecting means.
In this mode, an example in which the configuration of the program unit is simplified is shown. The program circuit 110 includes a resistor 109, a fuse 102, and switch driving inverters 105 and 106. The fuse 102 has a resistance value sufficiently lower than that of the resistance 109. For example, when the fuse is not blown, the node 121 has a low level potential.

When there is no defect in the corresponding normal memory cell group, the fuse 102 is not cut. The node 121 becomes a low level potential and the P-channel MOSFET 10
The gate 122 of No. 7 has a low level potential. Therefore P
The channel MOSFET 107 is turned on, and the power supply potential is supplied to the memory cell power supply line 3 from the main power supply line 1.

When there is a defect in the corresponding normal memory cell group, the fuse 102 is cut at the same time as the spare memory cell group is replaced as described above. The node 121 becomes a high level potential and the P-channel MOSFET 10
The gate 122 of No. 7 has a high level potential. Therefore P
The channel MOSFET 107 is turned off, and the potential supply from the main power supply line 1 to the memory cell power supply line 3 is cut off.

<Third Embodiment of Power Supply Disconnecting Means>
FIG. 5 shows a third embodiment of the power supply disconnecting means.
In this mode, the program circuit 110 is the same as that of FIG.
In this example, the transmission gate is composed of 07 and N-channel MOSFET 108. The operation of the program circuit 110 is the same as that of FIG.

When there is no defect in the corresponding normal memory cell group, the node 121 becomes low level potential,
The gate 122 of the P-channel MOSFET 107 has a low level potential, the gate 123 of the N-channel MOSFET 108 has a high level potential, and the P-channel MOSF
Both the ET 107 and the N-channel MOSFET 108 are turned on, and the power supply potential from the main power supply line 1 to the memory cell power supply line 3 is supplied.

When the relevant normal memory cell group is defective, the node 121 becomes high level potential, the gate 122 of the P-channel MOSFET 107 becomes high level potential, and the gate 123 of the N-channel MOSFET 108 becomes low level potential. P channel MO
Both the SFET 107 and the N-channel MOSFET 108 are turned off, and the power supply from the main power supply line 1 to the memory cell power supply line 3 is cut off.

By using the transmission gate, when the power is turned on or when the power supply is changed from a low voltage to a high voltage, the N-channel MOSFET 108 having a driving capability quickly raises the potential to (VDD-Vth), and then the comparison is made. P-channel MOSFET 1 with low dynamic drive capability
It is possible to raise it to VDD by 07. On the contrary, when the power supply voltage changes from a high voltage to a low voltage, it can be discharged mainly by the capable N-channel transistor 108. Note that VDD represents the potential of the main power supply, and Vth represents the threshold voltage of the transistor.

<Fourth Embodiment of Power Supply Disconnecting Means>
FIG. 6 shows a fourth embodiment of the power supply disconnecting means.
In this form, the program circuit 110 is the same as that in FIG. 4, and the switch circuit 111 is an example using a transmission gate as in FIG.

<Regarding Layout> Next, an embodiment relating to layout will be described with reference to FIG. 40
Reference numeral 0 is a normal memory cell area, and 404 is a redundant memory cell area. Reference numeral 403 is a word line drive circuit area. Bit line load circuit 401 (transistors 11 to 14 of FIG.
Is equivalent to ) Is provided adjacent to the normal memory cell region 400 and the redundant memory cell region 404, and the power supply disconnecting circuit 402 is provided adjacent to the bit line load circuit region 401. The feature of the present invention resides in that the normal memory cell region 400, the redundant memory cell region 404, the bit line load circuit region 401, the power supply disconnecting circuit region 4 are provided.
No. 02 is arranged adjacent to each other in this order. The redundant part does not need a power supply disconnecting circuit and is not provided.

FIG. 9 shows an embodiment of a layout relating to sub-blocks corresponding to 81 to 84 in FIG. 1 and the like. The sub-block 0 and the sub-block 1, which are redundant switching units, are composed of a memory cell array region 407 and a wiring region 406 that bundles the memory cell power supply lines arranged in the center or substantially the center of the sub-block. Further, a separation region 405 is provided between the sub blocks. By arranging the wiring region 406 in the center of the sub block, the current supply to the power supply lines of the left and right memory cell arrays is well balanced. In addition, a memory cell power line isolation region 405 is provided between the sub-blocks.

<Power Supply or Grounding Wiring><First Embodiment of Power Supply or Grounding Wiring> A first embodiment of the power supply or grounding wiring will be described with reference to FIG. In the present invention, the memory cell VSS line (ground line) 409 is electrically connected to the low resistance layer within the wiring region 406 of FIG. The memory cell power supply line 408 is connected to the common memory cell power supply (VDD) supply line 410 via a connection hole 413 that connects the memory cell power supply line 408 and the common memory cell power supply line 410. Further, the memory cell ground (VSS) line 409 is connected to the common memory cell ground (VSS).
The line 411 is connected via a connection hole 412 that connects the memory cell ground line 409 and the common memory cell ground line 411. By the way, the word line of the memory cell is connected to the wiring region 406.
However, it is omitted here because it does not directly relate to the present invention.

The semiconductor memory device is devised to lower the impedance of the VSS line in order to secure a low voltage operation margin. As one of them, a method of connecting the memory cell VSS line to a conductive layer having a low resistance to have a low impedance at regular intervals in the memory cell array (hereinafter, referred to as “VS”).
"S lined") is common. In this embodiment, the VSS lining also serves as the wiring region 406.

Further, in FIG. 10, the memory cell power supply line 408 and the common memory cell power supply line 410 are formed above the memory cell ground line 409 and the common memory cell ground line 411, or the memory cell power line 408 and the common The memory cell power supply line 410 is connected to the memory cell ground line 4
09 and the common memory cell ground line 411 may be formed in a lower layer. By adopting such a layer structure, FIG.
The layout can be performed without considering the distance L1 between the common memory cell power supply line 410 and the connection hole 412 or the distance L2 between the common memory cell ground line 411 and the connection hole 413 therein. That is, when the memory cell power supply line 408 and the common memory cell power supply line 410 are formed in a layer above the memory cell ground line 409 and the common memory cell ground line 411, the common memory cell ground line 411 is used as the common memory cell power supply line. It can be located under 410. Further, the memory cell power supply line 408 and the common memory cell power supply line 410 are connected to the memory cell ground line 409 and the common memory cell ground line 41.
When formed in a layer lower than 1, the common memory cell power supply line 410 can be arranged below the common memory cell ground line 411.

<Second Embodiment of Power Supply or Grounding Wiring> A second embodiment of the power supply or grounding wiring will be described with reference to FIG. FIG. 11 shows a potential of a P-type semiconductor region (hereinafter, referred to as “P well region” or “sub region”) having a relatively low impurity concentration in which a memory cell is formed in the wiring region 406 region. . Memory cell power line 4
08 is connected to the common memory cell power supply line 410 through a connection hole 413 that connects the memory cell power supply line 408 and the common memory cell power supply line 410. Further, in the P well region, a P-type semiconductor region (hereinafter, referred to as “P + st region”) 4 having a relatively high impurity concentration as compared with the P well is provided.
15 are provided, and the common memory cell ground line 411 to P +
A ground potential is supplied through a connection hole 414 that connects the st region 415 and the common memory cell ground line 411. In a semiconductor memory device, in order to prevent a back gate effect and a latch-up of a memory cell transistor, it is common to take a potential of a sub region at regular intervals in a memory cell array. In this embodiment, the wiring region 4 is used to drop the sub-potential.
It is configured to double within 06.

Further, in FIG. 11, the memory cell power supply line 40
8 and the common memory cell power supply line 410 may be formed above the common memory cell ground line 411. With such a configuration, the layout can be performed without worrying about the distance L3 between the common memory cell power supply lines 410 and 414 in FIG. That is, the common memory cell ground line 4
11 can be arranged below the common memory cell power supply line 410.

<Third Embodiment of Power Supply or Grounding Wiring> A third embodiment of the power supply or grounding wiring will be described with reference to FIG. FIG. 12 shows that the memory cell ground line 409 is electrically connected to the low resistance layer in the wiring region 406 and the sub potential is taken. Memory cell power line 40
8 is connected to the common memory cell power supply line 410 via a connection hole 413 that connects the memory cell power supply line 408 and the common memory cell power supply line 410. Further, the memory cell ground line 409 is connected to the common memory cell ground line 411 via a connection hole 412 that connects the memory cell ground line 409 and the common memory cell ground line 411. Furthermore, P
A P + st region 415 is provided in the well region, and the ground potential is supplied through the connection hole 414.

Further, as shown in FIG. 12, the memory cell power supply line 408 and the common memory cell power supply (VDD) supply line 4
10 may be formed in a layer above the memory cell ground line 409 and the common memory cell ground line 411. With such a configuration, the layout can be performed without worrying about L1 and L3 in FIG. That is, the common memory cell ground line 411 can be arranged below the common memory cell power supply line 410.

Further, in the embodiments of FIGS. 10 to 12, the common memory cell power supply line 410 and the common memory cell ground line 411 may be formed in different layers.

The sheet resistance of the common memory cell ground line 411 may be set lower than the sheet resistance of the common memory cell power supply line 410. Generally, in a static RAM, the resistance of the VSS line is an important factor that determines the low voltage operation margin, and by preferentially setting the resistance to the low resistance, the chip total performance is improved. On the other hand, a current flows through the memory cell VDD line (power supply line) upon returning from the retention mode, which is a general specification for static RAMs. For example, the node capacitance on one side of one memory cell is 20 fF, which are commonly connected. Even if the number of memory cells connected to the memory cell VDD line is 16384, in order to realize the recovery from retention of 5 ms, the resistance value of the commonly connected memory cell power supply line may be 15 MΩ or less. It's not as strict as the VSS line.

The common memory cell ground line 411 is made of a metal layer such as aluminum (hereinafter referred to as “AL”), and the common memory cell power supply line 410 is made of a polycrystalline silicon layer (hereinafter referred to as “polysilicon layer”). ) Or a polycrystalline silicon layer containing a refractory metal (hereinafter referred to as “polycide layer”). Since the commonly connected memory cell VDD line may have some resistance, it can be used also as a constituent layer of the memory cell by forming a polysilicon layer or a polycide layer.

<Fourth Embodiment of Power Supply or Grounding Wiring> A fourth embodiment of the power supply or grounding wiring will be described with reference to FIG. However, the following description does not relate to the inside of the wiring region 406 described above, but to the region of the inter-subblock separation region 405.

FIG. 14 shows an inter-subblock separation area 405.
The memory cell VSS line (ground line) is electrically connected to the low resistance layer in the region (1). The memory cell power supply lines 4 on the left and right of the sub-block in the sub-block separation region 405
08 are separated.

Further, the memory cell ground line 409 is connected to the common memory cell ground line 411 through a connection hole 412 connecting the memory cell ground line 409 and the common memory cell ground line 411. As described above, the semiconductor memory device is devised to lower the impedance of the VSS line in order to secure a low voltage operation margin. As one of them, it is general to line VSS at regular intervals in the memory cell array. In the present invention, the VSS lining is also used in the inter-subblock separation region 405.

<Fifth Embodiment of Power Supply or Grounding Wiring> A fifth embodiment of the power supply or grounding wiring will be described with reference to FIG. FIG. 15 shows a sub-block separation region 40.
The feature is that the potential of the P well region in which the memory cells are formed is taken within the 5 regions. In the inter-subblock isolation region 405, the memory cell power supply lines on the left and right of the subblock are isolated. In addition, a P + st region 415 is provided in the P well region, and the common memory cell ground line 411 to the P + st region 415 and the common memory cell ground line 411 are provided.
A ground potential is supplied through a connection hole 414 for connecting the.

As described above, in the semiconductor memory device, in order to prevent the back gate effect and the latch-up of the memory cell transistor, it is common to take the potential of the sub-region at regular intervals in the memory cell array. In the present invention, lowering the sub-potential is performed by the sub-block separation region 40.
It is configured so that it can be combined within 5.

<Sixth Embodiment of Power Supply or Grounding Wiring> A sixth embodiment of the power supply or grounding wiring will be described with reference to FIG. FIG. 16 shows an inter-subblock separation region 40.
The memory cell VSS line is electrically connected to the low resistance layer and the sub potential is taken in the five regions. In the inter-subblock isolation region 405, the memory cell power supply lines 408 on the left and right of the subblock are isolated. By adopting such a layout, the present invention can be easily implemented.

Further, the memory cell ground line 409 is connected to the common memory cell ground line 411 through a connection hole 412 connecting the memory cell ground line 409 and the common memory cell ground line 411. Furthermore, in the P well region, P + st
A region is provided and the ground potential is supplied through the connection hole 414.

<Regarding Memory Cell> In the static RAM for explaining the embodiment of the memory cell, a method of using a driving N-channel MOS transistor and a complementary P-channel MOS transistor as a load transistor is a method of realizing a low voltage operation. is there. Especially recently
A memory cell using a P-channel thin film transistor (hereinafter referred to as “TFT”) has come to be generally used due to its advantage of high integration.

The present invention has a static memory cell using a TFT memory cell load, and the common memory cell power supply line 410 is formed in the same layer as the gate electrode of the TFT.

FIG. 13 shows an example of a static type memory cell using a TFT memory cell load. FIG. 13A is a diagram showing a configuration of a transfer MOS transistor and a drive MOS transistor, and FIG. 13B is a diagram showing T of a memory cell load.
FIG. 3 is a diagram illustrating a configuration of an FT.

First, FIG. 13A will be described. An active field (hereinafter referred to as “F”) 500 and a first polysilicon layer or a polycide layer (hereinafter, referred to as “F”)
510 and 511 (referred to as “PLYA”) form the transfer MOS transistors T1 and T2 and the drive MOS transistors T3 and T4. The word line 530 is a second polysilicon layer or polycide layer (hereinafter,
"PLYB"), and the gate electrode of the transfer MOS transistor has a connection hole (hereinafter, referred to as "THL") for connecting PLYB and PLYA or PLYB and F.
"A"). The memory cell ground line 531 is made of PLYB like the word line 530, and is connected to F through the THLA 521. The connection between the storage node and the gate of the reverse-side inverter forming the flip-flop is performed by connecting the third polysilicon layer or polycide layer (hereinafter referred to as “PLYC”) to F or P.
It is performed using a connection hole (hereinafter, referred to as “THLB”) 540 that connects with LYA.

Next, FIG. 13B will be described. The N-type PLYC and the fourth polysilicon layer (hereinafter, "PL
560 (referred to as YD) and TFTs T5 and T6 are formed. Gate PLYC of T5 and drain P of T6
The LYD connection is made by connecting the PLYC and PLYD connection holes (hereinafter,
570 (referred to as “THLC”). Note that P
By selectively doping P-type impurities into LYD, T
The source and drain of FT and VDD wiring are formed.

The layers constituting the common memory cell power supply line 410 in FIG. 10 are PLYA and PLY.
Four layers of B, PLYC and PLYD can be considered. PLYD
Usually has a sheet resistance of several tens of KΩ and its high impedance makes it less preferable for use as a common memory cell power supply line. Since PLYB is used as a word line and a memory cell VSS supply line, it is wired in a direction perpendicular to the common memory cell power supply line 410. Therefore PLYB
Cannot be used because PLYB is short-circuited when it is used as a common memory cell power supply line. In addition, as shown in FIG. 13a) of the memory cell, the semi-broken contact and F, PLYA generated at the end of the memory cell array are
Since the processing must be performed within the 06 area, F and PLYA bite into this area and are laid out. Therefore, it is not preferable to avoid this and configure the common memory cell power supply line 410 with PLYA because the area of the wiring region 406 becomes large. In that respect, PLYC (TFT gate layer) has the above-mentioned PLYA, PLYB, and PLYC.
Therefore, it can be said that it is a layer suitable for the common memory cell power supply line 410 without any problems as in the case of using.

In the memory cell shown in FIG. 13, since the source, drain and gate electrodes of the bulk transistor are formed of an N-type impurity layer having a relatively high concentration, formation of a diode in the contact region with PLYC is prevented. PLYC needs to be N-type (the conductivity type of PLYC of the memory cell needs to be N-type). When the common memory cell power supply line (PLYC) 410 is an N-type which has the same conductivity type as the memory cell, the common memory cell power supply line (PLYC) 410 and the P-type VDD wiring (PLY)
D) A PN diode is formed at the connection portion 413 of 408. Since this diode is parasitic on the VDD line of the memory cell in series, the effective power supply voltage of the memory cell drops, and in particular, the retention voltage rises. The present invention avoids this parasitic diode, and is characterized in that the memory cell PLYC is selectively formed into an N type and the common memory cell power supply line 410PLYC is selectively formed into a P type. Selective impurity implantation can be easily realized by adding two photo processes and one ion implantation process.

[0106]

As described above, according to the present invention, the current defect of the semiconductor memory device can be relieved and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a second embodiment of a semiconductor memory device of the present invention.

FIG. 3 is a diagram showing a first embodiment of a power supply disconnecting circuit of the present invention.

FIG. 4 is a diagram showing a second embodiment of a power supply disconnecting circuit of the present invention.

FIG. 5 is a diagram showing a third embodiment of a power supply disconnecting circuit of the present invention.

FIG. 6 is a diagram showing a fourth embodiment of a power supply disconnecting circuit of the present invention.

FIG. 7 is a block diagram of a part of the semiconductor memory device of the present invention.

FIG. 8 is a layout diagram of the semiconductor memory device of the present invention.

FIG. 9 is a layout diagram of sub-blocks in the semiconductor memory device of the present invention.

FIG. 10 is a diagram showing a first embodiment of a power supply or ground wiring of a semiconductor memory device of the present invention.

FIG. 11 is a diagram showing a second embodiment of the power supply or ground wiring of the semiconductor memory device of the present invention.

FIG. 12 is a diagram showing a third embodiment of the power supply or ground wiring of the semiconductor memory device of the present invention.

FIG. 13 is a diagram showing an embodiment of a memory cell of a semiconductor memory device of the present invention.

FIG. 14 is a diagram showing a fourth embodiment of the power supply or ground wiring of the semiconductor memory device of the present invention.

FIG. 15 is a diagram showing a fifth embodiment of the power supply or ground wiring of the semiconductor memory device of the present invention.

FIG. 16 is a diagram showing a sixth embodiment of the power supply or ground wiring of the semiconductor memory device of the present invention.

FIG. 17 is a diagram showing a first conventional example according to the present invention.

FIG. 18 is a diagram showing a second conventional example according to the present invention.

[Explanation of symbols]

1 ... Main power supply wiring 2, 201-204 ... Power supply disconnecting means 3 ... Memory cell power supply line 4 ... Common connection line 11-14 ... Bit line precharge transistors 21-24 ... -Memory cell transistors 31-34 ... Bit lines 41-44 ... Column gate transistors 51, 52 ... Memory cell power supply lines 61, 62 ... Word lines 81-84 ... Sub-blocks 101, 102・ ・ ・ Fuse 103 ・ ・ ・ P channel MOSFET 104 ・ ・ ・ N channel MOSFET 105, 106 ・ ・ ・ Inverter 107 ・ ・ ・ P channel MOSFET 108 ・ ・ ・ N channel MOSFET 110 ・ ・ ・ Program circuit 111 ・ ・ ・ Switch Circuit 112 ... Latch circuit 120-123 ... node 301 ... normal memory cell array 302 ... normal decoder 303 ... address buffer 304 ... spare memory cell array 305 ... spare decoder 306 ... spare program circuit 400 ... normal memory cell Area 401 ・ ・ ・ Bit line load circuit area 402 ・ ・ ・ Power supply disconnection circuit area 403 ・ ・ ・ Word line drive circuit area 404 ・ ・ ・ Redundant memory cell area 405 ・ ・ ・ Sub-block separation area 406 ・ ・ ・ Common memory Cell power supply line wiring area 407 ... Memory cell array area 408 ... Memory cell power supply line 409 ... Memory cell ground (VSS) line 410 ... Common memory cell power supply (VD
D) Supply line 411 ... Common memory cell ground line 412 ... First connection hole for connecting memory cell ground line and common memory cell ground line 413 ... Memory cell power line and common memory cell power supply Second connection hole for connecting line to the line L1 ... Distance between first connection hole and common memory cell power supply line 414 ... Third for connecting high-concentration sub-diffusion region to common memory cell ground line Connection hole 415 ・ ・ ・ High-concentration sub-diffusion region L2 ・ ・ ・ Distance between third connection hole and common memory cell power supply line 500 ・ ・ ・ Active field region 510,511 ・ ・ ・ First layer poly Silicon or polycide layer (PLYA) 520, 521 ... Connection hole for connecting first layer polysilicon or polycide layer and second layer polysilicon or polycide layer THLA) 530, 531 ・ ・ ・ First layer polysilicon or polycide layer (PLYB) 540 ・ ・ ・ Third layer polysilicon or polycide layer and active field region or first layer polysilicon or polycide Connection holes for connecting layers (THLB) T1, T2 ... Transfer MOS transistor T3, T4 ... Drive MOS transistor 550 ... Bit line contact 560 ... Third layer polysilicon or polycide layer 570 ... Connection holes (THL) for connecting the fourth polysilicon layer and the third polysilicon or polycide layer
C) 580 ... Fourth polysilicon layer T5, T6 ... Thin film transistor (TFT)

Claims (20)

[Claims] 1. A plurality of normal memory cell groups in which a plurality of memory cells are arranged in a matrix, and a spare memory cell group,
In a semiconductor memory device having means for switching to the spare memory cell group in units of the normal memory cell group, a memory cell power supply line is electrically commonly connected for each normal memory cell group, and between the normal memory cell groups. Means for electrically separating the memory cell power supply line, and further for electrically disconnecting the memory cell power supply line provided for each of the normal memory cell groups and the power supply line to which the potential is supplied from the power supply pad are provided. And semiconductor memory device. 2. The semiconductor memory device according to claim 1,
A bit line load circuit power supply line for supplying power to a plurality of bit line load circuits is electrically commonly connected to the memory cell power supply line provided for each of the normal memory cell groups, and the normal memory cells are connected. A memory cell power supply line provided for each group and a common connection line with a bit line load circuit power supply line for supplying power to the plurality of bit line load circuits and a power line supplied with a potential from a power pad are electrically connected. A semiconductor memory device characterized by comprising means for mechanically separating. 3. The semiconductor memory device according to claim 1, wherein the disconnecting means includes a program circuit including a fuse element and a switch circuit controlled by the output of the program circuit. A semiconductor memory device characterized by: 4. The semiconductor memory device according to claim 3, wherein
A semiconductor memory device, wherein the switch circuit includes a transmission gate formed by connecting a transistor of a first conductivity type and a transistor of a second conductivity type in parallel. 5. A plurality of normal memory cell groups in which a plurality of memory cells are arranged in a matrix, and a spare memory cell group,
A semiconductor memory device having means for switching to a spare memory cell group in units of the normal memory cell group, wherein a memory cell power supply line is electrically commonly connected for each normal memory cell group, and between the normal memory cell groups. And a means for electrically separating the memory cell power supply line with each other, and electrically disconnecting the memory cell power supply line provided for each of the regular memory cell groups and the power supply line supplied with a potential from the power supply pad. A memory device or a bit line load circuit power supply line for supplying power to the bit line load circuit for each of the regular memory cell groups is electrically connected in common, and further, a power line supplied with a potential from a power pad is electrically connected. A semiconductor memory device provided with means for electrically separating, or a memory cell power supply line provided for each of the normal memory cell groups, and a plurality of bit line load circuits. Bit line power supply lines for supplying a power source are electrically commonly connected, and a memory cell power supply line provided for each normal memory cell group and a bit line load for supplying power to a plurality of bit line load circuits In a semiconductor memory device comprising means for electrically disconnecting a common connection line with a circuit power supply line and a power supply line supplied with a potential from a power supply pad, the memory cell group, the bit line load circuit group, and the power supply disconnection A semiconductor memory device characterized by being arranged adjacent to each other in the order of circuit groups. 6. The semiconductor memory device according to claim 1, wherein
A first area for electrically commonly connecting the memory cell power supply lines is provided at the center or substantially the center of the normal memory cell group, and a second area for separating the memory cell power supply line is further provided between the normal memory cell groups. A semiconductor memory device characterized by being provided. 7. The semiconductor memory device according to claim 6,
A semiconductor memory device, wherein in the first region, the memory cell ground line is electrically commonly connected to a ground line having a resistance lower than that of the memory cell ground line. 8. The semiconductor memory device according to claim 6,
A semiconductor memory device, wherein a sub-potential of a memory cell region is applied within the first region. 9. The semiconductor memory device according to claim 6, wherein
In the first region, the memory cell ground line is electrically commonly connected to a ground line having a lower resistance than the memory cell ground line, and
A semiconductor memory device characterized by applying a potential of a well region in which a memory cell is formed. 10. The semiconductor memory device according to claim 7, wherein the memory cell power supply line and the memory cell power supply line provided for each memory cell group are in the memory cell ground line and the first region. The memory cell ground line is electrically connected in common to the ground line having a lower resistance than the memory cell ground line and a conductive layer in an upper layer, or is provided for each memory cell power line and each memory cell group. The memory cell power supply line, the memory cell ground line and a ground line having a lower resistance than the memory cell ground line in which the memory cell ground line is electrically commonly connected in the first region, and a lower conductive layer. A semiconductor memory device comprising: 11. The semiconductor memory device according to claim 8, wherein said memory cell power supply line and said memory cell power supply line provided for each memory cell group are said memory cell ground line in said first region. A semiconductor memory device comprising a ground line having a resistance lower than that of a memory cell ground line electrically connected in common and a conductive layer in an upper layer. 12. The semiconductor memory device according to claim 9, wherein the memory cell power supply line and the memory cell power supply line provided for each memory cell group are within the first region and the memory cell ground line. A semiconductor memory device comprising: a ground line having a resistance lower than that of a memory cell ground line in which memory cell ground lines are electrically commonly connected; and a conductive layer in an upper layer. 13. The semiconductor memory device according to claim 7, 8 or 9, wherein a memory cell power supply line provided for each memory cell group and a memory cell ground line are electrically connected in said first region. A semiconductor memory device, wherein a ground line having a resistance lower than that of a commonly connected memory cell ground line is formed of a different conductive layer. 14. The semiconductor memory device according to claim 13, wherein the sheet resistance value of the ground line having a lower resistance than that of the memory cell ground line electrically connected to the memory cell ground line in the first region is a memory. A semiconductor memory device having a sheet resistance value smaller than a sheet resistance value of a memory cell power supply line provided for each cell group. 15. The semiconductor memory device according to claim 14, wherein a ground line having a resistance lower than that of the memory cell ground line electrically connecting the memory cell ground lines in the first region is a metal layer. A semiconductor memory device, wherein a memory cell power supply line provided for each memory cell group is a polycrystalline silicon layer or a polycrystalline silicon layer containing a refractory metal. 16. The semiconductor memory device according to claim 15, further comprising a static memory cell using a thin film transistor as a load, wherein a memory cell power supply line provided for each memory cell group is provided. A semiconductor memory device, which is formed of the same conductive layer as a conductive layer forming a gate electrode of the thin film transistor. 17. The semiconductor memory device according to claim 16, wherein the thin film transistor has a source electrode and a drain electrode of a first conductivity type, and a gate has a memory cell of a second conductivity type. A semiconductor memory device, wherein a memory cell power supply line provided for each memory cell group is composed of a second conductivity type polycrystalline silicon layer. 18. The semiconductor memory device according to claim 6, wherein in the second region, the memory cell ground line is electrically commonly connected to a ground line having a resistance lower than that of the memory cell ground line. Semiconductor memory device. 19. The semiconductor memory device according to claim 6, wherein a sub-potential of the memory cell region is applied within the second region. 20. The semiconductor memory device according to claim 6, wherein in the second region, the memory cell ground line is electrically connected in common to a ground line having a resistance lower than that of the memory cell ground line. A semiconductor memory device characterized by applying a sub-potential of a region.