JPH11186495A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a required current quantity only by changing a single contact mask. SOLUTION: Related to a field effect transistor, a contact hole 4b is not allocated in the entire active region 1, however, a wiring layer 5b covers the entire active region 1. At first, the contact holes 4b are allocated in numbers about half of allocatable numbers as shown in (A), however, if a current value is required to be changed, or if a current is required to be reduced, the number of contact holes 4b is reduced as shown in (B). If increase is required, the number of contact holes 4b is increased as shown in (C), thus, with no change of wiring layer, only the allocation number of the contact holes 4b is changed to adjust current quantity of the field effect transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of changing a current amount.

[0002]

2. Description of the Related Art Conventionally, in order to obtain an optimum current for a field effect transistor in terms of circuit operation, the connection is changed to a field effect transistor having a different size prepared in advance, or a mask as shown in FIG. Is optimized by changing the size of the field-effect transistor by changing all the parameters. 5 is a plan view showing the structure of a field-effect transistor in a conventional semiconductor device. In FIG. 5, 1 is an active region, 2 is an element isolation region,
3 gate electrodes, 4a and 4b are contact holes, and 5a and 5b are wiring layers.

When a field effect transistor having the size shown in FIG. 5A is used to obtain an optimum current in terms of circuit operation, when reducing the current, the mask is changed as shown in FIG. In order to reduce the size and reduce the number of contact holes 4a and 4b from five to three in the example shown in the figure, and to increase the current, the mask is changed as shown in FIG. The number of contact holes 4a and 4b is increased from five to seven in the illustrated example.

[0004]

However, when the connection is changed to a field-effect transistor of a different size prepared in advance as in the former case, extra space is required, and high integration of the element is required. Not suitable.
Changing the size of the field-effect transistor by changing all the masks as in the latter case increases the labor and cost of recreating the mask. Further, there is a problem that a change in the size of the field-effect transistor changes a junction capacitance and a gate capacitance of parameters that affect circuit operation.

The present invention solves the above-mentioned conventional problems. The current amount can be changed without changing the capacitance parameter because the size of the field-effect transistor is not changed by changing only one contact mask. It is an object of the present invention to provide a semiconductor device that can change the value.

[0006]

In order to achieve the above object, the present invention provides a MOS type semiconductor device in which one side is provided on both sides of a gate electrode provided on a conductive type semiconductor substrate via a gate insulating film. A conductive type source / drain region, a wiring layer provided on the source / drain region via an insulating film so as to cover all the source / drain region, and the source / drain region; At least one contact hole connecting the region and the wiring layer is provided in each of the source and drain regions.
At least one of the drain regions is extended in a direction perpendicular to the gate electrode, and the arrangement of the contact holes is adjusted so as to obtain a desired current value.

According to the present invention, a semiconductor device can be obtained in which a required amount of current can be obtained by changing only one contact mask.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. It is to be noted that the same reference numerals are used for parts corresponding to the above-described conventional one.

(First Embodiment) FIG. 1 is a plan view showing a structure of a field effect transistor according to a first embodiment of the present invention. Here, active region 1, element isolation region 2, gate electrode 3, contact holes 4a and 4b, metal wiring layer 5
a and 5b are provided. In the present embodiment, the drain side contact hole 4a connected to a high bias is arranged in the drain region in parallel with the gate electrode 3. The number of the contact holes 4b on the source side is arranged in parallel with the gate electrode 3 in one of the source regions so as to obtain a desired current.

That is, the contact hole 4b is formed in the active region 1
Are not arranged in all the wiring layers 5b, but the active layer 1
To cover the whole of Initially, as shown in FIG. 1 (A), about half of the number of contact holes 4b can be arranged, and when the current value needs to be changed or when the current needs to be reduced, the arrangement shown in FIG. Thus, the number of contact holes 4b is reduced. When it is necessary to increase the number of contact holes 4b as shown in FIG.

As described above, according to this embodiment, the current amount of the field effect transistor can be adjusted by changing only the number of contact holes without changing the wiring layer. Although the case of adjusting the contact holes 4b has been described as an example, the number of the contact holes 4b is the same as the number of the contact holes 4a. Adjustments are possible.

That is, the source-side contact holes 4b connected to the low bias are arranged uniformly in the drain region in parallel with the gate electrode 3. Drain side contact hole 4
The number a is arranged in parallel with the gate electrode 3 in one of the drain regions so as to obtain a desired power supply. That is, the positions of the contact holes 4a and 4b shown on the right and left sides of FIG.

(Embodiment 2) FIG. 2 is a plan view showing a structure of a field effect transistor according to Embodiment 2 of the present invention. Initially, as shown in FIG. 2 (A), about half of the number in which the contact holes 4b can be arranged is arranged, and when it is necessary to change the current value, and when it is necessary to reduce the electric current, Thus, the number of contact holes 4a is reduced. If it is necessary to increase the number, the number of contact holes 4b is increased as shown in FIG. The contact holes 4a, 4b are not changed in the wiring layers 5a, 5b.
The amount of current of the field effect transistor can be adjusted only by changing the number of arrangements.

As described above, according to the present embodiment, the current amount of the field effect transistor can be adjusted by changing only the number of contact holes without changing the wiring layer.

(Embodiment 3) FIG. 3 is a plan view showing a structure of a field effect transistor according to Embodiment 3 of the present invention. Initially, as shown in FIG. 3A, one of the active regions 1 is formed in an L-shape, and the wiring layers 5a and 5c are arranged so as to entirely cover the active region 2, and are arranged in a direction perpendicular to the gate electrode 3. A contact hole 4c is arranged in the vicinity of the center of the active region 1 extending in the lateral direction (in the horizontal direction in the drawing), and when the current value needs to be changed or when the current needs to be reduced, as shown in FIG. The position of the contact hole 4c is moved to a side far from the gate electrode 3. If it is necessary to increase the number, the position of the contact hole 4c is brought closer to the gate electrode 3 as shown in FIG. Wiring layer 5
The current amount of the field effect transistor can be adjusted by changing only the arrangement position of the contact hole 4c without changing a and 5c.

As described above, according to the present embodiment, the current amount of the field effect transistor can be adjusted by changing only the arrangement position of the contact hole without changing the wiring layer.
The L-shaped active region may be formed on both sides of the gate electrode.

The impurity concentration of the L-shaped active region is 1 ×
By setting the resistance to 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , the effect can be increased by increasing the resistance value.

(Embodiment 4) FIG. 4 is a plan view showing a structure of a field effect transistor according to Embodiment 4 of the present invention. Initially, as shown in FIG. 4A, one of the active regions 1 is formed in a T-shape, and the wiring layers 5a and 5c are arranged so as to cover all the active regions.
A contact hole 4c is arranged in the vicinity of the center of the active region 1 extending in the lateral direction (in the drawing), and when the current value needs to be changed or when the current needs to be reduced, as shown in FIG. The position of the contact hole 4c is moved to a side far from the gate electrode 3. When it is necessary to increase the number, the position of the contact hole 4c is brought closer to the gate electrode as shown in FIG. Wiring layers 5a, 5
The current amount of the field effect transistor can be adjusted by changing only the arrangement position of the contact hole 4c without changing c.

As described above, according to the present embodiment, the current amount of the transistor can be adjusted by changing only the arrangement position of the contact hole without changing the wiring layer. Note that T
The active region may be formed in a letter shape on both sides of the gate electrode.

The impurity concentration of the T-shaped active region is 1 ×
By setting the resistance to 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , the effect can be increased by increasing the resistance value.

[0021]

As described above, according to the present invention, it is possible to obtain a semiconductor device which satisfies the required charge retention characteristics by controlling the impurity distribution in the semiconductor substrate, has little deterioration over time, and has high long-term reliability. Can be

[Brief description of the drawings]

FIG. 1 is a plan view showing a structure of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a structure of a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a plan view showing a structure of a field-effect transistor according to a third embodiment of the present invention.

FIG. 4 is a plan view showing a structure of a field-effect transistor according to a fourth embodiment of the present invention.

FIG. 5 is a plan view showing a structure of a field-effect transistor in a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Active region 2 Element isolation region 3 Gate electrode 4a, 4b, 4c Contact hole 5a, 5b, 5c Metal wiring layer

Claims (8)

[Claims] An MOS type semiconductor device has a source and drain region of the other conductivity type provided on both sides of a gate electrode provided on a semiconductor substrate of one conductivity type with a gate insulating film interposed therebetween. A wiring layer provided via an insulating film is provided so as to cover all of the source and drain regions, and a contact hole connecting the source and drain regions and the wiring layer has a source and a drain. A semiconductor device comprising at least one drain provided in each region of a drain. 2. A drain side contact hole connected to a high bias is uniformly arranged in a drain region in parallel with a gate electrode, and a source side contact hole is desirably formed in one of a source region in parallel with a gate electrode. 2. The semiconductor device according to claim 1, wherein the number of the contact holes is adjusted so as to obtain the current. 3. A source-side contact hole connected to a low bias is uniformly arranged in the drain region in parallel with the gate electrode, and the drain-side contact hole is desirably formed in one of the drain regions in parallel with the gate electrode. 2. The semiconductor device according to claim 1, wherein the number of the contact holes is adjusted so as to obtain the current. 4. A drain side contact hole connected to a high bias and a source side contact hole connected to a low bias are contacted in parallel with the gate electrode so that a desired current is obtained in each of the source and drain regions. 2. The semiconductor device according to claim 1, wherein the number of holes is adjusted and arranged. 5. A MOS type semiconductor device having a source and drain region of the other conductivity type provided on both sides of a gate electrode provided on a semiconductor substrate of one conductivity type with a gate insulating film interposed therebetween. A wiring layer provided via an insulating film is provided so as to cover all of the source and drain regions, and a contact hole connecting the source and drain regions and the wiring layer has a source and a drain. At least one is provided in each region of the drain, and at least one of the source and drain regions is extended in a direction perpendicular to the gate electrode, and the arrangement of the contact holes is adjusted so as to obtain a desired current value. Semiconductor device. 6. A source extending in a direction perpendicular to the gate electrode,
The drain region is L-shaped.
13. The semiconductor device according to claim 1. 7. A source extending in a direction perpendicular to the gate electrode,
The drain region has a T-shape.
13. The semiconductor device according to claim 1. 8. The method according to claim 6, wherein the impurity concentration of the source and drain regions expanded into an L-shape and a T-shape is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ^3. Semiconductor device.