JPH1117711A - Serial interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit/receive the data of a large capacitance with a packet corresponding to a prescribed standard and to enable error discrimination by generating a request packet from a present node to the other node, sending it to a serial interface bus, performing receiving processing to the packet of a response to the request packet and discriminating the presence/absence of error in the received response packet. SOLUTION: A transaction controller discriminates the presence/absence of error in the response packet and when there is an error, an error discrimination circuit 1261 is provided for discriminating the contents of the error. When the presence of error in the response packet is detected, the error discrimination circuit 1261 outputs a signal to a request packet generating circuit, a response packet circuit an FIFO for request and a packet for response and stops the processing of them. Then, an error code corresponding to the contents of the error is set to the error register of a control register CR and when the presence of error is detected, an interruption pit is set to the CR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital serial interface circuit, and more particularly to a hard disk drive (HDD).
Drive), DVD (Digital Video Disk) -ROM, CD
(Compact Disk)-ROM, Tape Streamer
amer) or the like for a serial interface circuit connected to a storage device.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

In the data transfer of the IEEE 1394 serial interface, a transfer operation performed in a network is called a subaction, and two subactions are defined. One is conventional Request, Acknow
Asynchronous (Asynch) for requesting and confirming receipt of ledge
ronous) forwarding, and the other is 125
Isochronous (Isoch) where data is always sent once every μs
ronous) Transfer.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Although transfer is performed in packet units, in the IEEE 1394 standard, the minimum data unit handled is one quadlet (q
uadlet) (= 4 bytes = 32 bits).

[0005] In the IEEE1394 standard, computer data is usually transmitted using asynchronous transfer as shown in FIG. Asynchronous transfer is shown in FIG.
As shown in (a), there are three transition states: arbitration (arb) for acquiring a bus, packet transmission for transferring data, and acknowledgment (ack).

The execution of packet transmission is performed in a format as shown in FIG. The first quadlet of the transfer packet includes a 16-bit destination ID (destination ID) area and a 6-bit transaction label tl (transaction label).
l) area, 2-bit retry code rt (retry cod
e) area, 4-bit transaction code tcod
An e (transanction code) area and a 4-bit priority pri (priority) area. The destination ID area indicates the bus number and node number of this node, and the priority area indicates the priority level.

[0007] The second and third quadlets have a 16-bit source ID area and a 48-bit destination offset (destina- tion).
tionoffset) region. The source ID area shows the ID of the node that sent this packet, and the destination offset area shows high (High) and low (L
ow), and indicates the address of the destination node address space.

[0008] The fourth quadlet is composed of a 16-bit data length area and a 16-bit extended transaction code (extended tcode) area. The data length field indicates the number of bytes of the received packet, and the extended tcode field is tc.
mode is a Lock transaction
If, the actual locking action performed by the data in this packet
(Lock Action).

[0009] A header CRC (header CRC) added to the quadlet before the data field area (data field)
The area is an error detection code of the packet header. Also,
A data CRC (data CRC) area added to the quadlet after the data area (data field) is an error detection code of the data field.

[0010]

As described above, in the normal computer data transfer performed by the asynchronous transfer, the SBP-based protocol is used as the protocol.
2 (Serial Bus Protocol-2) is used. According to this protocol, a host device (Host) is transferred from a target (Target) that is a storage device.
When transferring data to the initiator, which is a Computer, the data is written from the storage device to the memory of the host computer, and when transferring the data from the host computer to the target,
The transfer is performed in such a manner that the storage device reads the data in the memory of the host computer.

However, a processing circuit system for controlling a so-called transaction layer for transmitting and receiving a large amount of data stored in or read from the storage device in packets of the IEEE 1394 standard. Has not yet been established. It is also necessary to implement a circuit for detecting and determining a communication error in the transaction system.

The present invention has been made in view of the above circumstances, and has as its object to transmit and receive a large amount of data in packets conforming to a predetermined standard, and to provide a method for transmitting and receiving data when an error occurs. Another object of the present invention is to provide a serial interface circuit capable of performing such a determination and performing a smooth transmission / reception process.

[0013]

In order to achieve the above object, the present invention relates to a serial interface circuit for transmitting and receiving a packet between another node connected to the own node via a serial interface bus. A data processing circuit that generates a request packet to the other node from and transmits the request packet to the serial interface bus, and performs a reception process on a response packet to the request packet;
Determine whether there is an error in the received response packet,
When there is an error, an error determining circuit for determining the content of the error is provided.

In the present invention, when the error detection circuit detects an error, it stops the packet transmission / reception processing of the data processing circuit.

Further, according to the present invention, an error register is provided, and when the error is detected, the error discriminating circuit sets the content of the error in the error register.

Further, the present invention has a control circuit for initializing the data processing circuit when an error content is set in the error register.

In the present invention, when the error discriminating circuit detects an error, the error discriminating circuit informs the control circuit that the error has been detected, and the control circuit reads the error register in response to the error detection, The above initialization processing is performed.

Further, according to the circuit of the present invention, in the data processing circuit, a request packet from the own node to another node is generated and transmitted to the serial interface bus. Then, a response packet to the request packet from the other node is received and a predetermined process is performed. Further, the response packet is also input to the error determination circuit. The error discriminating circuit detects whether or not the received response packet has an error, and if there is an error, discriminates the content of the error. For example, when an error is detected by the error discriminating circuit, the packet transmission / reception processing of the data processing circuit is stopped, the content of the error is set in the error register, and the control circuit is notified that the error has been detected. You. That is, an error interrupt is performed. When the control circuit receives the notification of the error detection, the content of the error register is read, and the initialization processing for the data processing circuit is performed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an IEEE 1 according to the present invention.
FIG. 3 is a block diagram illustrating an embodiment of a 394 serial interface circuit. This serial interface circuit is configured to transfer computer data handled in asynchronous communication. Therefore, FIG. 1 does not show a specific configuration of the isochronous communication system circuit.

This serial interface circuit includes a link / transaction layer integrated circuit 10, a physical layer circuit 20, a hard disk driver (HDD) controller 30 (not shown) as a storage device, and a local processor 40 as a host computer. I have.

The link / transaction layer integrated circuit 10 is formed by integrating the link layer circuit 100 and the transaction layer circuit 120, and controls the asynchronous transfer under the control of the local processor 40 and the physical layer circuit. 20.

As shown in FIG. 1, a link layer circuit 100 includes a link core (Link Core) 101, a CPU interface circuit (Sub-CPU I / F) 102, and a transmission FIFO (AT-AT) used for asynchronous communication. FIFO: First-In F
irst-Out) 103, receiving FIFO (AR-FIFO) 104,
Classification circuit (DeMux) 105 for discriminating received packets, resolver for self ID (Resolver) 106, and control register (ControlRegisters, hereinafter referred to as CR) 1
07.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets to which commands and computer data are transferred, and a physical layer circuit 20 for directly driving these packets on the IEEE 1394 serial bus BS. It is composed of an interface circuit, a cycle timer reset every 125 μs, a cycle monitor and a CRC circuit. Further, it performs a transmission process of computer data read from a hard disk (not shown) and generated by the transaction layer circuit 120 as a predetermined transmission packet. For example, a transaction controller 1 of a transaction layer circuit 120 described later
Upon receiving a notification that there is data to be sent from 26, the 1394 serial bus is arbitrated via the physical layer circuit 20 to secure the bus. In FIG. 1, the FIFO and the like of the isochronous communication system are omitted as described above.

The CPU interface circuit 102 includes a local processor 40, a transmission FIFO 103, and a reception FIFO.
It performs arbitration such as writing and reading of asynchronous communication packets with the IFO 104 and arbitration of transmission and reception of various data between the local processor 40 and the CR 107. For example, a host computer as an initiator transmits an IEEE 1394 interface bus BS, and transmits a command for controlling a hard disk as a storage device stored in a reception FIFO to the local processor 40.

From the local processor 40, data for activating the transaction layer circuit 120 for transmitting and receiving computer data is set in the CR 107 through the CPU interface 102 (ADPst).
= 1).

The transmission FIFO 103 includes IEEE13
Asynchronous communication packets to be transmitted to the N. 94 serial bus BS are stored.
Given to.

The receiving FIFO 104 is based on the IEEE standard.
Asynchronous communication packets transmitted through the 1394 serial bus BS, for example, commands for controlling a hard disk as a storage device and the like are stored by the classification circuit 105.

The discrimination circuit 105 has a transaction code tcode (Transaction) in the first quadred of the asynchronous communication packet via the link core 101.
code) and transaction label tl (Transaction
label), discriminates whether the packet is a response packet (Response Packet) from the initiator host computer to the target transaction layer circuit or other packets, and only the response packet is transferred to the transaction layer circuit. The packet is input to the circuit 120, and the other packets are stored in the reception FIFO 104.

The transaction label tl used for sorting check is set to "a" in common, and t
In the code (Transaction code), different data is set for a write request (request) and response (Response), and for a read (Read) request (Read request) and response (Read Response). Specifically, tcode
Is set to "0" in the case of a quadlet write in a write request and "1" in the case of a block write.
"2" for a write response
Is set to It is set to "4" in the case of a quadlet read in a read request (Read request), and is set to "5" in the case of a block read (Block Read). In the case of a read response (Read Response), it is set to “6/7”.

The resolver 106 receives the self-I data transmitted over the IEEE 1394 serial interface bus BS.
The D packet is analyzed and stored in the CR 107. It also has functions such as error checking and counting the number of nodes.

The transaction layer circuit 120
It has a function of automatically transmitting and receiving data of a computer peripheral device (a hard disk in this embodiment) as an asynchronous packet based on the SBP-2 (Serial Bus Protocol-2) standard. Further, the transaction layer circuit 120 has a retry function and a split timeout detection function. The retry function is a function of retransmitting the corresponding request packet when an ack busy ^* Ack code is returned after transmitting the request packet. When retransmitting a packet, the 2-bit rt area in the first quadred of the transmission packet is set from “00” to “01”, and the core link 101 is notified and transmitted. The split timeout detection function is a function for detecting a timeout until a response packet is returned.

This transaction layer circuit 120
Is a transport data interface circuit 121,
Request packet generation circuit (SBPreq) 122, response packet decode circuit (SBPRsp) 123, request FIFO (Request F
IFO: ADPTF) 124, Response FIFO (Response FIFO: ADP)
RF) 125, and the transaction controller 12
6. Then, the request packet generation circuit 122, the response packet decode circuit 123, the request F
A data processing circuit AD is provided by the I / O 124, the response FIFO 125, and the transaction controller 126.
P is configured.

The transport data interface circuit 121 arbitrates the transmission and reception of data between the HDD controller 30, the request packet generation circuit 122, and the response packet decode circuit 123.

The request packet generation circuit 122 has a link
Upon receiving a data transfer start instruction from the CR 107 of the layer circuit 100, in the case of transmission (write), the transport data interface circuit 1 according to the SBP-2 standard.
21 so that the computer data recorded on a hard disk (not shown) obtained through
The data is divided into a plurality of pieces of data, and the address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107. The 1394 bus address and the transaction label tl (= a) and the transaction code tcode ( For example, a 1394 header made up of four cladlets in which, for example, 1 or 5) is set is stored in the request FIFO 124. In the case of reception (reading), CR1 is used in accordance with the SBP-2 standard.
07, the SBP protocol address is calculated based on the data such as the transfer data length, and the 1394 bus address and the transaction label tl (= a), the transaction code tcode (for example, 1 or 5), etc., which are increased for each packet, are calculated. Set and specified address,
1394 block read request command (B
lock read Request Command) is stored in the request FIFO 124 as one or more packets.

The request packet generation circuit 122 calculates the maximum data length of a response packet to a request packet to be transmitted upon receiving the maximum length data max-payload specified by the CR 107 during transmission and reception. This maximum data length (byte) maxpl is obtained based on the following equation.

[0036]

[Expression 1] maxpl = 2 ^{(max, Payload + 2)} (1)

The response packet decoding circuit 123 reads the data stored in the response FIFO 125 at the time of reception, removes the 1394 header, and transfers the data at a predetermined timing to the transport data interface circuit 12.
1 to the HDD controller 30.

The request FIFO 124 stores packetized transmission data when transmitting (writing), and stores a 1394 block read request command when receiving (reading). The request FIFO 12
When the data to be transmitted is stored, the signal 4 outputs an active signal EMT, for example, at a low level (“0”) indicating this to the transaction controller 126.

In the case of receiving (reading), the response FIFO 125 stores received data transmitted from the host computer via the 1394 serial bus BS. The response FIFO 125 outputs a signal indicating the remaining storage capacity to the transaction controller 126.

The transaction controller 126
The packetized transmission data stored in the request FIFO 124 at the time of transmission, and the request FIFO 12 at the time of reception.
4 controls the output of the 1394 block read request command (request packet) stored in No. 4 to the link core 101 of the link layer core circuit 100. Also, when sending,
Upon receiving a response packet from the classification circuit 105 of the link layer circuit 100, the retry code rcode is set to C
The response packet from the classification circuit 105 is stored in the response FIFO 125 upon reception.

The transaction controller 12
6, as shown in FIG. 2, it is determined whether or not there is an error in the response packet (including Acknowledge which is a confirmation of reception from another node). An error determination circuit 1261 for stopping the processing of the packet generation circuit 122, the response packet decode circuit 123, the request FIFO 124, and the response packet 125 by the signal S126.

Write (transmit) and read (receive)
Acknowledgment (Acknowledge)
edge) or a response packet, for example, there is a possibility that an error as shown in FIG. 3 may occur. When the error determination circuit 1261 detects that there is an error, the request packet generation circuit 122 and the response packet decode circuit
3. Request FIFO 124 and Response Packet 125
Is stopped, the contents of these errors are determined, and for example, an error code corresponding to the contents is set to CR10.
7 is set in the error register. When an error is detected, CR1 for an interrupt signal (Interrupt) is output.
An interrupt bit is set to 07 to notify the local processor 40 that an error has been detected.

Here, the contents of each error code in FIG. 3 will be described. The error code ERC "0" indicates no error, "1" indicates that an inappropriate ack code was returned for the transmitted request, "2" indicates an inappropriate ack code for the received response, and "3" indicates There is no response within the specified time,
"4" indicates the number of retries, the other party is busy even if a request packet is sent, "5" indicates that a bus reset has occurred, "6" has received an inappropriate rcode (response code), and "7". Indicates that a response packet has been received from a node other than the designated node, and "8" indicates that a tcode (transaction code) different from the transaction being executed has been received.

Here, the operation of the error discriminating circuit shown in FIG. 2 at the time of writing (receiving) will be described with reference to the flowchart of FIG. The normal operation of transmitting and receiving data will be described.

The error determining circuit 1261 first determines whether an appropriate ack code (response packet) for the request packet has been returned (S).
1). If it is an inappropriate ack code in step S1, it is determined that the error is that an inappropriate ack code was returned in response to the request transmitted with code "1". If it is determined in step S1 that an appropriate ack code has been returned, the response is completed (Complete) or busy (Bus).
Different determination processing is performed depending on whether y) or Pending.

In the case of complete, it is determined whether it is a read or a write. If the read is an inappropriate response, it is determined that an error of code "1" is detected. Is determined to be complete (S3).

In the case of busy, a retry operation for retransmission is performed, and it is determined whether the number of retries has reached a preset retry limit number (S4). If it is determined in step S4 that the retry limit has not been reached, the operation of step S1, that is, the retransmission operation of the request packet is performed. On the other hand, if the retry limit has been reached, it is determined that the other party is busy even if the request packet is transmitted as many times as the retry limit of code “4”.

In the case of pending, step S5
Steps S9 to S9 are sequentially performed. First, step S5
In, it is determined whether a response packet has been received within a preset time. In step S5, if the response packet does not return within the preset time, it is determined that the error does not return within the time specified by the code "3". On the other hand, if the response is returned within the specified time, the process proceeds to step S6.

In step S6, it is determined whether or not an inappropriate ack code has been returned to the received response. In step S6, a
If the ck code is returned, the inappropriate ac
It is determined that the error has returned the k code. On the other hand, if an appropriate ack code has been returned, the process proceeds to step S7.

In step S7, an appropriate rcod
It is determined whether or not e (response code) has been received. In step S7, if an inappropriate rcode is received, it is determined that the error is that an inappropriate rcode with code "6" was received. On the other hand,
If de is received, the process proceeds to step S8.

In step S8, the source
It is determined whether or not the ID is normal. Step S
If it is determined in step 8 that the source ID is abnormal,
It is determined that an error has occurred in receiving a response packet from a node other than the designated node with the code “7”. On the other hand, if a normal source ID has been received, the process proceeds to step S9.

In step S9, the received tco
It is determined whether or not de (transaction code) is normal. If it is determined in step S9 that the received tcode is abnormal, it is determined that the received error is an error in which a tcode different from the transaction executed by the code “8” is received. On the other hand, when a normal tcode is received, it is processed as no error (complete).

When the error discriminating circuit 1261 detects that there is an error as described above, the signal S126 is output to the request packet generating circuit 122, the response packet decoding circuit 123, the request FIFO 124 and the response packet 125. Then, a process for stopping those processes is performed. Then, an error code corresponding to the content of the error is set in the error register of the CR 107, and when an error is detected, an interrupt signal (Interrupt) is generated.
An interrupt bit is set in the CR 107 for use. This notifies the local processor 40 that there is a request to interrupt due to an error. As a result, the contents of the CR 107 are read by the local processor 40, and an initialization (reset) process for the transaction layer circuit 120 is performed via the CR 107.

Next, normal transmission and reception operations of computer data in the case of transferring a packet determined by the SBP-2 standard in the above configuration will be described.

First, a transmission operation, that is, a case where data is transferred from a target hard disk to a host computer which is an initiator and an operation of writing data from a storage device (hard disk) to a memory of the host computer will be described. I do.

An O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB (Operatio Request Block) is transmitted to the physical layer circuit 20 and the link layer circuit 100.
Is input to the classification circuit 105 via the link core 101.

The classification circuit 105 receives the received packet and receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. As a result, the transaction layer circuit 120 is activated.

In the activated transaction layer circuit 120, the request packet generation circuit 122 starts a data request to the HDD controller 30 via the transport interface 121. The transmission data transmitted via the transport interface 121 in response to the request is transmitted to the request packet generation circuit 1.
At 22, the computer data recorded on the hard disk (not shown) obtained via the transport data interface circuit 121 in accordance with the SBP-2 standard is divided into one or more data so as to be divided into packets.
The address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107, and the 1394 bus address which increases for each packet, the transaction label tl (= a), and the transaction code tco
1394 header consisting of four cladlets in which de (for example, 1 or 5) is set,
It is stored in O124.

One 1394 is stored in one FIFO for request 124.
When data equal to or larger than the packet size is stored, the data is sent to the link core 101 of the link layer circuit 100 by the transaction controller 126. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20. As a result, if a bus can be acquired, a write request packet (Write Request Packet) including transfer data is sent to the physical layer circuit 2.
0, transmitted to the host computer via the 1394 serial bus BS.

After transmission, an Ack code for the write request packet and a write response packet (Write Response Packet) are transmitted from the host computer, and the physical layer circuit 20 and the link core 101 of the link layer circuit 100 are transmitted. Classification circuit 10 via
5 is input.

In the sorting circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and the transaction layer circuit 12 as the target is sent from the host computer.
If the response packet is determined to be a response packet (Response Packet) for the
Transaction controller 12 of layer circuit 120
6 is input.

In the transaction controller 126, if the Ack code and the response code (Response code) of the input response packet are normal, the next data is transmitted to the link core 101. By repeating the above operation, the operation of writing (transmitting) the computer data to the memory of the host computer is performed.

FIG. 4 shows an outline of the operation of the transaction layer circuit 120 for the above transmission.

Next, a reception operation, that is, a case where data is transferred from the host computer to the target and an operation in which the storage device (hard disk) reads data from the memory of the host computer will be described.

An O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB (Operatio Request Block) is transmitted to the physical layer circuit 20 and the link layer circuit 100.
Is input to the classification circuit 105 via the link core 101.

The classification circuit 105 receives the received packet and receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. As a result, the transaction layer circuit 120 is activated.

In the activated transaction layer circuit 120, the request packet generation circuit 122
According to the BP-2 standard, the address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107, and the 1394 bus address which increases for each packet, the transaction label tl (= a), and the transaction code tcode (for example, 1 or 5) is set, and 139 of the specified address and data length are set.
4 block read request command (Block readRequest C
ommand) is packetized and stored in the request FIFO 124.

The read request command packet stored in the request FIFO 124 is sent by the transaction controller 126 to the link core 101 of the link layer circuit 100. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20.
As a result, if the bus is acquired, a read request packet (Read Request Packet) is transmitted to the host computer via the physical layer circuit 20 and the 1394 serial bus BS.

After the transmission, an Ack code for the read request packet from the host computer and a read response packet (Read R) including data of the designated data length.
esponse Packet) is sent to the physical layer circuit 20 and the link core 10 of the link layer circuit 100.
The signal is input to the classification circuit 105 through the line 1.

In the sorting circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and it is determined that the received packet is a response packet (Response Packet) from the host computer to the target transaction layer circuit. Then, the response packet is input to the transaction controller 126 of the transaction layer circuit 120.

In the transaction controller 126, the response packet from the classification circuit 105 is
It is stored in O125. The data stored in the response FIFO 125 is read by the response packet decoding circuit 123, the 1394 header is removed, and the data is output to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing.
By repeating the above operation, the operation of writing (receiving) the computer data to the storage device (hard disk) is performed.

FIG. 5 shows an outline of the operation of the transaction layer circuit 129 relating to the above reception.

As described above, according to the present embodiment, the storage device is connected, the data of the storage device is read, and a self-designated transaction label is added and transmitted as a transmission asynchronous packet to the serial interface bus BS. When transferring data of another node to the storage device, a request packet to which a self-designated label is added is generated and transmitted to the serial interface bus BS. Since the transaction layer circuit 120 is provided as a data processing circuit for extracting a data portion from a packet and transferring the data portion to the storage device, large-capacity data stored in the storage device or read from the storage device is stored in the storage device. IEEE that was in accordance with the P-2 standard
1394 packets can be transmitted and received, IEEE
Large-capacity data transfer can be realized using asynchronous packets of the E1394 serial bus interface. Further, the sequence such as ORB fetch, data transfer, and status transmission to the initiator based on the SBP-2 standard can be simplified, and is optimal when connecting data of a computer peripheral device such as a disk driver and a tape streamer to the IEEE 1394 serial bus. Design is possible.

Also, it is determined whether or not the response packet has an error. If there is an error, the content of the error is determined, and the request packet generation circuit 122, the response packet decode circuit 123, the request FIFO 124, and the response packet are determined. Since the error discriminating circuit 1261 for stopping the process at 125 with the signal S126 is provided, when an error occurs, it is possible to determine the error, the addition of a control system circuit can be reduced, and accurate transmission / reception processing can be performed.

Further, the transaction layer circuit 1
20 is a request FIFO 124 and a response FIFO 12
5 as well as the transmission FIFO 103 and the reception FIFO 104 in the link layer circuit 100, the request FIFO 124 and the response FIFO 12
5, the transmission and reception of normal 1394 packets other than the data can be performed in parallel with the exchange of the data according to the fifth embodiment.

Further, the transaction code tcode (Transaction code) and the transaction label tl (Transaction label) in the first quadrant of the asynchronous communication packet via the link core 101 are checked, and the target transaction is transmitted from the host computer as the initiator. Discriminating whether the packet is a response packet (Response Packet) to the layer circuit or another packet, input only the response packet to the transaction layer circuit 120, and store the other packet in the reception FIFO 104 Since the classification circuit 105 is provided, even if a fatal error occurs in the transaction layer circuit 120 and the data read / write operation is stopped, for example, the read command of the next input command of the data is read. Without becomes possible out, there is an advantage that the reception of the no command regardless of the data read / write status can be smoothly performed.

[0077]

As described above, according to the present invention,
In addition to being able to transmit and receive large-capacity data in packets conforming to a predetermined standard, it is also possible to determine if an error has occurred, reduce the need for additional control circuitry, and perform accurate transmission and reception processing. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.

FIG. 2 is a block diagram illustrating an error determination circuit according to the present invention.

FIG. 3 is a diagram showing an example of an error code.

FIG. 4 is a flowchart illustrating an error determination operation.

FIG. 5 is a diagram schematically illustrating a transmission operation in the transaction layer circuit according to the present invention.

FIG. 6 is a diagram schematically illustrating a receiving operation in the transaction layer circuit according to the present invention.

FIG. 7 is a diagram for describing asynchronous transfer of the IEEE 1394 standard.

[Explanation of symbols]

10 link / transaction layer integrated circuit, 20
... Physical layer circuit, 30 ... HDD controller, 40 ... Local processor, 100, 100a ... Link layer circuit, 101 ... Link core, 102 ... CP
U interface circuit, 103: Asynchronous transmission FIFO, 104: Asynchronous reception FIFO, 1
05, 105a: Classification circuit, 106: Resolver, 107
... Control register, 120 ... Transaction
Layer circuit, 121: transport data interface circuit, 121: request packet generation circuit, 123: response packet decoding circuit, 124: request FIFO, 1
25 ... Response FIFO, 126 ... Transaction controller, 1261 ... Error discrimination circuit.

Claims (8)

[Claims] 1. A serial interface circuit for transmitting and receiving a packet between a self-node and another node connected via a serial interface bus, comprising: generating a request packet from the self-node to another node; And a data processing circuit for performing a reception process on a response packet to the request packet; and determining whether the received response packet has an error,
A serial interface circuit having an error discriminating circuit for discriminating the content of the error when there is an error; 2. The serial interface circuit according to claim 1, wherein said error determination circuit stops a packet transmission / reception process of said data processing circuit when detecting an error. 3. The serial interface circuit according to claim 1, further comprising an error register, wherein said error discriminating circuit sets an error content in said error register when an error is detected. 4. The serial interface circuit according to claim 2, further comprising an error register, wherein said error discriminating circuit sets an error content in said error register when an error is detected. 5. The serial interface circuit according to claim 3, further comprising a control circuit for initializing said data processing circuit when an error content is set in said error register. 6. The serial interface circuit according to claim 4, further comprising a control circuit for initializing said data processing circuit when an error content is set in said error register. 7. When the error discriminating circuit detects the error, the error discriminating circuit notifies the control circuit that the error has been detected. The control circuit reads the error register in response to the error detection, and performs the initialization processing. 6. The serial interface circuit according to claim 5, wherein 8. When the error discriminating circuit detects an error, the error discriminating circuit informs the control circuit that the error has been detected. The control circuit reads the error register in response to the notice of the error detection, and executes the initialization processing. 7. The serial interface circuit according to claim 6, wherein