JPH1117774A - Serial interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable transmission/reception while making the data of a large capacitance into packets and to enable smooth processing by generating a request packet from a present node to the other node, sending it to a serial interface and detecting split time out when the packet of a response to the request packet is not returned within preset time. SOLUTION: A pending detection circuit 1261 detects whether the response from the other node is under pending or not and when pending is detected, a detecting signal S1261 is outputted to a split time counter 1262. When the detecting signal is received, the split time counter 1262 starts time measuring operation. When the time of the split time counter 1262 reaches the set time of a time out register 1263, a time out signal STO showing split time out is outputted from a comparator circuit 1264. Thus, for example, communication operation is stopped and an error is displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital serial interface circuit, and more particularly to a hard disk drive (HDD).
Drive), DVD (Digital Video Disk) -ROM, CD
(Compact Disk)-ROM, Tape Streamer
The present invention relates to a serial interface circuit connected to a storage device such as an amer) and a signal processing method thereof.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

In the data transfer of the IEEE 1394 serial interface, a transfer operation performed in a network is called a subaction, and two subactions are defined. One is conventional Request, Acknow
Asynchronous (Asynch) for requesting and confirming receipt of ledge
ronous) forwarding, and the other is 125
Isochronous (Isoch) where data is always sent once every μs
ronous) Transfer.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Although transfer is performed in packet units, in the IEEE 1394 standard, the minimum data unit handled is one quadlet (q
uadlet) (= 4 bytes = 32 bits).

[0005] In the IEEE1394 standard, computer data is usually transmitted using asynchronous transfer as shown in FIG. Asynchronous transfer is shown in FIG.
As shown in (a), there are three transition states: arbitration (arb) for acquiring a bus, packet transmission for transferring data, and acknowledgment (ack).

The execution of packet transmission is performed in a format as shown in FIG. The first quadlet of the transfer packet includes a 16-bit destination ID (destination ID) area and a 6-bit transaction label tl (transaction label).
l) area, 2-bit retry code rt (retry cod
e) area, 4-bit transaction code tcod
An e (transanction code) area and a 4-bit priority pri (priority) area. The destination ID area indicates the bus number and node number of this node, and the priority area indicates the priority level.

[0007] The second and third quadlets have a 16-bit source ID area and a 48-bit destination offset (destina- tion).
tionoffset) region. The source ID area shows the ID of the node that sent this packet, and the destination offset area shows high (High) and low (L
ow), and indicates the address of the address space of the destination node.

[0008] The fourth quadlet is composed of a 16-bit data length area and a 16-bit extended transaction code (extended tcode) area. The data length field indicates the number of bytes of the received packet, and the extended tcode field is tc.
mode is a Lock transaction
If, the actual locking action performed by the data in this packet
(Lock Action).

[0009] A header CRC (header CRC) added to the quadlet before the data field area (data field)
The area is an error detection code of the packet header. Also,
A data CRC (data CRC) area added to the quadlet after the data area (data field) is an error detection code of the data field.

[0010]

As described above, in the normal computer data transfer performed by the asynchronous transfer, the SBP-based protocol is used as the protocol.
2 (Serial Bus Protocol-2) is used. According to this protocol, a host device (Host) is transferred from a target (Target) that is a storage device.
When transferring data to the initiator, which is a Computer, the data is written from the storage device to the memory of the host computer, and when transferring the data from the host computer to the target,
The transfer is performed in such a manner that the storage device reads the data in the memory of the host computer.

However, a processing circuit system for controlling a so-called transaction layer for transmitting and receiving a large amount of data stored in or read from the storage device in packets of the IEEE 1394 standard. Has not yet been established. There is also a need for a circuit that detects a split timeout in a split transaction.

The present invention has been made in view of the above circumstances, and an object of the present invention is to enable automatic detection of split timeout, and to transmit and receive a large amount of data as a packet conforming to a predetermined standard. Another object of the present invention is to provide a serial interface circuit capable of performing smooth transmission / reception processing.

[0013]

In order to achieve the above object, the present invention relates to a serial interface circuit for transmitting and receiving a packet between another node connected to the own node via a serial interface bus. And a second data processing circuit for generating a request packet to be transmitted to another node and transmitting the request packet to the serial interface bus, and a second data processing circuit for detecting a split timeout when a response packet to the request packet is not returned within a predetermined time. Data processing circuit.

In the present invention, the second data processing circuit detects whether or not a response from another node is pending, and outputs a detection signal when the response is detected as pending. Circuit, a split time counter which starts up when receiving a detection signal from the pending detection circuit and measures time, a timeout register which can set a timeout time arbitrarily, and a time of the split time counter set time of the timeout register. And a comparison circuit that outputs a timeout signal indicating that a split timeout has occurred.

In the present invention, when the split time counter receives the response packet after the start of the timing operation and before the timeout signal is output from the comparison circuit, the split time counter stops the timing operation.

In the present invention, the set time of the timeout register is changed according to the data length.

Further, according to the circuit of the present invention, in the first data processing circuit, a request packet from the own node to another node is generated and transmitted to the serial interface bus. The second data processing circuit detects a split timeout when a response packet to the request packet is not returned within a preset time.

For example, a pending detection circuit detects whether or not a response from another node is pending, and outputs a detection signal to the split time counter when the response is detected as pending. The split time counter is activated upon receiving the detection signal, and starts the timekeeping operation. When the time of the split time counter reaches the time set in the time-out register, a time-out signal indicating a split time-out is output from the comparison circuit.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an IEEE 1 according to the present invention.
FIG. 3 is a block diagram illustrating an embodiment of a 394 serial interface circuit. This serial interface circuit is configured to transfer computer data handled in asynchronous communication. Therefore, FIG. 1 does not show a specific configuration of the isochronous communication system circuit.

This serial interface circuit includes a link / transaction layer integrated circuit 10, a physical layer circuit 20, a hard disk driver (HDD) controller 30 (not shown) as a storage device, and a local processor 40 as a host computer. I have.

The link / transaction layer integrated circuit 10 is formed by integrating the link layer circuit 100 and the transaction layer circuit 120, and controls the asynchronous transfer under the control of the local processor 40 and the physical layer circuit. 20.

As shown in FIG. 1, a link layer circuit 100 includes a link core (Link Core) 101, a CPU interface circuit (Sub-CPU I / F) 102, and a transmission FIFO (AT-AT) used for asynchronous communication. FIFO: First-In F
irst-Out) 103, receiving FIFO (AR-FIFO) 104,
Classification circuit (DeMux) 105 for discriminating received packets, resolver for self ID (Resolver) 106, and control register (ControlRegisters, hereinafter referred to as CR) 1
07.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets to which commands and computer data are transferred, and a physical layer circuit 20 for directly driving these packets on the IEEE 1394 serial bus BS. It is composed of an interface circuit, a cycle timer reset every 125 μs, a cycle monitor and a CRC circuit. Further, it performs a transmission process of computer data read from a hard disk (not shown) and generated by the transaction layer circuit 120 as a predetermined transmission packet. For example, a transaction controller 1 of a transaction layer circuit 120 described later
Upon receiving a notification that there is data to be sent from 26, the 1394 serial bus is arbitrated via the physical layer circuit 20 to secure the bus. In FIG. 1, the FIFO and the like of the isochronous communication system are omitted as described above.

The CPU interface circuit 102 includes a local processor 40, a transmission FIFO 103, and a reception FIFO.
It performs arbitration such as writing and reading of asynchronous communication packets with the IFO 104 and arbitration of transmission and reception of various data between the local processor 40 and the CR 107. For example, a host computer as an initiator transmits an IEEE 1394 interface bus BS, and transmits a command for controlling a hard disk as a storage device stored in a reception FIFO to the local processor 40.

From the local processor 40, data for activating the transaction layer circuit 120 for transmitting and receiving computer data is set in the CR 107 through the CPU interface 102 (ADPst).
= 1).

The transmission FIFO 103 includes IEEE13
Asynchronous communication packets to be transmitted to the N. 94 serial bus BS are stored.
Given to.

The receiving FIFO 104 is based on the IEEE standard.
Asynchronous communication packets transmitted through the 1394 serial bus BS, for example, commands for controlling a hard disk as a storage device and the like are stored by the classification circuit 105.

The discrimination circuit 105 has a transaction code tcode (Transaction) in the first quadred of the asynchronous communication packet via the link core 101.
code) and transaction label tl (Transaction
label), discriminates whether the packet is a response packet (Response Packet) from the initiator host computer to the target transaction layer circuit or other packets, and only the response packet is transferred to the transaction layer circuit. The packet is input to the circuit 120, and the other packets are stored in the reception FIFO 104.

The transaction label tl used for sorting check is set to "a" in common, and t
In the code (Transaction code), different data is set for a write request (request) and response (Response), and for a read (Read) request (Read request) and response (Read Response). Specifically, tcode
Is set to "0" in the case of a quadlet write in a write request and "1" in the case of a block write.
"2" for a write response
Is set to It is set to "4" in the case of a quadlet read in a read request (Read request), and is set to "5" in the case of a block read (Block Read). In the case of a read response (Read Response), it is set to “6/7”.

The resolver 106 receives the self-I data transmitted over the IEEE 1394 serial interface bus BS.
The D packet is analyzed and stored in the CR 107. It also has functions such as error checking and counting the number of nodes.

The transaction layer circuit 120
It has a function of automatically transmitting and receiving data of a computer peripheral device (a hard disk in this embodiment) as an asynchronous packet based on the SBP-2 (Serial Bus Protocol-2) standard. Further, the transaction layer circuit 120 has a retry function and a split timeout detection function. The retry function is a function of retransmitting the corresponding request packet when an ack busy ^* Ack code is returned after transmitting the request packet. When retransmitting a packet, the 2-bit rt area in the first quadred of the transmission packet is set from “00” to “01”, and the core link 101 is notified and transmitted. The split timeout detection function is a function for detecting a timeout until a response packet is returned.

This transaction layer circuit 120
Is a transport data interface circuit 121,
Request packet generation circuit (SBPreq) 122, response packet decode circuit (SBPRsp) 123, request FIFO (Request F
IFO: ADPTF) 124, Response FIFO (Response FIFO: ADP)
RF) 125, and the transaction controller 12
6. Then, the request packet generation circuit 122, the response packet decode circuit 123, the request F
A data processing circuit AD is provided by the I / O 124, the response FIFO 125, and the transaction controller 126.
P is configured.

The transport data interface circuit 121 arbitrates the transmission and reception of data between the HDD controller 30, the request packet generation circuit 122, and the response packet decode circuit 123.

The request packet generation circuit 122 has a link
Upon receiving a data transfer start instruction from the CR 107 of the layer circuit 100, in the case of transmission (write), the transport data interface circuit 1 according to the SBP-2 standard.
21 so that the computer data recorded on a hard disk (not shown) obtained through
The data is divided into a plurality of pieces of data, and the address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107. The 1394 bus address and the transaction label tl (= a) and the transaction code tcode ( For example, a 1394 header made up of four cladlets in which, for example, 1 or 5) is set is stored in the request FIFO 124. In the case of reception (reading), CR1 is used in accordance with the SBP-2 standard.
07, the SBP protocol address is calculated based on the data such as the transfer data length, and the 1394 bus address and the transaction label tl (= a), the transaction code tcode (for example, 1 or 5), etc., which are increased for each packet, are calculated. Set and specified address,
1394 block read request command (B
lock read Request Command) is stored in the request FIFO 124 as one or more packets.

The request packet generation circuit 122 calculates the maximum data length of a response packet to a request packet to be transmitted upon receiving the maximum length data max-payload specified by the CR 107 during transmission and reception. This maximum data length (byte) maxpl is obtained based on the following equation.

[0036]

[Formula 1] maxpl = 2 ^{(max, Payload + 2)} (1)

The response packet decoding circuit 123 reads the data stored in the response FIFO 125 at the time of reception, removes the 1394 header, and transfers the data at a predetermined timing to the transport data interface circuit 12.
1 to the HDD controller 30.

The request FIFO 124 stores packetized transmission data when transmitting (writing), and stores a 1394 block read request command when receiving (reading). The request FIFO 12
When the data to be transmitted is stored, the signal 4 outputs an active signal EMT, for example, at a low level (“0”) indicating this to the transaction controller 126.

In the case of receiving (reading), the response FIFO 125 stores received data transmitted from the host computer via the 1394 serial bus BS. The response FIFO 125 sends a signal S125 indicating the remaining storage capacity to the transaction controller 12.
6 is output.

The transaction controller 126
The packetized transmission data stored in the request FIFO 124 at the time of transmission, and the request FIFO 12 at the time of reception.
4 controls the output of the 1394 block read request command (request packet) stored in No. 4 to the link core 101 of the link layer core circuit 100. Also, when sending,
Upon receiving a response packet from the classification circuit 105 of the link layer circuit 100, the retry code rcode is set to C
The response packet from the classification circuit 105 is stored in the response FIFO 125 upon reception.

The transaction controller 12
In the split transaction, when a response packet is not returned after receiving a so-called pending ack code in the process of the split transaction, it is detected as a split timeout, and for example, the communication operation is stopped and an error is displayed.

In IEEE 1394, a response packet is returned in response to transmission of a request packet. When the responder (Responder) on the other node side does not have a sufficient response speed, the response packet is exchanged in a process called a split transaction.

FIG. 2 is a conceptual diagram of a split transaction. In this case, the requester (R
The responder on the other node side that has received the request packet from the equester) sets a 4-bit ack code to indicate that it is pending and sends it back. Thereafter, when the writing and reading processes are completed (Complete), a response packet is transmitted to the requester. As described above, if a response packet is not returned after a pending ack code is received during the split transaction process, it is detected as a split timeout.

FIG. 3 is a block diagram showing a configuration example of a split timeout detecting circuit for realizing the split timeout detecting function. As shown in FIG. 3, the split timeout detection circuit detects whether or not a response from another node is pending, and outputs a detection signal S1261 when detecting that the response is pending. , A split time counter 1262 that starts up and counts time when it receives a detection signal S1261 from a pending detection circuit 1261.
A time-out register 1263 that can arbitrarily set a time-out time, and a time-out signal ST indicating that a split time-out has occurred when the time of the split time counter reaches the time set in the time-out register.
And a comparison circuit 1264 for outputting O.
Also, the split time counter 1261 stops the timing operation when receiving a response packet after the start of the timing operation and before the timeout circuit is output from the comparison circuit 1264. Further, the set time of the timeout register 1263 is changed according to, for example, the data length.

FIG. 4 is a flowchart showing the operation of the split timeout detecting circuit. As shown in FIG. 4, the pending detection circuit 1261 detects whether or not a response from another node is pending. If the response is pending, a detection signal S1261 is output to the split time counter 1261. (S
1). Upon receiving the detection signal, the split time counter 1262 is activated and starts a timekeeping operation (S2).
When the time of the split time counter 1262 reaches the time set in the time-out register 1263 (S3), the comparison circuit 1264 outputs a time-out signal STO indicating a split time-out. Thereby, for example, the communication operation is stopped and an error display is performed.

In step S4, it is determined whether or not the split time counter 1261 has received a response packet after the start of the clocking operation and before the timeout signal is output from the comparison circuit 1264. When it is determined that the response packet has been received, the timer operation is stopped assuming that the response has been normally performed. On the other hand, if it is determined that the response packet has not been received, the process returns to step S3 to determine whether the time of the split time counter 1262 has reached the time set in the timeout register 1263. .

Next, a description will be given of a normal transmission and reception operation of computer data in the case of transferring a packet determined by the SBP-2 standard in the above configuration.

First, a transmission operation, that is, a case where data is transferred from a target hard disk to a host computer which is an initiator and an operation of writing data from a storage device (hard disk) to a memory of the host computer will be described. I do.

O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB (Operation Request Block) is transmitted to the physical layer circuit 20 and the link layer circuit 10
0 is input to the classification circuit 105 via the link core 101 of 0.

Upon receiving the received packet, the classification circuit 105 receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. As a result, the transaction layer circuit 120 is activated.

In the activated transaction layer circuit 120, the request packet generation circuit 122 starts a data request to the HDD controller 30 via the transport interface 121. The transmission data transmitted via the transport interface 121 in response to the request is transmitted to the request packet generation circuit 1.
At 22, the computer data recorded on the hard disk (not shown) obtained via the transport data interface circuit 121 in accordance with the SBP-2 standard is divided into one or more data so as to be divided into packets.
The address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107, and the 1394 bus address which increases for each packet, the transaction label tl (= a), and the transaction code tco
1394 header consisting of four cladlets in which de (for example, 1 or 5) is set,
It is stored in O124.

One 1394 is stored in one FIFO for request 124.
When data equal to or larger than the packet size is stored, the data is sent to the link core 101 of the link layer circuit 100 by the transaction controller 126. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20. As a result, if a bus can be acquired, a write request packet (Write Request Packet) including transfer data is sent to the physical layer circuit 2.
0, transmitted to the host computer via the 1394 serial bus BS.

After the transmission, an Ack code for the write request packet and a write response packet (Write Response Packet) are transmitted from the host computer, and the physical layer circuit 20 and the link core 101 of the link layer circuit 100 are transmitted. Classification circuit 10 via
5 is input.

In the classification circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and the target transaction layer circuit 12 is sent from the host computer.
If the response packet is determined to be a response packet (Response Packet) for the
Transaction controller 12 of layer circuit 120
6 is input.

In the transaction controller 126, if the Ack code and the response code (Response code) of the input response packet are normal, the next data is transmitted to the link core 101. By repeating the above operation, the operation of writing (transmitting) the computer data to the memory of the host computer is performed.

FIG. 5 shows an outline of the operation of the transaction layer circuit 120 for the above transmission.

Next, a reception operation, that is, a case where data is transferred from the host computer to the target, and a case where the storage device (hard disk) performs an operation of reading data from the memory of the host computer will be described.

An O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB is a physical layer circuit 2
0, which is input to the classification circuit 105 via the link core 101 of the link layer circuit 100.

Upon receiving the received packet, the classification circuit 105 receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. As a result, the transaction layer circuit 120 is activated.

In the activated transaction layer circuit 120, the request packet generation circuit 122
According to the BP-2 standard, the address of the SBP protocol is calculated based on the data such as the transfer data length set in the CR 107, and the 1394 bus address which increases for each packet, the transaction label tl (= a), and the transaction code tcode (for example, 1 or 5) is set, and 139 of the specified address and data length are set.
4 block read request command (Block readRequest C
ommand) is packetized and stored in the request FIFO 124.

The read request command packet stored in the request FIFO 124 is sent by the transaction controller 126 to the link core 101 of the link layer circuit 100. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20.
As a result, if the bus is acquired, a read request packet (Read Request Packet) is transmitted to the host computer via the physical layer circuit 20 and the 1394 serial bus BS.

After the transmission, an Ack code for the read request packet from the host computer and a read response packet (Read R) including data of the designated data length.
esponse Packet) is sent to the physical layer circuit 20 and the link core 10 of the link layer circuit 100.
The signal is input to the classification circuit 105 through the line 1.

In the sorting circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and it is determined that the received packet is a response packet (Response Packet) from the host computer to the target transaction layer circuit. Then, the response packet is input to the transaction controller 126 of the transaction layer circuit 120.

In the transaction controller 126, the response packet from the classification circuit 105 is
It is stored in O125. The data stored in the response FIFO 125 is read by the response packet decoding circuit 123, the 1394 header is removed, and the data is output to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing.
By repeating the above operation, the operation of writing (receiving) the computer data to the storage device (hard disk) is performed.

FIG. 6 shows an outline of the operation of the transaction layer circuit 129 for the above reception.

As described above, according to the first embodiment, the storage device is connected, the data of the storage device is read, and a self-designated transaction label is added to the serial interface bus BS as a transmission asynchronous packet. When transmitting and transferring the data of the other node to the storage device, a request packet with a self-designated label is generated and transmitted to the serial interface bus BS, and a response packet to the request packet from the other node is received. And a transaction as a data processing circuit for extracting a data portion from the response packet and transferring the data portion to the storage device.
Since the layer circuit 120 is provided, the large-capacity data stored in or read from the storage device can be converted into an IE conforming to the SBP-2 standard.
EE1394 packets can be transmitted and received.
Large-capacity data transfer can be realized by using asynchronous packets of the IEEE 1394 serial bus interface. And O based on the SBP-2 standard.
Sequences such as RB fetch, data transfer, and status transmission to the initiator can be simplified, and an optimum design can be made when data of a computer peripheral device such as a disk driver and a tape streamer is connected to the IEEE 1394 serial bus.

Further, it is detected whether or not the response from the other node is pending. If the response is pending, a pending detection circuit 1261 for outputting a detection signal S1261 and a detection signal S1261 from the pending detection circuit 1261 are output. A split time counter 1262 that starts up and counts the time when it receives the command, and a time-out register 1263 that can set a timeout time arbitrarily.
And a comparison circuit 1264 that outputs a timeout signal STO indicating that a split time-out has occurred when the time of the split time counter reaches the time set in the time-out register. Since the addition can be reduced and the retry interval can be arbitrarily set, a smooth transmission / reception process according to the specification can be performed.

Further, the transaction layer circuit 1
20 is a request FIFO 124 and a response FIFO 12
5 as well as the transmission FIFO 103 and the reception FIFO 104 in the link layer circuit 100, the request FIFO 124 and the response FIFO 12
5, the transmission and reception of normal 1394 packets other than the data can be performed in parallel with the exchange of the data according to the fifth embodiment.

Further, the transaction code tcode (Transaction code) and the transaction label tl (Transaction label) in the first quadrant of the asynchronous communication packet via the link core 101 are checked, and the target transaction is transmitted from the host computer as the initiator. Discriminating whether the packet is a response packet (Response Packet) to the layer circuit or another packet, input only the response packet to the transaction layer circuit 120, and store the other packet in the reception FIFO 104 Since the classification circuit 105 is provided, even if a fatal error occurs in the transaction layer circuit 120 and the data read / write operation is stopped, for example, the read command of the next input command of the data is read. Without becomes possible out, there is an advantage that the reception of the no command regardless of the data read / write status can be smoothly performed.

[0070]

As described above, according to the present invention,
Split timeout detection can be automated, the addition of control circuits can be reduced, and large-capacity data can be transmitted and received as packets conforming to a predetermined standard.
Smooth transmission / reception processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.

FIG. 2 is a diagram illustrating the concept of a split transaction.

FIG. 3 is a block diagram illustrating a configuration example of a split timeout detection circuit according to the present invention.

FIG. 4 is a flowchart illustrating the operation of the circuit of FIG. 3;

FIG. 5 is a diagram schematically illustrating a transmission operation in the transaction layer circuit according to the present invention.

FIG. 6 is a diagram schematically illustrating a receiving operation in the transaction layer circuit according to the present invention.

FIG. 7 is a diagram for describing asynchronous transfer of the IEEE 1394 standard.

[Explanation of symbols]

10 link / transaction layer integrated circuit, 20
... Physical layer circuit, 30 ... HDD controller, 40 ... Local processor, 100, 100a ... Link layer circuit, 101 ... Link core, 102 ... CP
U interface circuit, 103: Asynchronous transmission FIFO, 104: Asynchronous reception FIFO, 1
05, 105a: Classification circuit, 106: Resolver, 107
... Control register, 120 ... Transaction
Layer circuit, 121: transport data interface circuit, 121: request packet generation circuit, 123: response packet decoding circuit, 124: request FIFO, 1
25 Response FIFO, 126 Transaction Controller, 1261 Pending Detection Circuit, 1262
... Split time counter, 1263 ... Timeout register, 1264 ... Comparison circuit (Comp).

Claims (6)

[Claims] 1. A serial interface circuit for transmitting and receiving a packet between a self-node and another node connected via a serial interface bus, comprising: generating a request packet from the self-node to another node; And a second data processing circuit for detecting a split timeout when a response packet to the request packet is not returned within a preset time. 2. A pending detection circuit for detecting whether or not a response from another node is pending, and outputting a detection signal when the response is detected as pending, A split time counter that starts and counts time when a detection signal is received by the pending detection circuit, a timeout register that can set a timeout time arbitrarily, and a split when the time of the split time counter reaches the time set in the timeout register. 2. The serial interface circuit according to claim 1, further comprising: a comparison circuit that outputs a timeout signal indicating a timeout. 3. The serial interface circuit according to claim 2, wherein the split time counter stops the timing operation when receiving a response packet after the start of the timing operation and before a timeout signal is output from the comparison circuit. 4. The serial interface circuit according to claim 2, wherein the set time of the timeout register is changed according to the data length. 5. The serial interface circuit according to claim 3, wherein the time set in the timeout register is changed according to the data length. 6. The serial interface circuit according to claim 1, further comprising a circuit for stopping a packet transfer process when a split timeout is detected by said second data processing circuit.