JP4062829B2 - Serial interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a serial interface circuit that transmits and receives packet data.
[0002]
[Prior art]
In recent years, IEEE (The Institute of Electrical and Electronic Engineers) 1394 and High Performance Serial Bus that realize high-speed data transfer and real-time transfer have been standardized as interfaces for multimedia data transfer.
[0003]
In the data transfer of the IEEE1394 serial interface, a transfer operation performed in the network is called a subaction and two subactions are defined.
One is conventional Asynchronous transfer for request / acknowledge request and reception confirmation, and the other is isochronous transfer in which data is always sent once every 125 μs from a certain node.
[0004]
In this way, data in the IEEE 1394 serial interface having two transfer modes is transferred in units of packets, but in the IEEE 1394 standard, the minimum data unit to be handled is 1 quadlet (= 4 bytes = 32 bits). It is.
[0005]
According to the IEEE 1394 standard, computer data is normally transmitted using asynchronous transfer as shown in FIG.
Asynchronous transfer, as shown in FIG. 6A, takes three transition states: arbitration (arb) for acquiring a bus, packet transmission for transferring data, and acknowledgment (ack).
[0006]
The packet transmission is executed in a format as shown in FIG.
The first quadlet of the transfer packet includes a 16-bit destination ID area, a 6-bit transaction label tl (transaction label) area, a 2-bit retry code rt (retry code) area, and a 4-bit transaction code. It consists of a code tcode (transanction code) area and a 4-bit priority pri (priority) area.
The destination ID area indicates the bus number and node number of this node, and the priority area indicates the priority level.
[0007]
The second quadlet and the third quadlet are configured by a 16-bit source ID area and a 48-bit destination offset area.
The source ID area indicates the node ID that sent this packet, and the destination offset area is composed of continuous high and low areas, and indicates the address of the destination node address space.
[0008]
The fourth quadlet is composed of a 16-bit data length area and a 16-bit extended transaction code area.
The data length area indicates the number of bytes of the received packet, and the extended tcode area indicates the actual lock action (Lock Action) performed by the data of this packet when tcode is a lock transaction. .
[0009]
The header CRC (header CRC) area added to the quadlet before the data field area is an error detection code of the packet header.
A data CRC (data CRC) area added to the quadlet after the data field is an error detection code of the data field.
[0010]
[Problems to be solved by the invention]
By the way, the serial interface circuit is provided with CSR (Control and Status Registers) which are control and status registers including, for example, a core register, a bus-dependent register, a unit-architecture register, and the like. It is done.
[0011]
On the IEEE 1394 serial interface, access (read / write) to the CSR is generally performed by software.
This is because the CSR itself also has on the software side. In such a case, since all processing is performed on the CPU side as the control circuit, the request packet for access is stored in the same reception FIFO (Firs-In First-Out) as the command transfer packet. Thereafter, the CPU sequentially reads and performs predetermined processing.
[0012]
Therefore, in the configuration in which all processing is performed on the CPU side as a conventional control circuit, there is a disadvantage that it takes time to respond and the burden on the CPU is large.
[0013]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a serial interface circuit that can reduce the burden on the control circuit and can respond at high speed.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is a serial interface circuit that receives a packet transferred through a serial interface bus and transmits a response packet to the received packet to the serial interface bus, and includes a control and status register, A control system circuit that generates a response packet according to the content of the received packet and transmits the response packet to the serial interface bus, and when the received packet is a request packet to the register, a response packet according to the content and processing of the request packet And an automatic response circuit that generates a request packet to determine whether or not the received packet is a request packet for requesting access to the register. If the received packet is a request packet, the received packet is supplied to the automatic response circuit. In this case, the received packet is sent to the control system circuit. And a sheet discriminating circuit.
[0015]
In the present invention, the automatic response circuit determines whether the address of the supplied data is normal access or abnormal access to the register, and generates a response packet corresponding to the content if normal. If it is abnormal, an error response packet is generated.
[0016]
In the present invention, the received packet is an asynchronous packet, and the information determined by the determination circuit is information set in a destination offset area.
[0017]
In the present invention, the determination circuit supplies the reception packet to the automatic response circuit and the control system circuit until the supply destination of the reception packet is determined. After the determination, the determination circuit supplies the reception packet to the non-supply destination circuit. Stop.
[0018]
According to the present invention, the packet transferred through the serial interface bus is input to the determination circuit, for example.
In the determination circuit, for example, it is determined based on the supply destination information added to the received packet whether it is a request packet for requesting access to the control and status register, or another control packet such as a command.
At this time, if it is determined that the received packet is a request packet, the request packet is supplied to the automatic response circuit. If it is determined that the received packet is a control packet, the control packet is supplied to the control system circuit. .
In the automatic response circuit supplied with the request packet, a response packet corresponding to the content and processing of the request packet is automatically generated, and the generated response packet is sent to the serial interface bus through the transmission system circuit.
The control system circuit generates a normal response packet according to the contents and processing of the supplied control packet, and sends the generated response packet to the serial interface bus through the transmission system circuit.
[0019]
In the determination circuit, for example, the received packet is supplied to the automatic response circuit and the control system circuit until the supply destination of the received packet is determined.
As a result of the determination, when the received packet is a request packet, the supply of the received packet to the control system circuit is stopped, and when the received packet is other than the request packet, the supply of the received packet to the automatic response circuit is stopped. Stopped.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.
In FIG. 1, the specific configuration of the isochronous communication system circuit is not shown.
[0021]
This serial interface circuit includes a link layer circuit 10, a physical layer circuit 20, and a microcomputer 30 as a host computer.
[0022]
The link layer circuit 10 performs control of asynchronous transfer and isochronous transfer and control of the physical layer circuit 20 under the control of the microcomputer 30.
[0023]
As shown in FIG. 1, the asynchronous communication system circuit of the link layer circuit 10 includes, for example, a link core 101, a microcomputer I / F circuit 102, a demultiplexer 103, a reception FIFO memory (AR-FIFO) 104, and a transmission It comprises a FIFO memory (AT-FIFO) 105, an inbound circuit 106 as a discrimination circuit, an auto response circuit (automatic response circuit) 107, an outbound circuit 108, and a transmission link FIFO memory (LAT-FIFO) 109.
The reception FIFO memory 104, the microcomputer I / F 102, and the microcomputer 30 constitute a control system circuit.
[0024]
The link core 101 has a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, an interface circuit with the physical layer circuit 20 that directly drives the IEEE1394 serial bus BS of these packets, and a cycle timer that is reset every 125 μs. It consists of a cycle monitor and CRC circuit.
The link core 101 transmits / receives a CS (Cycle Start) packet indicating whether transmission / reception is possible or not every 125 μs to / from a transmission / reception destination signal processing circuit via the physical layer circuit 20 and the IEEE 1394 serial interface bus BS. .
In FIG. 1, as described above, the isochronous communication FIFO and the like are omitted.
[0025]
The microcomputer I / F 102 mainly performs arbitration such as writing and reading of asynchronous communication packets between the microcomputer 30 and the transmission FIFO memory 104 and the reception FIFO memory 105.
[0026]
The demultiplexer 103 refers to the t-code (FIG. 6) present in the 1394 header of the communication packet input from the link core 101, and selects any of the asynchronous communication packet, the isochronous communication packet, and the self ID packet. If it is an asynchronous communication packet, it is output to the inbound circuit 106, and if it is an isochronous communication packet, it is output to a processing circuit (not shown).
[0027]
In the reception FIFO memory 104, the inbound circuit 106 stores the asynchronous communication packet transmitted through the IEEE 1394 serial interface bus BS.
For example, when the CSR-abort signal ABRT from the inbound circuit 106 is actively received, the received packet stored up to, for example, about 3 quadlets is not a packet processed by the microcomputer 30, but is read / written to the CSR (for example). Assuming that the packet is for write / lock processing, the write pointer is restored (returned to the pointer position before the start of storing the packet).
[0028]
The transmission FIFO memory 105 stores asynchronous communication packets to be transmitted to the IEEE 1394 serial bus BS, and the stored data is given to the outbound circuit 108.
[0029]
The inbound circuit 106 receives the asynchronous communication packet input from the demultiplexer 103, and determines whether the received packet is a packet addressed to the CSR or the configuration ROM (CONFIG ROM), or to be stored in the reception FIFO memory 104. Whether the packet is a command or the like is determined by the address indicated by the destination offset area of the third quadlet shown in FIG. 6B. In the case of a packet to be supplied to 107 and stored in the reception FIFO memory 104, the packet is supplied to the reception FIFO memory 104.
[0030]
FIG. 2 is a diagram illustrating an example of the destination offset.
In this example, as shown in FIG. 2, the offset “021C-021F” is “Bus Manager ID”, the offset “0220-0223” is “Bandwidth available”, the offset “0224-0227” is “Channel available Hi”, and the offset “0228-022B” is “Channel available Lo”, offset “0400-0413” is “Config ROM”, offset “0900-0903” is “OMPR”, offset “0904-0907” is “OPCR”, offset “0980- “0983” indicates “IMPR”, and the offset “0984-0987” indicates “IPCR”.
[0031]
Then, as described above, the inbound circuit 106 supplies the received packet data to both the auto response circuit 107 and the reception FIFO memory 104 until the address indicated by the destination offset area of the third quadlet is confirmed. When it is determined that the packet is addressed to the CSR or to the configuration ROM (CONFIG ROM), the CSR-abort signal ABRT is active and is output to the reception FIFO memory 104, and is inactive and is output to the auto response circuit 107. .
[0032]
Specifically, when the first quadlet data (32 bits) is input, the inbound circuit 106 writes the data to the top (first) register of the auto response circuit 107 and the address 0 of the reception FIFO memory 104. Write the data for the first quadlet.
Next, when the second quadlet data (32 bits) is input, the inbound circuit 106 writes the data to the second register of the auto response circuit 107 and stores the second quadlet in the first address of the FIFO memory 104 for reception. Write data.
Then, when the third quadlet data (32 bits) is input, the inbound circuit 106 confirms the address indicated by the destination offset area to determine whether the packet is addressed to the CSR, that is, is an auto-response packet. Is determined.
When determining that the packet is addressed to the CSR, the inbound circuit 106 writes data to the third register of the auto response circuit 107 and returns the write pointer (address) of the reception FIFO memory 104 to 0.
Thereafter, the nth data is written to the nth register until the last data of the packet.
On the other hand, when the inbound circuit 106 determines that the packet is not addressed to the CSR, the inbound circuit 106 writes the data of the third quadlet to the second address of the reception FIFO memory 104.
Thereafter, the nth data is written to the (n−1) th address until the last data of the packet.
[0033]
If the inbound circuit 106 determines that the packet is not addressed to the CSR or the like but destined for the reception FIFO memory 104, the inbound circuit 106 deactivates the CSR-abort signal ABRT to the reception FIFO memory 104, and the auto response circuit 107. The CSR-abort signal ABRT is activated.
[0034]
The reception data is stored in the reception FIFO memory 104 or the auto response circuit 107 by a write signal WRIN and a confirmation signal CNFM. The write signal WRIN controls the write pointer, and the confirm signal CNFM controls the confirmation pointer. Thus, the supply data will be confirmed by the confirm signal CNFM.
For example, the receiving FIFO memory 104 that has received the active CSR-abort signal ABRT ignores the subsequent confirmation signal and returns the alternative write pointer to the previous state.
[0035]
The auto response circuit 107 performs predetermined auto response processing on the asynchronous communication packet input from the inbound circuit 106, generates an asynchronous communication packet as a result of the processing, and outputs the asynchronous communication packet to the outbound circuit 106.
Here, the auto-response processing is not performed by outputting the asynchronous communication packet transmitted through the IEEE 1394 serial interface bus BS to the microcomputer 30 and processing it automatically in the link layer circuit 10. The processing result is a process of transmitting the processing result to the IEEE 1394 serial bus BS.
[0036]
FIG. 3 is a block diagram illustrating a specific configuration example of the auto response circuit 107.
As shown in FIG. 3, the auto response circuit 107 includes an input timing generation circuit 1071, a data store circuit 1072, an address check circuit 1073, a response packet generation circuit 1074, an output timing generation circuit 1075, a CSR 1076, and a CONFIG ROM 1077. ing.
[0037]
When the input timing generation circuit 1071 receives the CSR-abort signal ABRT inactive and receives the confirmation signal CNFM IN active, the input timing generation circuit 1071 receives the write signal WRIN and receives the input timing signal S1071a of the received data supplied from the inbound circuit 106. , S1071b are generated and output to the data store circuit 1072 and the output timing generation circuit 1075, respectively.
[0038]
The data store circuit 1072 includes registers DSreg1, DSreg2, and DSreg3, and temporarily stores data supplied from the inbound circuit 106 based on the input timing generated by the input timing generation circuit 1071. This stored data is supplied to the address check circuit 1073 and the response packet generation circuit 1074.
[0039]
The address check circuit 1073 determines whether the address of the data stored in the data store circuit 1072 is normal access or abnormal access to the register, and outputs the result as a signal S1073 to the response packet generation circuit 1074.
[0040]
When the output signal S1073 of the address check circuit 1072 indicates that the access to the normal register is indicated, the response packet generation circuit 1074 generates a response packet according to the content and outputs the response packet as data DOUT. It outputs to 108.
On the other hand, the response packet generation circuit 1074 generates an address error or type error response packet when the output signal S1073 of the address check circuit 1072 locks, for example, a read-only address, and outputs the response packet as data DOUT. Output to.
[0041]
The output timing generation circuit 1075 receives the timing signal S1071b from the input timing generation circuit 1071, generates the output timing of the response packet data DOUT to the transmission link FIFO memory 109 by the response packet generation circuit 1074, and outputs it as a read response signal WROUT. Output to the outbound circuit 108. At this time, the confirmation signal CNFM is active and the abort (invalid) signal ABRT is output inactive.
[0042]
FIG. 4 is a diagram illustrating input data and signals when a response packet for a read-quadlet request (Read-Quadlet-Request) is supplied to the auto response circuit 107, and generated response packet data and signal examples. .
FIG. 5 is a diagram showing a format of a response packet generated in response to the read quadlet request.
FIG. 4 shows a case where a read request is issued to the offset “021C (Bus Manager ID)” as an example.
[0043]
In this case, as shown in FIGS. 4A and 4B, the write signal WRIN is sequentially input to Hdr1, Hdr2, and Hdr3 in units of quadlets, and the write signal WRIN and the confirmation signal CNFM IN are input at the input timing of the fourth quadlet. Supplied.
In this example, the data of the first header (Hdr1) of the first quadlet is supplied as “00010004”, for example, and the data of the second header (Hdr2) of the second quadlet is supplied as “FFC1FFFF”, for example. The data of the third header (Hdr3) of the quadlet is supplied as “F000021C”, for example.
[0044]
Then, the data (Hdr1, Hdr2, Hdr3) is taken into the registers DSreg1, DSreg2, DSreg3 of the data store circuit 1072.
In the data store circuit 1072, when Hdr3 is input to the register DSreg1, all data has been captured.
[0045]
In the address check circuit 1073, when t-code = 4 of the data Hdr1 fetched in the register DSreg3 of the data store circuit 1072, this packet is a read request, and the packet addressed to the auto response by the offset = 21C fetched in the register DSreg1 Thus, the signal S1073 is output to the response packet generation circuit 1074 at a high level, for example.
[0046]
The CSR 1076 and the CONFIG ROM 1077 have a register corresponding to each offset value, and data (0000003f) with an offset value = 21C is output from the data Hdr3 of the register DSreg1 of the data store circuit 1072.
[0047]
Then, response packet generation circuit 1074 generates first and second headers Hdr1 and Hdr2 in the first and second quadlets, and further sets read data in the fourth quadlet to generate a response packet. .
In this case, the response packet generation circuit 1074 generates the response packet Hdr1 = 00010060 (t-code = 6: read response) from the input data Hdr1 = 00010040 for the data of the first header (Hdr1) of the first quadlet. Is done.
Similarly, Hdr2 = FFC00000 of the response packet is generated from the input data Hdr2 = FFC1FFFF.
[0048]
The output timing generation circuit 1075 outputs Hdr1, Hdr2 and read data generated from the response packet generation circuit 1074 in synchronization with the read response output timing signal WROUT.
Finally, the signal CNFMOUT is output by the output timing generation circuit 1075 and becomes valid data.
[0049]
The outbound circuit 108 outputs the asynchronous communication packet generated by the auto response circuit 107 to the transmission link FIFO memory 108 in the case of auto response processing, and is generated by the microcomputer 30 in the case of normal processing. The asynchronous communication packet stored in the trusted FIFO memory 105 is output to the transmission link FIFO memory 108.
[0050]
The transmission link FIFO memory 109 is a ring buffer that stores the asynchronous communication packet input from the outbound circuit 108.
[0051]
Next, the operation in the above configuration will be described taking the operation when a request packet addressed to CSR is received as an example.
[0052]
For example, packet data transferred through the IEEE 1394 serial interface bus BS is input to the demultiplexer 103 via the physical layer circuit 20 and the link core 101 of the link layer circuit 10.
[0053]
In the demultiplexer 103, the t-code (FIG. 6) existing in the 1394 header of the communication packet input from the link core 101 is referred to, and any of an asynchronous communication packet, an isochronous communication packet, and a self ID packet is obtained. If it is an asynchronous communication packet, it is output to the inbound circuit 106.
[0054]
The inbound circuit 106 receives the asynchronous communication packet from the demultiplexer 103, and the received packet is addressed to the CSR or the configuration ROM (CONFIG ROM) depending on the address indicated by the destination offset area of the third quadlet of the received packet. Whether the packet is a control command or the like to be stored in the reception FIFO memory 104.
[0055]
When the inbound circuit 106 determines that the received packet is a request packet addressed to the CSR, the received packet data is supplied to the auto response circuit 107.
On the other hand, when it is determined that the packet is to be stored in the reception FIFO memory 104, the reception packet is supplied to the reception FIFO memory 104.
[0056]
At this time, as described above, the inbound circuit 106 receives the received packet data in both the auto response circuit 107 and the reception FIFO memory 104 until the address indicated by the destination offset area of the third quadlet is confirmed. Supplied.
In this example, since the received packet is assumed to be a request packet addressed to the CSR, it is determined that the packet is addressed to the CSR, and the inbound circuit 106 actively outputs the CSR-abort signal ABRT to the reception FIFO memory 104. Inactive and output to the auto response circuit 107.
The inbound circuit 106 outputs a write signal WRIN to the auto response circuit 107 at the start timing of each quadlet, and outputs the confirmation signal CNFM at the start timing of the third quadlet, for example, at the start timing of the fifth quadlet. .
[0057]
On the other hand, in the receiving FIFO memory 104, when it is actively received via the CSR-abort signal S108 from the inbound circuit 106, for example, a received packet stored up to about 3 quadlets is addressed to the CSR, and a write pointer is set. It is returned to the pointer position before the start of storage of the packet.
[0058]
The write signal WRIN, SR-abort signal ABRT, and confirmation signal CNFM supplied from the inbound circuit 106 to the auto response circuit 107 are input to the input timing generation circuit 1071.
Since the input timing generation circuit 1071 receives the CSR-abort signal ABRT inactive and receives the confirmation signal CNFM active, the input timing signals S1071a and S1071b of the received data supplied from the inbound circuit 106 based on the write signal WRIN. Is generated and output to the data store circuit 1072 and the output timing generation circuit 1075.
[0059]
The data store circuit 1072 temporarily stores data supplied from the inbound circuit 106 based on the input timing generated by the input timing generation circuit 1071. This stored data is supplied to the address check circuit 1073 and the response packet generation circuit 1074.
[0060]
The address check circuit 1073 determines whether the address of the data stored in the data store circuit 1072 is normal access or abnormal access to the register, and outputs the result to the response packet generation circuit 1074 as a signal S1073.
[0061]
In the response packet generation circuit 1074, when the output signal S1073 of the address check circuit 1072 indicates that the access is to the normal register, a response packet corresponding to the content is generated and is used as the data DOUT. It is output to the outbound circuit 108.
On the other hand, when the output signal S1073 of the address check circuit 1072 locks, for example, an address that only permits reading, an address error or type error response packet is generated and output to the outbound circuit 108 as data DOUT.
[0062]
The output timing generation circuit 1075 receives the timing signal S1071b from the input timing generation circuit 1071 and generates the output timing of the response packet data DOUT to the transmission link FIFO memory 109 by the response packet generation circuit 1074, and outputs it as a signal WROUT. It is output to the circuit 108. At this time, the confirmation signal CNFM is active and the abort (invalid) signal ABRT is inactive and is output to the outbound circuit 108.
[0063]
The generated response packet is input to the link core 101 via the transmission link FIFO memory 108 and further transmitted to the serial interface bus BS via the physical layer circuit 20.
[0064]
As described above, according to this embodiment, when the received packet is a request packet addressed to the CSR, the auto-response circuit 107 that generates a response packet according to the content and processing of the request packet, and the received packet to the CSR The received packet is supplied to the auto-response circuit 107 if it is a request packet, and the received data is stored in the microcomputer 30 if it is not a request packet. Since the inbound circuit 107 that supplies the reception FIFO memory 104 to be used is provided, there is an advantage that a serial interface circuit that can reduce the burden on the microcomputer 30 as a control circuit and can respond at high speed can be realized.
[0065]
If control information set in the configuration register or the like is actively received from the outside or the microcomputer 30, even if the CSR-abort signal ABRT from the inbound circuit 106 is actively received, the storage of the received packet is not stopped. It can also be configured to store everything.
In this case, the microcomputer 30 can be controlled by software.
[0066]
【The invention's effect】
As described above, according to the present invention, there is an advantage that a serial interface circuit that can reduce the burden on the control circuit and can respond at high speed can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.
FIG. 2 is a diagram illustrating an example of a destination offset.
FIG. 3 is a block diagram showing a specific configuration example of an auto response circuit according to the present invention.
FIG. 4 is a diagram showing input data and signals when a read packet for a read quadlet request is supplied to an auto response circuit, and generated response packet data and signal examples.
FIG. 5 is a diagram illustrating a format of a response packet generated in response to a read quadlet request.
FIG. 6 is a diagram for explaining asynchronous transfer of the IEEE 1394 standard.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Link layer circuit, 20 ... Physical layer circuit, 30 ... Microcomputer, 101 ... Link core, 102 ... Microcomputer I / F, 103 ... Demultiplexer, 104 ... Reception FIFO memory (AR-FIFO), 105 ... FIFO memory for transmission (AT-FIFO), 106 ... Inbound circuit, 107 ... Auto response circuit (automatic response circuit), 108 ... Outbound circuit, 109 ... Link FIFO memory for transmission (LAT-FIFO), 1071 ... Input timing generation Circuit: 1072: Data store circuit, 1073: Address check circuit, 1074: Response register, 1075: Output timing generation circuit, 1076: CSR, 1077: CONFIG ROM.

Claims (6)

A serial interface circuit that receives a packet transferred through a serial interface bus and transmits a response packet to the received packet to the serial interface bus.
Control and status registers;
A control system circuit for generating a response packet according to the content of the received packet and transmitting it to the serial interface bus;
An automatic response circuit that generates a response packet according to the content and processing of the request packet when the received packet is a request packet to the register;
It is determined whether or not the received packet is a request packet for requesting access to the register. If the received packet is a request packet, the received packet is supplied to the automatic response circuit. A serial interface circuit having a determination circuit for supplying to a control system circuit. The automatic response circuit determines whether the address of the supplied data is normal access or abnormal access to the register, and if normal, generates a response packet according to the contents, and if abnormal, The serial interface circuit according to claim 1, wherein an error response packet is generated. 2. The serial interface circuit according to claim 1, wherein the received packet is an asynchronous packet, and the information discriminated by the discriminating circuit is information set in a destination offset area. 3. The serial interface circuit according to claim 2, wherein the received packet is an asynchronous packet, and the information determined by the determination circuit is information set in a destination offset area. 4. The determination circuit supplies the reception packet to the automatic response circuit and the control system circuit until determining the supply destination of the reception packet, and stops the reception packet supply to the non-supply destination circuit after the determination. Serial interface circuit. 5. The determination circuit supplies the reception packet to the automatic response circuit and the control system circuit until determining the supply destination of the reception packet, and stops the reception packet supply to the non-supply destination circuit after the determination. Serial interface circuit.

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