JP3837843B2 - Serial interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital serial interface circuit, and in particular, a serial connected to a storage device such as an HDD (Hard Disk Drive), a DVD (Digital Video Disk) -ROM, a CD (Compact Disk) -ROM, and a tape streamer. The present invention relates to an interface circuit.
[0002]
[Prior art]
In recent years, IEEE (The Institute of Electrical and Electronic Engineers) 1394 and High Performance Serial Bus that realize high-speed data transfer and real-time transfer have been standardized as interfaces for multimedia data transfer.
[0003]
In the data transfer of the IEEE1394 serial interface, a transfer operation performed in the network is called a subaction and two subactions are defined.
One is a conventional Asynchronous transfer for request and acknowledge request and reception confirmation, and the other is an isochronous transfer in which data is always sent once every 125 μs from a certain node.
[0004]
In this way, data in the IEEE 1394 serial interface having two transfer modes is transferred in units of packets, but in the IEEE 1394 standard, the minimum data unit to be handled is 1 quadlet (= 4 bytes = 32 bits). It is.
[0005]
According to the IEEE 1394 standard, computer data is normally transmitted using asynchronous transfer as shown in FIG.
As shown in FIG. 7A, asynchronous transfer takes three transition states: arbitration (arb) for acquiring a bus, packet transmission for transferring data, and acknowledgment (ack).
[0006]
The packet transmission is executed in a format as shown in FIG.
The first quadlet of the transfer packet includes a 16-bit destination ID area, a 6-bit transaction label tl (transaction label) area, a 2-bit retry code rt (retry code) area, and a 4-bit transaction code tcode. ( transaction code) area and 4-bit priority pri (priority) area.
The destination ID area indicates the bus number and node number of this node, and the priority area indicates the priority level.
[0007]
The second and third quadlets have a 16-bit source ID field and a 48-bit destination offset.
offset) area.
The source ID area indicates the node ID that sent this packet, and the destination offset area is composed of continuous high and low areas, indicating the address of the destination node address space.
[0008]
The fourth quadlet is composed of a 16-bit data length area and a 16-bit extended transaction code area.
The data length area indicates the number of bytes of the received packet, and the extended tcode area indicates the actual lock action (Lock Action) performed by the data of this packet when tcode is a lock transaction. .
[0009]
The header CRC (header CRC) area added to the quadlet before the data field area is an error detection code of the packet header.
A data CRC (data CRC) area added to the quadlet after the data field is an error detection code of the data field.
[0010]
[Problems to be solved by the invention]
By the way, as described above, SBP-2 (Serial Bus Protocol-2) is used as a protocol in normal computer data transfer performed by asynchronous transfer.
According to this protocol, when data is transferred from a target (Storage Device) to a host computer (Initiator), data is written from the storage device to the host computer memory. In addition, when data is transferred from the host computer to the target, the transfer is performed in such a manner that the storage device reads the data in the memory of the host computer.
[0011]
However, a processing circuit system for controlling a so-called transaction layer for transmitting and receiving large-capacity data stored in a storage device or read from the storage device as an IEEE 1394 packet is still established. It has not been.
It is also necessary to implement a communication error detection and discrimination circuit in the transaction system.
[0012]
The present invention has been made in view of such circumstances, and an object of the present invention is to transmit / receive a large amount of data in a packet conforming to a predetermined standard, and to determine when an error occurs. An object of the present invention is to provide a serial interface circuit that can be performed and can perform smooth transmission and reception processing.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a serial interface circuit that transmits and receives packets between other nodes connected to the own node via a serial interface bus, and generates a request packet from the own node to the other node. The data processing circuit that transmits to the serial interface bus and performs reception processing for the response packet to the request packet, and determines whether or not the received response packet has an error. An error determination circuit that determines the transaction code and label in the received packet, and discriminates whether it is a response packet or other packet from the initiator to the data processing circuit that is the target, Only the response packet is input to the data processing circuit. The error determination circuit determines whether or not an appropriate response packet for the request packet has been returned. If the response packet is inappropriate, the error determination circuit is inappropriate for the transmitted request. determines that the error response packet is returned, when it is determined that has been returned appropriate response packet, the response is complete (Complete), busy (busy), different determination processing on whether it is, pending (pending) In the case of completion, it is determined whether there is a reception or transmission corresponding to the request, and in the case where the request does not correspond, it is determined that the error is a response packet that is inappropriate for the transmitted request. If it corresponds, it is determined that the error is complete, and if it is busy, a retry operation is performed to perform retransmission, and this retry count is set in advance. It is determined whether the retry limit has been reached, and if the retry limit has been reached, it is determined that the other party is busy, and in the case of pending, a response packet is received within a preset time. It is determined whether or not it is an error that the response does not return within the specified time if it is received within the specified time .
[0014]
In the present invention, the error determination circuit stops packet transmission / reception processing of the data processing circuit when an error is detected.
[0015]
In the present invention, an error register is provided, and the error determination circuit sets the error content in the error register when an error is detected.
[0016]
The present invention further includes a control circuit for initializing the data processing circuit when the error content is set in the error register.
[0017]
In the present invention, when the error determination circuit detects an error, the error detection circuit notifies the control circuit that the error has been detected, and the control circuit reads the error register upon receiving the error detection notification and performs the initialization. Process.
[0018]
Further, according to the circuit of the present invention, a request packet from the own node to another node is generated and sent to the serial interface bus in the data processing circuit.
Then, a response packet to the request packet from another node is received and predetermined processing is performed.
The response packet is also input to the error determination circuit. The error determination circuit detects whether or not there is an error in the received response packet. If there is an error, the error content is determined.
For example, when an error is detected by the error determination circuit, packet transmission / reception processing of the data processing circuit is stopped, the error content is set in the error register, and the control circuit is notified that the error has been detected. The That is, an error interrupt is performed.
Upon receiving notification of error detection, the control circuit reads the contents of the error register and performs initialization processing on the data processing circuit.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.
Note that this serial interface circuit is configured for the purpose of transferring computer data handled in asynchronous communication. For this reason, the specific configuration of the isochronous communication system circuit is not shown in FIG.
[0020]
The serial interface circuit includes a link / transaction layer integrated circuit 10, a physical layer circuit 20, a hard disk driver (HDD) controller 30 (not shown) as a storage device, and a local processor 40 as a host computer.
[0021]
The link / transaction layer integrated circuit 10 is configured by integrating the link layer circuit 100 and the transaction layer circuit 120. Under the control of the local processor 40, the asynchronous transfer control and the physical layer circuit 20 are controlled. I do.
[0022]
As shown in FIG. 1, the link layer circuit 100 includes a link core 101, a CPU interface circuit (Sub-CPU I / F) 102, and a transmission FIFO (AT-FIFO: First) used in asynchronous communication. -In First-Out) 103, a receiving FIFO (AR-FIFO) 104, a classification circuit (DeMux) 105 for discriminating a received packet, a resolver for self ID (Resolver) 106, and a control register (hereinafter referred to as CR) 107.
[0023]
The link core 101 is a transmission circuit and reception circuit for asynchronous communication packets and isochronous communication packets to which commands and computer data are transferred, and an interface circuit with a physical layer circuit 20 that directly drives the IEEE 1394 serial bus BS of these packets. It consists of a cycle timer, cycle monitor, and CRC circuit that are reset every 125 μs.
Further, it performs a transmission process of computer data read from a hard disk (not shown) and generated as a predetermined transmission packet by the transaction layer circuit 120.
For example, upon receiving notification that there is data to be sent from the transaction controller 126 of the transaction layer circuit 120, which will be described later, the 1394 serial bus is arbitrated via the physical layer circuit 20 to secure the bus.
In FIG. 1, as described above, the isochronous communication FIFO and the like are omitted.
[0024]
The CPU interface circuit 102 performs arbitration such as writing and reading of asynchronous communication packets between the local processor 40, the transmission FIFO 103, and the reception FIFO 104, and arbitration of transmission / reception of various data between the local processor 40 and the CR 107.
For example, an IEEE 1394 interface bus BS is transmitted from a host computer as an initiator, and a command for controlling a hard disk as a storage device stored in a reception FIFO is transmitted to the local processor 40.
[0025]
From the local processor 40, data for starting up the transaction layer circuit 120 to send and receive computer data is set in the CR 107 through the CPU interface 102 (ADPst = 1).
[0026]
The transmission FIFO 103 stores asynchronous communication packets to be transmitted to the IEEE 1394 serial bus BS, and the stored data is given to the link core 101.
[0027]
The receiving FIFO 104 stores the asynchronous communication packet transmitted through the IEEE 1394 serial bus BS, for example, a control command for a hard disk as a storage device, by the sorting circuit 105.
[0028]
The classification circuit 105 checks the transaction code tcode (Transaction code) and the transaction label tl (Transaction label) in the first quadred of the asynchronous communication packet via the link core 101, and the target transaction from the host computer that is the initiator. -Whether the packet is a response packet to the layer circuit (Response Packet) or other packet is classified, only the response packet is input to the transaction layer circuit 120, and the other packet is stored in the reception FIFO 104 .
[0029]
Note that the transaction label tl used for the classification check is commonly set to “a”, and tcode (Transaction code) is a write request, a response, and a read request (Read) ( Different data is set for Read request and Read response.
Specifically, tcode is set to “0” when the write request is a quadlet write and “1” when the block write is a block write.
In the case of a write response, it is set to “2”.
It is set to “4” when the read request is a quadlet read and “5” when the block read is a block read.
In the case of a read response (Read Response), it is set to “6/7”.
[0030]
The resolver 106 analyzes the self ID packet transmitted through the IEEE 1394 serial interface bus BS and stores it in the CR 107. It also has functions such as error check and node count.
[0031]
The transaction layer circuit 120 has a function of automatically transmitting and receiving data of a computer peripheral device (hard disk in the present embodiment) as an asynchronous packet based on the SBP-2 (Serial Bus Protocol-2) standard. Yes.
In addition, the transaction layer circuit 120 has a retry function and a split timeout detection function.
The retry function is a function for retransmitting a corresponding request packet when an ack busy ^* Ack code is returned after transmitting the request packet. When retransmitting a packet, the 2-bit rt region in the first quadred of the transmission packet is set from “00” to “01” to notify the core link 101 and transmit.
The split timeout detection function is a function for detecting a timeout until a response packet is returned.
[0032]
The transaction layer circuit 120 includes a transport data interface circuit 121, a request packet generation circuit (SBPreq) 122, a response packet decode circuit (SBPRsp) 123, a request FIFO (Request FIFO: ADPTF) 124, and a response FIFO (Response FIFO). : ADPRF) 125 and transaction controller 126.
The request packet generation circuit 122, the response packet decoding circuit 123, the request FIFO 124, the response FIFO 125, and the transaction controller 126 constitute a data processing circuit ADP.
[0033]
The transport data interface circuit 121 arbitrates transmission / reception of data between the HDD controller 30, the request packet generation circuit 122, and the response packet decoding circuit 123.
[0034]
When the request packet generation circuit 122 receives a data transfer activation instruction from the CR 107 of the link layer circuit 100, a hard disk (not shown) obtained via the transport data interface circuit 121 according to the SBP-2 standard in the case of transmission (writing) The computer data recorded in the packet is divided into one or more data so that it can be divided into packets, the SBP protocol address is calculated based on data such as the transfer data length set in the CR 107, and the 1394 bus increases for each packet. A 1394 header composed of four cladlets in which an address, a transaction label tl (= a), a transaction code tcode (for example, 1 or 5) and the like are added is added and stored in the request FIFO 124.
In the case of reception (reading), in accordance with the SBP-2 standard, an SBP protocol address is calculated based on data such as the transfer data length set in the CR 107, and the 1394 bus address and transaction label that increase for each packet are calculated. tl (= a), transaction code tcode (for example, 1 or 5), etc. are set, and the 1394 block read request command (Block read Request Command) for the specified address and data length is set to one or more packets for request Store in the FIFO 124.
[0035]
The request packet generation circuit 122 calculates the maximum data length of the response packet for the request packet to be transmitted in response to the maximum length data max-payload specified by the CR 107 during transmission and reception.
This maximum data length (byte) maxpl is obtained based on the following equation.
[0036]
[Expression 1]
maxpl = 2 ^{(max, Payload + 2)} (1)
[0037]
The response packet decoding circuit 123 reads the data stored in the response FIFO 125 at the time of reception, removes the 1394 header, and outputs the data to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing.
[0038]
The request FIFO 124 stores packetized transmission data at the time of transmission (writing), and stores a 1394 block read request command at the time of reception (reading).
When the data to be sent is stored, the request FIFO 124 outputs an active signal EMT to the transaction controller 126 at a low level (“0”) indicating that fact.
[0039]
In the case of reception (reading), the response FIFO 125 stores reception data transmitted from the host computer side through the 1394 serial bus BS.
The response FIFO 125 outputs a signal indicating the remaining storage capacity to the transaction controller 126.
[0040]
The transaction controller 126 transmits the packetized transmission data stored in the request FIFO 124 at the time of transmission and the link core 101 of the link layer core circuit 100 of the 1394 block read request command (request packet) stored in the request FIFO 124 at the time of reception. Control output to.
Also, upon transmission, a response packet from the classification circuit 105 of the link layer circuit 100 is received, and the retry code rcode is written to the CR 107. At the time of reception, the response packet from the classification circuit 105 is stored in the response FIFO 125.
[0041]
Further, as shown in FIG. 2, the transaction controller 126 determines whether or not there is an error in the response packet (including Acknowledge that is a reception confirmation from another node). An error determination circuit 1261 is provided for determining and stopping the processing of the request packet generation circuit 122, the response packet decoding circuit 123, the request FIFO 124, and the response packet 125 at the signal S126.
[0042]
If the write transaction (transmission) and read (receive), for acknowledgment (Acknowledge) or response packet received, there is a possibility that for example an error as shown in FIG. 3 occurs, an error determination circuit 1261, an error When it is detected, the processing of the request packet generation circuit 122, the response packet decoding circuit 123, the request FIFO 124, and the response packet 125 is stopped, and the contents of these errors are determined. For example, an error code corresponding to the contents is set. Set in the error register of CR107. When it is detected that there is an error, an interrupt bit is set in the CR 107 for an interrupt signal (Interrupt) to notify the local processor 40 that the error has been detected.
[0043]
Here, the contents of each error code in FIG. 3 will be described.
Error code ERC “0” indicates no error, “1” returns an ack code inappropriate for the transmitted request, “2” returns an ack code inappropriate for the received response, “3” No response is returned within the specified time, “4” is the retry limit count, the other party is busy even if a request packet is sent, “5” is a bus reset, “6” is an inappropriate rcode (response "7" is a response packet from a node other than the designated node, and "8" is a tcode (transaction code) different from the transaction being executed.
[0044]
Here, the operation at the time of writing (receiving) of the error discriminating circuit shown in FIG. 2 will be described with reference to the flowchart of FIG. 4, and then the normal computer data when transferring a packet determined by the SBP-2 standard is described. The transmission and reception operations will be described.
[0045]
The error determination circuit 1261 first determines whether or not an appropriate ack code (response packet) for the request packet has been returned (S1).
If the ack code is inappropriate in step S1, it is determined that the error is that an inappropriate ack code is returned in response to the request transmitted with the code “1”.
If it is determined in step S1 that the ack code has been returned appropriately, different determination processing is performed depending on whether the response is complete, busy, or pending.
[0046]
In the case of complete, it is determined whether it is a read or a write. If the response is an inappropriate response if it is a read, it is determined that the error is a code “1”, and if it is a write, the complete (S3).
[0047]
In the case of busy, a retry operation for performing retransmission is performed, and it is determined whether or not the number of retries has reached a preset retry limit (S4).
If it is determined in step S4 that the retry limit count has not been reached, the operation in step S1, that is, the request packet retransmission operation is performed.
On the other hand, if the retry limit number has been reached, it is determined that the partner is busy even if the request packet is sent the number of times of the retry limit of code “4”.
[0048]
In the case of pending, the determination operations in steps S5 to S9 are performed in order.
First, in step S5, it is determined whether or not a response packet has been received within a preset time.
In step S5, if the response packet does not return within the preset time, it is determined that the response does not return within the specified time of the code “3”.
On the other hand, if the response is returned within the specified time, the process proceeds to step S6.
[0049]
In step S6, it is determined whether or not an ack code inappropriate for the received response is returned.
In step S6, when an inappropriate ack code is returned to the received response, it is determined that the error is that an inappropriate ack code of code 2 is returned.
On the other hand, if an appropriate ack code is returned, the process proceeds to step S7.
[0050]
In step S7, it is determined whether or not an appropriate rcode (response code) has been received.
If an inappropriate rcode is received in step S7, it is determined that the error is that an inappropriate rcode of code “6” has been received.
On the other hand, if an appropriate rcode is received, the process proceeds to step S8.
[0051]
In step S8, it is determined whether or not the source ID is normal.
If it is determined in step S8 that the source ID is abnormal, it is determined that the error is a response packet received from a node other than the designated node with the code “7”.
On the other hand, if a normal source ID is received, the process proceeds to step S9.
[0052]
In step S9, it is determined whether or not the received tcode (transaction code) is normal.
If it is determined in step S9 that the received tcode is abnormal, it is determined that the error is a tcode received that is different from the transaction in which the code “8” is executed.
On the other hand, when normal tcode is received, it is processed as no error (complete).
[0053]
When it is detected that there is an error as described above, the error determination circuit 1261 outputs the signal S126 to the request packet generation circuit 122, the response packet decode circuit 123, the request FIFO 124, and the response packet 125, A process for stopping the process is performed.
An error code corresponding to the content of the error is set in the error register of the CR 107, and when an error is detected, an interrupt bit is set in the CR 107 for an interrupt signal (Interrupt). This notifies the local processor 40 that there is a request to interrupt due to an error.
As a result, the content of the CR 107 is read by the local processor 40, and an initialization (reset) process for the transaction layer circuit 120 is performed via the CR 107.
[0054]
Next, normal transmission and reception operations of computer data when a packet determined by the SBP-2 standard is transferred in the above configuration will be described.
[0055]
First, a transmission operation, that is, a case in which data is transferred from a target hard disk to an initiator host computer and data is written from a storage device (hard disk) to a memory of the host computer will be described.
[0056]
Packet data such as ORB ( Operation Request Block) based on the SBP-2 standard transferred from the host computer via the 1394 serial bus BS is separated via the physical layer circuit 20 and the link core 101 of the link layer circuit 100. 105 is input.
[0057]
The classification circuit 105 receives the received packet and classifies whether it is a response packet (Response Packet) or other packet from the host computer to the target transaction layer circuit.
In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
Reception data such as ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102.
In the local processor 40, the transaction layer circuit register of the CR 107 is initialized according to the contents of the ORB through the CPU interface circuit 102.
As a result, the transaction layer circuit 120 is activated.
[0058]
In the activated transaction layer circuit 120, the request packet generation circuit 122 starts a request for data to the HDD controller 30 via the transport interface 121.
In response to the request, the transmission data sent via the transport interface 121 is computer data recorded on a hard disk (not shown) obtained via the transport data interface circuit 121 according to the SBP-2 standard in the request packet generation circuit 122. The SBP protocol address is calculated based on the data such as the transfer data length set in the CR 107, and the 1394 bus address and the transaction label tl are increased for each packet. (= A), a transaction code tcode (for example, 1 or 5) and the like, a 1394 header composed of 4 gradlets is added and stored in the request FIFO 124.
[0059]
When data of one 1394 packet size or larger is stored in the request 1 FIFO 124, the data is sent to the link core 101 of the link layer circuit 100 by the transaction controller 126.
The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20.
Thus, if the bus is acquired, a write request packet including the transfer data is transmitted to the host computer via the physical layer circuit 20 and the 1394 serial bus BS.
[0060]
After transmission, an Ack code for the write request packet and, in some cases, a write response packet are sent from the host computer, and are sorted via the physical layer circuit 20 and the link core 101 of the link layer circuit 100. Input to the circuit 105.
[0061]
In the classification circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and if it is determined that the response packet is a response packet (Response Packet) from the host computer to the target transaction layer circuit 120, The response packet is input to the transaction controller 126 of the transaction layer circuit 120.
[0062]
In the transaction controller 126, if the Ack code and the response code of the input response packet are normal, the next data is sent to the link core 101.
The above operation is repeated, and the operation of writing (sending) computer data to the memory of the host computer is performed.
[0063]
FIG. 4 shows an outline of the operation of the transaction layer circuit 120 relating to the above transmission.
[0064]
Next, a reception operation, that is, a case where the storage device (hard disk) reads data from the memory of the host computer when data is transferred from the host computer to the target will be described.
[0065]
Packet data such as ORB ( Operation Request Block) based on the SBP-2 standard transferred from the host computer via the 1394 serial bus BS is separated via the physical layer circuit 20 and the link core 101 of the link layer circuit 100. 105 is input.
[0066]
The classification circuit 105 receives the received packet and classifies whether it is a response packet (Response Packet) or other packet from the host computer to the target transaction layer circuit.
In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
Reception data such as ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102.
In the local processor 40, the transaction layer circuit register of the CR 107 is initialized according to the contents of the ORB through the CPU interface circuit 102.
As a result, the transaction layer circuit 120 is activated.
[0067]
In the activated transaction layer circuit 120, the request packet generation circuit 122 calculates the address of the SBP protocol based on data such as the transfer data length set in the CR 107 in accordance with the SBP-2 standard, and increases for each packet. A 1394 bus address, a transaction label tl (= a), a transaction code tcode (for example, 1 or 5), etc. are set, and a 1394 block read request command (Block read Request Command) corresponding to the specified address and data length is packetized. And stored in the request FIFO 124.
[0068]
The read request command packet stored in the request FIFO 124 is sent to the link core 101 of the link layer circuit 100 by the transaction controller 126.
The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20.
As a result, if the bus is acquired, a read request packet is transmitted to the host computer via the physical layer circuit 20 and the 1394 serial bus BS.
[0069]
After transmission, an Ack code for the read request packet and a read response packet (Read Response Packet) including data for the specified data length are sent from the host computer, and the physical layer circuit 20 and the link layer circuit 100 are sent. Are input to the sorting circuit 105 via the link core 101.
[0070]
In the classification circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and if it is determined that the response packet is a response packet (Response Packet) from the host computer to the target transaction layer circuit, The response packet is input to the transaction controller 126 of the transaction layer circuit 120.
[0071]
In the transaction controller 126, the response packet from the classification circuit 105 is stored in the response FIFO 125.
The data stored in the response FIFO 125 is read by the response packet decoding circuit 123, the 1394 header is removed, and the data is output to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing.
The above operation is repeated, and the operation of writing (receiving) computer data to the storage device (hard disk) is performed.
[0072]
FIG. 5 shows an outline of the operation of the transaction layer circuit 129 related to the above reception.
[0073]
As described above, according to the present embodiment, the storage device is connected, reads the data of the storage device, adds a self-designated transaction label, sends it to the serial interface bus BS as a transmission asynchronous packet, and When transferring data to the storage device, a request packet with a self-designated label is generated and sent to the serial interface bus BS, a response packet to this request packet from another node is received, and the data from the response packet Since the transaction layer circuit 120 is provided as a data processing circuit for taking out the data and transferring it to the storage device, large-capacity data stored in or read from the storage device can be stored in the SBP-2 standard. Combined with the IEEE1394 packet can be transmitted and received, it is possible to realize a large data transfer using an asynchronous packet of IEEE1394 serial bus interface.
The sequence of ORB fetch, data transfer, and status transmission to the initiator based on the SBP-2 standard can be simplified, and it is optimal for connecting computer peripheral data such as disk drivers and tape streamers to the IEEE 1394 serial bus. Design becomes possible.
[0074]
Also, it is determined whether or not there is an error in the response packet. If there is an error, the error content is determined, and the request packet generation circuit 122, response packet decode circuit 123, request FIFO 124, and response packet 125 are processed. Since the error discriminating circuit 1261 is stopped by the signal S126, the discriminating can be performed when an error occurs, and the addition of the control system circuit can be reduced, and the accurate transmission / reception processing can be performed.
[0075]
Further, since the requesting FIFO 124 and the response FIFO 125 are provided in the transaction layer circuit 120, and the transmission FIFO 103 and the receiving FIFO 104 are provided in the link layer circuit 100, data exchange by the requesting FIFO 124 and the response FIFO 125 is performed in parallel. Thus, normal 1394 packets other than data can be transmitted and received.
[0076]
In addition, the transaction code tcode (Transaction code) and the transaction label tl (Transaction label) in the first quadred of the packet for asynchronous communication through the link core 101 are checked, and the target transaction layer circuit is transmitted from the initiator host computer. Is a response packet (Response Packet) or other packet, and only the response packet is input to the transaction layer circuit 120, and the other packet is stored in the reception FIFO 104. For example, even if a fatal error occurs on the transaction layer circuit 120 side and the data read / write operation stops, the next input command of data can be read. No Rukoto, there is an advantage that the reception of the no command regardless of the data read / write status can be smoothly performed.
[0077]
【The invention's effect】
As described above, according to the present invention, not only can a large amount of data be transmitted and received in packets conforming to a predetermined standard, but also when an error occurs, the determination can be made. The addition of a circuit can be reduced, and an accurate transmission / reception process can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.
FIG. 2 is a block diagram showing an error determination circuit according to the present invention.
FIG. 3 is a diagram illustrating an example of an error code.
FIG. 4 is a flowchart for explaining an error determination operation;
FIG. 5 is a diagram showing an outline of a transmission operation in a transaction layer circuit according to the present invention.
FIG. 6 is a diagram showing an outline of a reception operation in a transaction layer circuit according to the present invention.
FIG. 7 is a diagram for explaining asynchronous transfer of the IEEE 1394 standard.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Link / transaction layer integrated circuit, 20 ... Physical layer circuit, 30 ... HDD controller, 40 ... Local processor, 100, 100a ... Link layer circuit, 101 ... Link core, 102 ... CPU interface circuit, 103 ... Asynchronous transmission Trust FIFO, 104 ... Asynchronous reception FIFO, 105, 105a ... Sorting circuit, 106 ... Resolver, 107 ... Control register, 120 ... Transaction layer circuit, 121 ... Transport data interface circuit, 121 ... Request packet generation circuit, 123 ... Response packet decoding circuit 124... Request FIFO 125. Response FIFO 126 126 Transaction controller 1261 Error determination circuit

Claims (8)

A serial interface circuit that transmits and receives packets between other nodes connected to the local node via a serial interface bus,
A data processing circuit that generates a request packet from the own node to another node, sends the request packet to the serial interface bus, and performs a reception process on a response packet to the request packet
An error determination circuit that determines whether or not there is an error in the received response packet, and if there is an error, determines an error content ;
The transaction code and label in the received packet are checked, the response packet from the initiator to the data processing circuit that is the target is distinguished from other packets, and only the response packet is sent to the data processing circuit. A separation circuit to be input to
The error discrimination circuit
It is determined whether or not an appropriate response packet for the request packet has been returned, and if it is an inappropriate response packet, it is determined that the error is that an inappropriate response packet has been returned for the transmitted request.
When determining that has been returned appropriate response packet, the response is complete (Complete), busy (Busy), performs a different determination processing on whether it is, pending (Pending),
In the case of complete, it is determined whether there is reception or transmission corresponding to the request. In the case where the request does not correspond, it is determined that an error response packet is returned in response to the transmitted request, and the request is responded. If it is, determine that the error is complete and
In the case of busy, a retry operation for performing retransmission is performed, it is determined whether or not the number of retries has reached a preset retry limit, and the partner is busy if the retry limit has been reached. Determined as an error,
In the case of pending, it is determined whether or not the response packet is received within a preset time, and if it is received within the time, it is determined that the error is that the response does not return within the specified time. Serial interface circuit. The serial interface circuit according to claim 1, wherein the error determination circuit stops packet transmission / reception processing of the data processing circuit when an error is detected. Has an error register,
The serial interface circuit according to claim 1, wherein the error determination circuit sets an error content in the error register when an error is detected. Has an error register,
The serial interface circuit according to claim 2, wherein when an error is detected, the error determination circuit sets an error content in the error register. The serial interface circuit according to claim 3, further comprising a control circuit that initializes the data processing circuit when an error content is set in the error register. The serial interface circuit according to claim 4, further comprising: a control circuit that initializes the data processing circuit when an error content is set in the error register. When the error determination circuit detects an error, it notifies the control circuit that the error has been detected,
The serial interface circuit according to claim 5, wherein the control circuit reads the error register upon receiving notification of error detection and performs the initialization process. When the error determination circuit detects an error, it notifies the control circuit that the error has been detected,
The serial interface circuit according to claim 6, wherein the control circuit reads the error register upon receiving notification of error detection and performs the initialization process.

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