JPH1117710A - Serial interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial interface circuit with which the data of a large capacitance can be transmitted/received while being made into packet matched with a prescribed standard and smooth transmission/reception processing is enabled in high efficiency in use. SOLUTION: A transaction layer circuit 120 is provided with a 1st FIFO 124 having a large storage capacitance and a 2nd FIFO 125 having a small storage capacitance, and at the same time, selectors 127-130 are provided for storing the packet of a large capacitance containing data in the 1st FIFO 124 at the time of transmission (write) operation and reception (read) operation, storing the packet of a small capacitance containing no data in the 2nd FIFO 125 and reading them. Thus, when transmitting/receiving the data of a large capacitance, the FIFO can be efficiently used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital serial interface circuit, and more particularly to a hard disk drive (HDD).
Drive), DVD (Digital Video Disk) -ROM, CD
(Compact Disk)-ROM, Tape Streamer
The present invention relates to a serial interface circuit connected to a storage device such as an amer) and a signal processing method thereof.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

In the data transfer of the IEEE 1394 serial interface, a transfer operation performed in a network is called a subaction, and two subactions are defined. One is conventional Request, Acknow
Asynchronous (Asynchr) for requesting and confirming receipt of ledge
onous) forwarding, and the other is 125
Isochronous (Isoch) where data is always sent once every μs
ronous) Transfer.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Although transfer is performed in packet units, in the IEEE 1394 standard, the minimum data unit handled is one quadlet (q
uadlet) (= 4 bytes = 32 bits).

[0005] In the IEEE 1394 standard, computer data is normally transmitted using asynchronous transfer as shown in FIG. Asynchronous transfer is shown in FIG.
As shown in (a), there are three transition states: arbitration (arb) for acquiring a bus, packet transmission for transferring data, and acknowledgment (ack).

The execution of packet transmission is performed in a format as shown in FIG. The first quadlet of the transfer packet includes a 16-bit destination ID (destination ID) area and a 6-bit transaction label tl (transaction label).
l) area, 2-bit retry code rt (retry cod
e) area, 4-bit transaction code tcod
An e (transanction code) area and a 4-bit priority pri (priority) area. The destination ID area indicates the bus number and node number of this node, and the priority area indicates the priority level.

[0007] The second and third quadlets have a 16-bit source ID area and a 48-bit destination offset (destina- tion).
tionoffset) region. The source ID area shows the ID of the node that sent this packet, and the destination offset area shows high (High) and low (L
ow), and indicates the address of the address space of the destination node.

[0008] The fourth quadlet is composed of a 16-bit data length area and a 16-bit extended transaction code (extended tcode) area. The data length field indicates the number of bytes of the received packet, and the extended tcode field is tc.
mode is a Lock transaction
If, the actual locking action performed by the data in this packet
(Lock Action).

[0009] A header CRC (header CRC) added to the quadlet before the data field area (data field)
The area is an error detection code of the packet header. Also,
A data CRC (data CRC) area added to the quadlet after the data area (data field) is an error detection code of the data field.

[0010]

As described above, in the normal computer data transfer performed by the asynchronous transfer, the SBP-based protocol is used as the protocol.
2 (Serial Bus Protocol-2) is used. According to this protocol, a host device (Host) is transferred from a target (Target) that is a storage device.
When transferring data to the initiator, which is a Computer, the data is written from the storage device to the memory of the host computer, and when transferring the data from the host computer to the target,
The transfer is performed in such a manner that the storage device reads the data in the memory of the host computer.

However, a processing circuit system for controlling a so-called transaction layer for transmitting and receiving a large amount of data stored in or read from the storage device in packets of the IEEE 1394 standard. Has not yet been established. Also, it is necessary to realize a circuit system with good use efficiency in configuring an LSI.

The present invention has been made in view of the above circumstances, and has as its object to transmit and receive large-capacity data in packets conforming to a predetermined standard. An object of the present invention is to provide a serial interface circuit that can be used efficiently.

[0013]

In order to achieve the above object, the present invention relates to a serial interface circuit for transmitting and receiving asynchronous packets between a self-node and another node connected via a serial interface bus. 1 storage means, a second storage means having a storage capacity smaller than that of the first storage means, a self-designated label is added to the read data to generate a transmission packet, and data of another node is transmitted to the own node. When transferring, a transmission packet generation circuit that generates a request packet to which a self-designated label is added, and when transferring read data to another node, a transmission packet including the data generated by the transmission packet generation circuit is transmitted. When the data is stored in the first storage means and the data of the other node is transferred to the own node, the transmission packet generation circuit uses Selecting means for storing the generated request packet in the second storage means, and storing at least a data portion of the response packet in the first storage means when a response packet to the request packet from another node is received; A first data transfer circuit for transmitting a transmission packet containing data stored in the first storage means or a request packet stored in the second storage means to the serial interface bus; A second data transfer circuit for transferring the data of the response packet stored in the means.

Further, the present invention has a control circuit which receives a control packet from another node and instructs the selecting means to store the data and the request packet in accordance with the content of the control packet.

Further, in the present invention, the transmission packet generation circuit divides the read data into a plurality of data, adds the label to each of the divided data, and transfers the data of another node to its own node. Are generated and transmitted to the serial interface bus so that a plurality of request packets each having a specified label can be transmitted.

The first data transfer circuit receives a response packet to a transmission packet from the other node, and sends a next transmission packet to the serial interface bus when the response packet is normal.

According to the circuit of the present invention, for example, in the case of a transfer request of the storage device data from the own node to another node, the data of the storage device is read by the transmission packet generation circuit. Next, a self-designated label is added to the read data, and the read data is stored in the first storage unit having a large storage capacity by the selection unit. Then, the transmission packet including the data stored in the first storage means is transmitted to the serial interface bus by the first data transfer circuit.

When transferring data from another node to the own node, a request packet is generated by the transmission packet generation circuit and stored in the second storage means having a small storage capacity. Then, the second data is transferred by the first data transfer circuit.
Is transmitted to the serial interface bus. When a response packet to the request packet is sent from the serial interface bus, at least the data portion of the response packet is stored in the first storage unit having a large storage capacity by the selection unit. Then, the data of the response packet stored in the first storage means is transferred to the storage device by the second data transfer circuit.

Further, when a control packet from another node is input to the control circuit, the control circuit transmits the transmission data or the reception data to the selecting means in accordance with the content of the control packet to the first unit having a large storage capacity. , And an instruction to store the request packet in the second storage unit having a small storage capacity.

In the transmission packet generation circuit,
The read data is divided into a plurality of data, and a label is added to each divided data. Also, when transferring data of another node to the own node, a plurality of request packets with designated labels are generated so that the data can be packetized and transferred. In these cases, the first data transfer circuit receives the response packet to the transmission packet from the other node and, if normal, receives the transmission packet containing the next data stored in the first storage means or the next request packet. The packet is sent out on the serial interface bus.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an IEEE 1 according to the present invention.
FIG. 3 is a block diagram illustrating an embodiment of a 394 serial interface circuit. This serial interface circuit is configured to transfer computer data handled in asynchronous communication. Therefore, FIG. 1 does not show a specific configuration of the isochronous communication system circuit.

This serial interface circuit comprises a link / transaction layer integrated circuit 10, a physical layer circuit 20, a hard disk driver (HDD) controller 30 (not shown) as a storage device, and a local processor 40 as a host computer. I have.

The link / transaction layer integrated circuit 10 is constructed by integrating the link layer circuit 100 and the transaction layer circuit 120, and controls the asynchronous transfer under the control of the local processor 40 and the physical layer circuit. 20.

As shown in FIG. 1, the link layer circuit 100 includes a link core (Link Core) 101, a CPU interface circuit (Sub-CPU I / F) 102, and a transmission FIFO (AT-AT) used for asynchronous communication. FIFO: First-In F
irst-Out) 103, receiving FIFO (AR-FIFO) 104,
Classification circuit (DeMux) 105 for discriminating received packets, resolver for self ID (Resolver) 106, and control register (ControlRegisters, hereinafter referred to as CR) 1
07.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets to which commands and computer data are transferred, and a physical layer circuit 20 for directly driving these packets on the IEEE 1394 serial bus BS. It is composed of an interface circuit, a cycle timer reset every 125 μs, a cycle monitor and a CRC circuit. Further, it performs a transmission process of computer data read from a hard disk (not shown) and generated by the transaction layer circuit 120 as a predetermined transmission packet. In FIG. 1, the FIFO and the like of the isochronous communication system are omitted as described above.

The CPU interface circuit 102 includes a local processor 40, a transmission FIFO 103, and a reception FIFO.
It performs arbitration such as writing and reading of asynchronous communication packets with the IFO 104 and arbitration of transmission and reception of various data between the local processor 40 and the CR 107. For example, a host computer as an initiator transmits an IEEE 1394 interface bus BS, and transmits a command for controlling a hard disk as a storage device stored in a reception FIFO to the local processor 40. Then, from the local processor 40, data for activating the transaction layer circuit 120 for transmitting and receiving computer data is set in the CR 107 through the CPU interface 102.

Further, from the local processor 40,
As described later, the operation mode in the transaction layer circuit 120, specifically, a write (transmit) operation for transferring data of the hard disk from the own node to another node and a read (receive) operation for transferring data from the other node to the own node. A data bit (direction bit; hereinafter, referred to as d bit) used for controlling switching between FIFOs having different storage capacities according to the
Set to 7. For example, during a write (transmit) operation, the d bit is set to "1" and a read (receive) is performed.
In operation, it is set to "0".

The transmission FIFO 103 includes IEEE13
Asynchronous communication packets to be transmitted to the N. 94 serial bus BS are stored.
Given to.

Also, the receiving FIFO 104 is an IEEE
Asynchronous communication packets transmitted through the 1394 serial bus BS, for example, commands for controlling a hard disk as a storage device and the like are stored by the classification circuit 105.

The discrimination circuit 105 has a transaction code tcode (Transaction code) in the first quadred of the asynchronous communication packet via the link core 101.
code) and transaction label tl (Transaction
label), discriminates whether the packet is a response packet (Response Packet) from the initiator host computer to the target transaction layer circuit or other packets, and only the response packet is transferred to the transaction layer circuit. The packet is input to the circuit 120, and the other packets are stored in the reception FIFO 104.

The transaction label tl used for the sorting check is set to "a" in common, and t
In the code (Transaction code), different data is set for a write request (request) and response (Response), and for a read (Read) request (Read request) and response (Read Response). Specifically, tcode
Is set to "0" in the case of a quadlet write in a write request and "1" in the case of a block write.
"2" for a write response
Is set to It is set to "4" in the case of a quadlet read in a read request (Read request), and is set to "5" in the case of a block read (Block Read). In the case of a read response (Read Response), it is set to “6/7”.

The resolver 106 receives the self-I data transmitted through the IEEE 1394 serial interface bus BS.
The D packet is analyzed and stored in the CR 107. It also has functions such as error checking and counting the number of nodes.

The transaction layer circuit 120
It has a function of automatically transmitting and receiving data of a computer peripheral device (a hard disk in this embodiment) as an asynchronous packet based on the SBP-2 (Serial Bus Protocol-2) standard. Further, the transaction layer circuit 120 has a retry function and a split timeout detection function. The retry function is a function of retransmitting the corresponding request packet when an ack busy ^* Ack code is returned after transmitting the request packet. When retransmitting a packet, the 2-bit rt area in the first quadred of the transmission packet is set from “00” to “01” before transmission. Split timeout
imeout) The detection function is a function to detect a timeout until a response packet is returned.

This transaction layer circuit 120
Is a transport data interface circuit 121,
Request packet generating circuit (SBPreq) 122, response packet decoding circuit (SBPRsp) 123, first FIFO (FIFO-A) 12
4, a second FIFO (FIFO-B) 125, a transaction controller 126, and selectors 127 to 130. Then, the request packet generation circuit 12
2. Response packet decoding circuit 123, first FIFO 1
24, a second FIFO 125, a transaction controller 126, and selectors 127 to 130 constitute a data processing circuit ADP.

The transport data interface circuit 121 arbitrates the transmission and reception of data between the HDD controller 30, the request packet generation circuit 122, and the response packet decode circuit 123.

The request packet generation circuit 122 has a link
Upon receiving a data transfer start instruction from the CR 107 of the layer circuit 100, in the case of transmission (write), the transport data interface circuit 1 according to the SBP-2 standard.
21 so that the computer data recorded on a hard disk (not shown) obtained through
Divided into at least data and the transaction label tl
(= A) and the like are added and output to the selectors 127 and 128. Also receive (read)
In the case of (1), according to the SBP-2 standard, a 1394 block read request command (Block read Request Command) corresponding to the specified address and data length is packetized by specifying one or more transaction labels tl (= a) and the like. To the selectors 127 and 128.

The response packet decoding circuit 123 reads the response packet stored in the first FIIFO 124 at the time of reception, removes the 1394 header from the read packet, and sends the data to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing. Output.

The first FIFO 124 has a storage capacity of 2 kB, for example, and stores packetized transmission data through the selector 127 in the case of transmission (write), and the host in the case of reception (read) through the selector 127. The received data transmitted from the computer through the 1394 serial bus BS is stored.

The second FIFO 125 has a capacity equal to that of the first FIFO.
A capacity smaller than the storage capacity of the IFO 124, for example, 48
In the case of reception (reading), a 1394 block read request command is stored through the selector 128. In addition, transmission (writing)
In this case, the second FIFO 125 is not used. That is, a response packet containing no data is not stored by the transaction controller 126. However,
The response packet not including this data is sent to the second FIFO 12
5 can be stored.

The transaction controller 126
The packetized transmission data stored in the first FIFO 124 at the time of transmission and the 1394 block read request command stored in the second FIFO 125 at the time of reception are read through the selector 130, and output control to the link core 101 of the link layer core circuit 100 is performed. . At the time of transmission, the classification circuit 1 of the link layer circuit 100
The retry code rcode is written in the CR 107 upon reception of the response packet from the receiver 05, the 1394 header is removed from the response packet from the classification circuit 105 upon reception, and the packet data is passed through the selector 127 to the first F
It is stored in the IFO 124.

The selectors 127 to 130 have two input terminals of "0" and "1" (hereinafter referred to as "0 terminal" and "1 terminal" and are represented by "0" and "1" in FIG. 1).
And the transaction layer circuit 120 according to the setting data of the control register (CR) 107.
Is activated, either the input to the 0 terminal or the input to the 1 terminal is selected and output according to the value of the d bit set in the CR 107. Specifically, the input to the terminal 1 is selected during a write (transmit) operation in which the d bit is “1”, and the input to the terminal 0 is performed in a read (receive) operation in which the d bit is “0”. Select input.

One terminal of the selector 127 is connected to the output terminal of the request packet generation circuit 122, the zero terminal is connected to the output terminal of the transaction controller 126 to the response side FIFO, and the output terminal is connected to the input terminal of the first FIFO 124. It is connected. The 0 terminal of the selector 128 is connected to the output terminal of the request packet generation circuit 122,
The terminal is connected to the output terminal to the FIFO side of the response system of the transaction controller 126, and the output terminal is
It is connected to the input terminal of the IFO 125. Selector 1
29 terminals are connected to the output terminal of the first FIFO 124, 1 terminal is connected to the output terminal of the second FIFO 125, and the output terminal is connected to the input terminal of the response packet decoding circuit 123. One terminal of the selector 130 is the first
Connected to the output terminal of the FIFO 124,
The output terminal is connected to the output terminal of the IFO 125, and the output terminal is connected to the request input terminal of the transaction controller 126.

FIG. 2 shows a connection mode between the FIFO by the selector in the transaction layer circuit 120, the transmission packet generation circuit 122, the response packet decoding circuit 123, and the transaction controller 126 during the transmission operation and the reception operation. In FIG. 2, (a) shows a connection mode at the time of transmission operation, and (b) shows a connection mode at the time of reception operation.

Next, the operation of transmitting and receiving computer data in the case of transferring a packet determined by the SBP-2 standard in the above configuration will be described.

First, a transmission operation, that is, a case where data is transferred from a target hard disk to a host computer which is an initiator and an operation of writing data from a storage device (hard disk) to a memory of the host computer is performed will be described. I do.

An O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB (Operation Request Block) is transmitted to the physical layer circuit 20 and the link layer circuit 10
0 is input to the classification circuit 105 via the link core 101 of 0.

Upon receiving the received packet, the classification circuit 105 receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. In parallel with this initialization, the local processor 40 sets the d bit for controlling the switching between FIFOs having different storage capacities in accordance with the transmission operation and the reception operation in the transaction layer circuit 120 to "1". You.

As a result, the transaction layer circuit 120 is activated, and the selectors 127 to 130 select the input to one terminal. That is,
As shown in FIG. 2A, the request packet generation circuit 122
Output packet is the first FIFO 124 having a large storage capacity.
And the data stored in the first FIFO 124 is input to the transaction controller 126.

In the activated transaction layer circuit 120, the request packet generation circuit 122 starts a data request to the HDD controller 30 via the transport interface 121. The transmission data transmitted via the transport interface 121 in response to the request is transmitted to the request packet generation circuit 1.
At 22, the data is divided into one or more pieces of data so as to be divided into packets according to the SBP-2 standard, a 1394 header in which a transaction label tl (= a) or the like is specified is added, and the first FI
It is stored in the FO 124.

When data equal to or larger than one 1394 packet size is stored in the first FIFO 124, the data is sent to the link core 101 of the link layer circuit 100 by the transaction controller 126. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20. As a result, if the bus can be obtained, a write request packet including the transfer data is obtained.
(Write Request Packet) is a physical layer circuit 2
0, transmitted to the host computer via the 1394 serial bus BS.

After transmission, an Ack code for a write request packet and a write response packet (Write Response Packet) are transmitted from the host computer, and the physical layer circuit 20 and the link core 101 of the link layer circuit 100 are transmitted. Classification circuit 10 via
5 is input.

In the classification circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and the host computer supplies the transaction layer circuit 12 as a target.
If the response packet is determined to be a response packet (Response Packet) for the
Transaction controller 12 of layer circuit 120
6 is input.

In the transaction controller 126, if the Ack code and the response code (Response code) of the input response packet are normal, the next data is transmitted to the link core 101. By repeating the above operation, the operation of writing (transmitting) the computer data to the memory of the host computer is performed.

FIG. 3 shows an outline of the operation of the transaction layer circuit 120 for the above transmission.

Next, a receiving operation, that is, a case where data is transferred from the host computer to the target and an operation in which the storage device (hard disk) reads data from the memory of the host computer will be described.

An O based on the SBP-2 standard transmitted from the host computer via the 1394 serial bus BS.
Packet data such as RB is a physical layer circuit 2
0, which is input to the classification circuit 105 via the link core 101 of the link layer circuit 100.

The classification circuit 105 receives the received packet and receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or other packets. In this case, the received data is stored in the receiving FIFO 104 because it is another packet.
The reception data such as the ORB stored in the reception FIFO 104 is input to the local processor 40 via the CPU interface circuit 102. Local processor 4
At 0, OR is output via the CPU interface circuit 102.
According to the contents of B, the register for the transaction layer circuit of the CR 107 is initialized. In parallel with this initialization, the local processor 40 sets the d bit to "0" for controlling switching between FIFOs having different storage capacities according to the transmission operation and the reception operation in the transaction layer circuit 120. You.

As a result, the transaction layer circuit 120 is activated, and the selectors 127 to 130 select the input to the 0 terminal. That is,
As shown in FIG. 2B, the request packet generation circuit 122
Output packet is a second FIFO 125 having a small storage capacity.
The response data (or only data) including the data input to the transaction controller 126 is stored in the first FIFO 124 having a large storage capacity, and the data stored in the first FIFO 124 is stored in the second FIFO 125. Is input to the response packet decoding circuit 123.

In the activated transaction layer circuit 120, the request packet generation circuit 122
According to the BP-2 standard, a 1394 block read request command (Block rea
d Request Command) is packetized and the selector 128
Through the second FIFO 125.

The read request command packet stored in the second FIFO 125 is sent to the link core 101 of the link layer circuit 100 by the transaction controller 126. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20.
As a result, if the bus is acquired, a read request packet (Read Request Packet) is transmitted to the host computer via the physical layer circuit 20 and the 1394 serial bus BS.

After the transmission, an Ack code for the read request packet from the host computer and a read response packet (Read R) including data of the designated data length.
esponse Packet) is sent to the physical layer circuit 20 and the link core 10 of the link layer circuit 100.
The signal is input to the classification circuit 105 through the line 1.

In the sorting circuit 105, the transaction code tcode and the transaction label tl of the received packet are checked, and it is determined that the received packet is a response packet (Response Packet) from the host computer to the target transaction layer circuit. Then, the response packet is input to the transaction controller 126 of the transaction layer circuit 120.

In the transaction controller 126, the response packet data from the classification circuit 105 is stored in the first FIFO 124 through the selector 127. The data stored in the first FIFO 124 is read by the response packet decoding circuit 123 through the selector 129 to remove the 1394 header, and is output to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing. By repeating the above operation, the operation of writing (receiving) the computer data to the storage device (hard disk) is performed.

FIG. 4 shows an outline of the operation of the transaction layer circuit 129 relating to the above reception.

As described above, according to the first embodiment, a storage device is connected, data in the storage device is read, a self-designated transaction label is added, and a transmission asynchronous packet is transmitted to the serial interface bus BS. When transmitting and transferring data of another node to the storage device, a request packet with a self-designated label is generated and transmitted to the serial interface bus BS, and a response packet to this request packet from another node is received. And a transaction as a data processing circuit for extracting a data portion from the response packet and transferring the data portion to the storage device.
Since the layer circuit 120 is provided, the large-capacity data stored in or read from the storage device can be converted into an IE conforming to the SBP-2 standard.
EE1394 packets can be transmitted and received.
Large-capacity data transfer can be realized by using asynchronous packets of the IEEE 1394 serial bus interface. And O based on the SBP-2 standard.
Sequences such as RB fetch, data transfer, and status transmission to the initiator can be simplified, and an optimum design can be made when data of a computer peripheral device such as a disk driver and a tape streamer is connected to the IEEE 1394 serial bus.

Further, the transaction layer circuit 1
20 is provided with a first FIFO 124 having a large storage capacity and a second FIFO 125 having a small storage capacity, and at the time of transmission (write) operation and reception (read) operation,
A large-capacity packet including data is transferred to the first FIFO 12
4 and the selectors 127 to 130 for storing and reading out small packets containing no data in the second FIFO 125, so that the FIFO can be used efficiently when transmitting and receiving large amounts of data. As a result, an increase in the number of gates due to unnecessary FIFO capacity can be suppressed.

Further, the transaction layer circuit 1
20 is provided with a first FIFO 124 and a second FIFO 125 and the link layer circuit 100
Since the FIFO 103 and the receiving FIFO 104 are provided, the normal FIFO other than the data is transferred in parallel with the exchange of the data by the first FIFO 124 and the second FIFO 125.
394 packets can be transmitted and received.

Also, the transaction code tcode (Transaction code) and the transaction label tl (Transaction label) in the first quadrant of the asynchronous communication packet via the link core 101 are checked, and the host computer serving as the initiator checks the target transaction. Discriminating whether the packet is a response packet (Response Packet) to the layer circuit or another packet, input only the response packet to the transaction layer circuit 120, and store the other packet in the reception FIFO 104 Since the classification circuit 105 is provided, even if a fatal error occurs in the transaction layer circuit 120 and the data read / write operation is stopped, for example, the read command of the next input command of the data is read. Without becomes possible out, there is an advantage that the reception of the no command regardless of the data read / write status can be smoothly performed.

[0069]

As described above, according to the present invention,
It is possible to realize a serial interface circuit that can transmit and receive a large amount of data in packets conforming to a predetermined standard and that can perform smooth transmission and reception processing with good use efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an IEEE 1394 serial interface circuit according to the present invention.

FIG. 2 shows a FIFO by a selector in a transaction layer circuit during a transmission operation and a reception operation.
And a transmission packet generation circuit, a response packet decoding circuit,
FIGS. 3A and 3B are diagrams illustrating a connection configuration with a transaction controller. FIG. 3A illustrates a connection configuration during a transmission operation, and FIG. 3B illustrates a connection configuration during a reception operation.

FIG. 3 is a diagram schematically illustrating a transmission operation in the transaction layer circuit according to the present invention.

FIG. 4 is a diagram schematically illustrating a receiving operation in the transaction layer circuit according to the present invention.

FIG. 5 is a diagram for explaining asynchronous transfer of the IEEE 1394 standard.

[Explanation of symbols]

10 link / transaction layer integrated circuit, 20
... Physical layer circuit, 30 ... HDD controller, 40 ... Local processor, 100, 100a ... Link layer circuit, 101 ... Link core, 102 ... CP
U interface circuit, 103: Asynchronous transmission FIFO, 104: Asynchronous reception FIFO, 1
05, 105a: Classification circuit, 106: Resolver, 107
... Control register, 120 ... Transaction
Layer circuit, 121: transport data interface circuit, 121: request packet generation circuit, 123: response packet decoding circuit, 124: first FIFO, 12
5: second FIFO, 126: transaction controller, 127 to 130: selector.

Claims (5)

[Claims] 1. A serial interface circuit for transmitting and receiving asynchronous packets between a self-node and another node connected via a serial interface bus, wherein the first storage means has a storage capacity of the first storage means. A second storage means smaller than the above, a transmission packet is generated by adding a self-designated label to the read data, and a request packet with the self-designated label is added when transferring data of another node to the own node. A transmission packet generation circuit to generate, and when transferring the read data to another node, store the transmission packet including the data generated by the transmission packet generation circuit in the first storage means, and store the data of the other node. When transferring the request packet to the own node, the request packet generated by the transmission packet generation circuit is stored in the second storage means. Selecting means for storing at least a data portion of a response packet in the first storage means when a response packet to a request packet from another node is received; and data stored in the first storage means A first data transfer circuit for sending a transmission packet or a request packet stored in the second storage means to the serial interface bus; and a second data transfer circuit for transferring data of a response packet stored in the first storage means. And a data transfer circuit. 2. The serial interface circuit according to claim 1, further comprising a control circuit for receiving a control packet from another node and instructing said selecting means to store the data and the request packet in accordance with the content of the control packet. . 3. The transmission packet generation circuit divides read data into a plurality of data, adds the label to each of the divided data, and packetizes the data when transferring data of another node to the own node. 2. The serial interface circuit according to claim 1, wherein a plurality of request packets each specifying a label are generated and transmitted to the serial interface bus so that the request packets can be transferred. 4. The serial communication device according to claim 3, wherein said first data transfer circuit receives a response packet to a transmission packet from said other node, and sends a next transmission packet to said serial interface bus when normal. Interface circuit. 5. The apparatus according to claim 1, wherein said first and second storage means include an FI
2. The serial interface circuit according to claim 1, comprising a FO memory.