JPH11176948A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH11176948A JPH11176948A JP9337472A JP33747297A JPH11176948A JP H11176948 A JPH11176948 A JP H11176948A JP 9337472 A JP9337472 A JP 9337472A JP 33747297 A JP33747297 A JP 33747297A JP H11176948 A JPH11176948 A JP H11176948A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- diffusion region
- transistor
- power supply
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 230000000295 complement effect Effects 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000002265 prevention Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Amplifiers (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、大電流による素子
破壊を防止する保護回路を有する半導体装置に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a protection circuit for preventing an element from being destroyed by a large current.
【０００２】[0002]
【従来の技術】図６は、従来の電源回路の構成を示した
ブロック図である。この図に示すように、電源回路１は
基準電圧源５、誤差増幅器６およびCMOS（相補型金属・
酸化膜・半導体）型Nch（Nチャンネル）パストランジス
タ８とで構成されている。このパストランジスタ８のソ
ースは、直列に接続された抵抗９および抵抗１０を介し
て端子４において接地されている。また、電源回路１の
入力端子２、すなわち基準電源５は、逆流防止用ダイオ
ード１１を介して、バッテリ１２と接続されている。2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional power supply circuit. As shown in this figure, a power supply circuit 1 includes a reference voltage source 5, an error amplifier 6, and a CMOS (complementary metal
An oxide film / semiconductor type Nch (N-channel) pass transistor 8 is provided. The source of the pass transistor 8 is grounded at the terminal 4 via a resistor 9 and a resistor 10 connected in series. The input terminal 2 of the power supply circuit 1, that is, the reference power supply 5 is connected to the battery 12 via the backflow prevention diode 11.
【０００３】上述した従来例において、天絡状態につい
てを考える。この従来例の電源回路１では、パストラン
ジスタ８における寄生PNPトランジスタがオン状態とな
り、無制限に大電流がパストランジスタ８に流れる。そ
の結果、この大電流により発生する熱エネルギにより、
パストランジスタ８は破壊される。すなわち、電源回路
１は、壊れることになる。In the above-mentioned conventional example, a short-to-power condition will be considered. In the power supply circuit 1 of this conventional example, the parasitic PNP transistor in the pass transistor 8 is turned on, and a large current flows through the pass transistor 8 indefinitely. As a result, due to the heat energy generated by this large current,
The pass transistor 8 is destroyed. That is, the power supply circuit 1 is broken.
【０００４】従来、この天絡に対する防止案として、例
えば特開昭62-296608号に記載の保護回路が知られてい
る。同広報記載の保護回路を図７を参照して説明する。
図７は、保護回路の構成を示すブロック図である。この
図において、２７は増幅回路ブロックであり、バイポー
ラ出力トランジスタ２８のベースとバイポーラ出力トラ
ンジスタ２９のベースとの間に介挿されている。Conventionally, a protection circuit disclosed in Japanese Patent Application Laid-Open No. 62-296608 is known as a measure for preventing this short-to-power. The protection circuit described in the publication will be described with reference to FIG.
FIG. 7 is a block diagram illustrating a configuration of the protection circuit. In this figure, reference numeral 27 denotes an amplifier circuit block, which is interposed between the base of the bipolar output transistor 28 and the base of the bipolar output transistor 29.
【０００５】３０は比較器であり、電圧源３１と増幅回
路ブロック２７との間に介挿されている。２は入力端子
であり、３は出力端子である。たとえば、入力端子２の
電位をVIN、出力端子の電位をV0UT、そして電圧源３０
の電圧をV30とすると、比較器３０は(VIN-V30)の値と電
位V0UTを比較器２７において比較し、V0UT＞(VIN−V30)
となった時、バイポーラ出力トランジスタ２９のドライ
ブ回路を遮断する。従って、バイポーラ出力トランジス
タ２８はオフ状態となり、バイポーラ出力トランジスタ
２８およびバイポーラ出力トランジスタ２９には大電流
は流れない。[0005] A comparator 30 is interposed between the voltage source 31 and the amplifier circuit block 27. 2 is an input terminal and 3 is an output terminal. For example, the potential of the input terminal 2 is VIN, the potential of the output terminal is V0UT, and the voltage source 30
Is the voltage of V30, the comparator 30 compares the value of (VIN−V30) with the potential V0UT in the comparator 27, and V0UT> (VIN−V30)
, The drive circuit of the bipolar output transistor 29 is cut off. Therefore, bipolar output transistor 28 is turned off, and no large current flows through bipolar output transistor 28 and bipolar output transistor 29.
【０００６】[0006]
【発明が解決しようとする課題】上述した電源回路１を
バイポーラトランジスタ作成プロセスに対して、工程数
が少なく、集積度も高く、さらに、比較的に安価に実現
できるCM0S（相補型金属・酸化膜・半導体）トランジス
タ作成プロセスにより実現しようとした場合、上記特開
昭62-296608号に記載の技術を用いることで、確かにGND
端子に流れ込む電流は無くなる。しかしながら、CMOSト
ランジスタ構造上のトランジスタが作成されている基板
に流れこむ大電流はなくせない。この大電流が流れた結
果、トランジスタの破壊が起こる。The power supply circuit 1 described above has a smaller number of steps, a higher degree of integration, and can be realized relatively inexpensively with respect to the bipolar transistor fabrication process of the power supply circuit 1 (CM0S (complementary metal / oxide film)).・ Semiconductor) In the case of trying to realize it by a transistor fabrication process, the technology described in Japanese Patent Application Laid-Open No. 62-296608 is certainly used.
No current flows into the terminal. However, a large current flowing into a substrate on which a transistor on a CMOS transistor structure is formed cannot be eliminated. As a result of this large current, the transistor is destroyed.
【０００７】本発明はこのような背景の下になされたも
ので、天絡状態においても、回路電流が増加することが
無いCM0S型のトランジスタで構成される電源回路を提供
することにある。The present invention has been made under such a background, and an object of the present invention is to provide a power supply circuit including a CM0S type transistor in which a circuit current does not increase even in a short-to-power condition.
【０００８】[0008]
【課題を解決するための手段】本発明の電源回路は、CM
OSのパストランジスタのソースとバックゲートとの間に
抵抗素子を挿入することにより、天絡時の回路電流増加
を防ぐものである。図２示す電源回路に用いる２重拡散
法による高耐圧CM0S構造のパストランジスタにおいて、
天絡時、バックゲート１９をエミッター、ドレイン２０
をベースそして、P-基板１４をコレクタとする寄生ＰＮ
Ｐトランジスタがオン状態となるが、抵抗素子１３の挿
入により、P-基板１４に流れる電流の値は制限される。The power supply circuit of the present invention comprises a CM
By inserting a resistance element between the source and the back gate of the OS pass transistor, an increase in circuit current at the time of short-to-power is prevented. In the pass transistor having a high breakdown voltage CM0S structure by the double diffusion method used in the power supply circuit shown in FIG.
In case of short-to-power, back gate 19 is used as emitter and drain 20
PN based on P - substrate 14 and collector
Although the P transistor is turned on, the value of the current flowing through the P − substrate 14 is limited by the insertion of the resistance element 13.
【０００９】[0009]
【発明の実施の形態】以下、図面を参照して本発明の実
施形態について説明する。図１は本発明の一実施形態に
よる電源回路の構成を示すブロック図である。この図に
おいて、１は電源回路であり、入力端子２とバッテリ１
２の出力端子Toとが逆流防止用ダイオード１１を介して
接続されている。また、電源回路１の入力端子４は、接
地されており、生成された電力は、出力端子３から出力
される。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a power supply circuit according to one embodiment of the present invention. In this figure, reference numeral 1 denotes a power supply circuit, and an input terminal 2 and a battery 1
The second output terminal To is connected via a backflow prevention diode 11. The input terminal 4 of the power supply circuit 1 is grounded, and the generated power is output from the output terminal 3.
【００１０】電源回路１は、基準電圧源５、誤差増幅器
６、CM0S型Nchパストランジスタ８、分割抵抗９および
分割抵抗１０により構成されている。基準電圧源５は、
入力端子Ｔ５ａが入力端子２と接続されており、入力端
子Ｔ５ｂが入力端子４と接続されており、出力端子Ｔ５
ｃが誤差増幅器６の反転入力端子Ｔ６ａと接続されてい
る。また、基準電圧源５は、バッテリ１２から供給され
る電圧値の電圧から所定の電圧値の電圧を発生する。The power supply circuit 1 includes a reference voltage source 5, an error amplifier 6, a CM0S type Nch pass transistor 8, a dividing resistor 9, and a dividing resistor 10. The reference voltage source 5
The input terminal T5a is connected to the input terminal 2, the input terminal T5b is connected to the input terminal 4, and the output terminal T5
c is connected to the inverting input terminal T6a of the error amplifier 6. The reference voltage source 5 generates a voltage having a predetermined voltage value from a voltage value supplied from the battery 12.
【００１１】誤差増幅器６は、出力端子Ｔ６ｃがパスト
ランジスタ８のゲート端子８ｇと接続され、正転入力端
子Ｔ６ｂが直列に接続されている分割抵抗９および分割
抵抗１０の接続点Ａに接続されている。また、誤差増幅
器６は、電源端子Ｔ６ｖが電源回路１の入力端子２と接
続され、接地端子Ｔ６ｇが電源回路１の入力端子４に接
続されている。さらに、誤差増幅器６は、入力端子Ｔ６
ａに入力される電圧の電圧値と接続点Ａの電圧値との差
を増幅した電圧値の電圧を出力端子Ｔ６ｃから出力す
る。The error amplifier 6 has an output terminal T6c connected to the gate terminal 8g of the pass transistor 8, and a non-inverting input terminal T6b connected to a connection point A of the divided resistors 9 and 10 connected in series. I have. The error amplifier 6 has a power supply terminal T6v connected to the input terminal 2 of the power supply circuit 1, and a ground terminal T6g connected to the input terminal 4 of the power supply circuit 1. Further, the error amplifier 6 has an input terminal T6
The output terminal T6c outputs a voltage having a voltage value obtained by amplifying the difference between the voltage value of the voltage input to a and the voltage value of the connection point A.
【００１２】パストランジスタ８は、ドレイン端子８ｄ
が入力端子２に接続され、ソース端子８ｓが分割抵抗９
の接続点Ａに接続されていない方の端子に接続されてい
る。また、パストランジスタ８は、ソース端子８ｓが電
源回路１の出力端子３に接続されており、ゲート端子８
ｇに与えられる電圧値に対応する電圧値の電圧をソース
端子８ｓに発生させる電流を流す。The pass transistor 8 has a drain terminal 8d
Is connected to the input terminal 2, and the source terminal 8 s is
Are connected to the terminal that is not connected to the connection point A. The pass transistor 8 has a source terminal 8 s connected to the output terminal 3 of the power supply circuit 1 and a gate terminal 8 s.
A current is applied to generate a voltage having a voltage value corresponding to the voltage value applied to g at the source terminal 8s.
【００１３】次に、パストランジスタ８について図２を
参照して説明する。図２は、図１のCM0S型Nchパストラ
ンジスタ８の構造を示す横断面図である。このパストラ
ンジスタ８は、２重拡散法による高耐圧CM0S構造で作成
されている。この図において、半導体のP-基板１４上に
N-ウェル１５が形成されており、さらに前記N-ウェル１
５中にP-ウェル１６が形成されている。Next, the pass transistor 8 will be described with reference to FIG. FIG. 2 is a cross-sectional view showing the structure of the CM0S type Nch pass transistor 8 of FIG. This pass transistor 8 is formed in a high breakdown voltage CM0S structure by a double diffusion method. In this figure, a semiconductor P - substrate 14
An N - well 15 is formed, and the N - well 1 is further formed.
5, a P - well 16 is formed.
【００１４】前記P-ウェル１６の表面には、前記パスト
ランジスタ８のソースとなるN+拡散領域１７と、フィー
ルド酸化膜１８を介して前記パストランジスタ８のバッ
クゲートとなるP+拡散領域１９とが形成されている。こ
の時、例えばポリシリで形成される抵抗１３の一方の端
子と前記ソースになるN+拡散領域１７とは接続され、同
様に抵抗１３の他方の端子と前記バックゲートになるP+
拡散領域１９とは接続される。On the surface of the P - well 16, an N + diffusion region 17 serving as a source of the pass transistor 8 and a P + diffusion region 19 serving as a back gate of the pass transistor 8 via a field oxide film 18 are formed. Are formed. At this time, for example, one terminal of the resistor 13 formed of polysilicon is connected to the N + diffusion region 17 serving as the source, and similarly, the other terminal of the resistor 13 is connected to the P + serving as the back gate.
The diffusion region 19 is connected.
【００１５】また、前記N-ウェル１５の表面には、前記
P-ウェル１６からフィールド酸化膜１８を介してドレイ
ンとなるN+拡散領域２０が離れて形成される。さらに、
前記P-ウェル１６上において、絶縁層２１を介してゲー
ト電極２２が形成される。上述したように、CM0S型Nch
パストランジスタ８は構成される。The surface of the N - well 15 is
An N + diffusion region 20 serving as a drain is formed apart from P - well 16 via field oxide film 18. further,
A gate electrode 22 is formed on the P - well 16 via an insulating layer 21. As described above, CM0S type Nch
The pass transistor 8 is configured.
【００１６】そして、ソースとなるN+拡散領域１７は、
出力端子３（図１参照）に接続される。また、バックゲ
ートとなるP+拡散領域１９は、抵抗１３を介して出力端
子３（図１参照）に接続される。さらに、ドレインとな
るN+拡散領域２０が入力端子２（図１参照）接続され、
ゲート電極２２は誤差増幅器６の出力端子Ｔ６ｃに接続
される。The N + diffusion region 17 serving as a source is
Connected to output terminal 3 (see FIG. 1). The P + diffusion region 19 serving as a back gate is connected to the output terminal 3 (see FIG. 1) via the resistor 13. Further, an N + diffusion region 20 serving as a drain is connected to the input terminal 2 (see FIG. 1),
Gate electrode 22 is connected to output terminal T6c of error amplifier 6.
【００１７】次に、一実施形態の動作を図１、図２およ
び図３を参照して説明する。図３は、誤って出力端子３
を逆流防止用ダイオード１１のアノード側、つまりバッ
テリ１２の出力端子Ｔｏに短絡した状態（以降この状態
を天絡とする）のパストランジスタ８の等価回路を示す
ものである。Next, the operation of the embodiment will be described with reference to FIGS. 1, 2 and 3. FIG. 3 shows that the output terminal 3
2 shows an equivalent circuit of the pass transistor 8 in a state in which is short-circuited to the anode side of the backflow prevention diode 11, that is, the output terminal To of the battery 12 (hereinafter, this state is referred to as short-to-supply).
【００１８】この天絡の結果、パストランジスタ８のN+
拡散領域（ソース）１７がN+拡散領域（ドレイン）２０
よりダイオード１１のホワード電圧分高くなり、図２中
のバックゲート１９をエミッタ、ドレイン２０をベー
ス、そしてP-基板１４をコレクターとする寄生PNPトラ
ンジスタ２３がオン状態となる。As a result of this short-to-power, the N +
The diffusion region (source) 17 is an N + diffusion region (drain) 20
The parasitic PNP transistor 23 having the back gate 19 as the emitter, the drain 20 as the base, and the P − substrate 14 as the collector in FIG. 2 is turned on.
【００１９】これにより、電流ＩSUBがP+拡散層からP-
基板１４に向かって流れ込もうとする。しかしながら、
ソース１７とバックゲート１９との間に抵抗１３が挿入
されているため、電流ＩSUBの値には制限がかかる。す
なわち、下式に示す様にP-基板１４に向かって流れ込も
うとする電流ＩSUBに制限がかかる。 ＩSUB ＝ （１＋１／ｈFE）-1×Ｉｓ ……（１） Ｉｓ ＝ ＩS0×exp［（ｑ／ｋＴ）×（ＶＦ−Ｒ１３×Ｉｓ）］……（２）As a result, the current I SUB flows from the P + diffusion layer to P −
An attempt is made to flow toward the substrate 14. However,
Since the resistor 13 is inserted between the source 17 and the back gate 19, the value of the current I SUB is limited. That is, as shown in the following equation, the current I SUB that is going to flow toward the P − substrate 14 is limited. I SUB = (1 + 1 / hFE) -1 × Is (1) Is = Is0 × exp [(q / kT) × (VF-R13 × Is)] (2)
【００２０】ここで、ｈFEは寄生ＰＮＰトランジスタ２
３の電流増幅率、Ｉｓはソース電流、ｑ／ｋＴ＝３８.
６、ＩS0は寄生ＰＮＰトランジスタ２３のエミッタ飽和
電流、ＶＦはダイオード１１のホワード電圧、Ｒ１３は
ソース１７とバックゲート１９との間に介挿された抵抗
１３の抵抗値である。Here, hFE is the parasitic PNP transistor 2
3, a current amplification factor of 3, Is is a source current, and q / kT = 38.
6, IS0 is the emitter saturation current of the parasitic PNP transistor 23, VF is the forward voltage of the diode 11, and R13 is the resistance value of the resistor 13 inserted between the source 17 and the back gate 19.
【００２１】たとえば、ｈＦＥ＝１、ＩS0＝５Ｅ−１８
（Ａ）およびＶＦ＝ｌ.２（Ｖ）とし、Ｒ１３をポリ抵
抗で形成する。そして、上記（ｌ）および（２）式へ、
前記の値を代入すれば、Ｒ１３＝５０（Ω）の時、Ｉ
SUB＝５.９（ｍＡ）となり、Ｒ１３＝５００（Ω）の
時、ＩSUB＝６９５（μＡ）となり、Ｒ１３＝５Ｋ
（Ω）の時、ＩSUB＝８２（μＡ）となる。For example, hFE = 1, IS0 = 5E-18
(A) and VF = 1.2 (V), and R13 is formed by a poly resistor. Then, to the above equations (l) and (2),
By substituting the above values, when R13 = 50 (Ω), I
SUB = 5.9 (mA), and when R13 = 500 (Ω), I SUB = 695 (μA), and R13 = 5K
(Ω), ISUB = 82 (μA).
【００２２】以上、本発明の一実施形態を図面を参照し
て詳述してきたが、具体的な構成はこの実施形態に限ら
れるものではなく、本発明の要旨を逸脱しない範囲の設
計変更等があっても本発明に含まれる。例えば、本発明
の第二の実施形態よる電源回路を図４に示す。この実施
形態は、本発明の第一の実施形態のCM0S型Nchパストラ
ンジスタ８をCM0S型Pch（Pチャンネル）パストランジス
タ８０へ変更したものである。As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention. For example, FIG. 4 shows a power supply circuit according to the second embodiment of the present invention. In this embodiment, the CM0S-type Nch pass transistor 8 of the first embodiment of the present invention is changed to a CM0S-type Pch (P-channel) pass transistor 80.
【００２３】このCM0S型Pchパストランジスタ８０は、
ソース端子８０ｓが入力端子２に接続され、抵抗１３を
介したバックゲートが接続されている。また、CM0S型Pc
hパストランジスタ８０のドレイン端子８０ｄは、出力
端子３へ接続されている。この結果、レギュレーション
開始電圧は下がる。その他の構成及び接続は、第１図と
同一であるため、同一箇所には同一符号を付してその説
明を省略する。This CM0S type Pch pass transistor 80
The source terminal 80s is connected to the input terminal 2 and the back gate via the resistor 13 is connected. Also, CM0S type Pc
The drain terminal 80 d of the h-pass transistor 80 is connected to the output terminal 3. As a result, the regulation start voltage decreases. Since other configurations and connections are the same as those in FIG. 1, the same portions are denoted by the same reference numerals and description thereof will be omitted.
【００２４】図５は、図４のCM0S型Pchパストランジス
タ８０の断面図である。ここで、CM0S型Pchパストラン
ジスタ80は、２重拡散法による高耐圧CM0S構造で作成さ
れている。図４に示すように、P-基板１４上にN-ウェル
１５が形成されている。また、前記N-ウェル１５中に
は、P-ウェル１６が形成されている。前記N-ウェル１５
の表面には、CM0S型Pchパストランジスタ８０のソース
端子８０ｓ（図４参照）となるP+拡散領域２４と、フィ
ールド酸化膜１８を介してCM0S型Pchパストランジスタ
８０のバックゲートとなるN+拡散領域２５とが形成され
る。FIG. 5 is a sectional view of the CM0S type Pch pass transistor 80 of FIG. Here, the CM0S type Pch pass transistor 80 is formed with a high breakdown voltage CM0S structure by a double diffusion method. As shown in FIG. 4, an N − well 15 is formed on a P − substrate 14. Further, a P - well 16 is formed in the N - well 15. The N - well 15
P + diffusion region 24 serving as source terminal 80s (see FIG. 4) of CM0S type Pch pass transistor 80, and N + diffusion serving as a back gate of CM0S type Pch pass transistor 80 via field oxide film 18. A region 25 is formed.
【００２５】例えば、ポリシリコン（多結晶シリコン）
で形成される抵抗１３の一方の端子は、前記ソース端子
８０ｓとなるＮ+拡散領域２４と接続され、抵抗１３の
他方の端子は、前記バックゲートとなるＮ+拡散領域２
５に接続される。P-ウェル１６の表面には、フィールド
酸化膜１８を介し、ドレイン端子８０ｄとなるP+拡散領
域２６が前記N-ウェル１５と前記P-ウェル１６の接合と
から離して形成される。For example, polysilicon (polycrystalline silicon)
Is connected to the N + diffusion region 24 serving as the source terminal 80s, and the other terminal of the resistor 13 is connected to the N + diffusion region 2 serving as the back gate.
5 is connected. On the surface of the P − well 16, a P + diffusion region 26 serving as a drain terminal 80 d is formed via the field oxide film 18 at a distance from the junction between the N − well 15 and the P − well 16.
【００２６】さらに、ゲート電極２２は、P-ウェル１６
上に絶縁層２１を介して形成される。上述したように、
CM0S型Pchパストランジスタ８０が構成される。そし
て、ドレイン端子８０ｄ（図１参照）となるP+拡散領域
２６は、出力端子３に接続され、バックゲートとなるN+
拡散領域２５は抵抗１３を介して入力端子２に接続され
る。また、ソース端子８０ｓとなるP+拡散領域２４は入
力端子２に接続され、ゲート電極２２は誤差増幅器６の
出力端子Ｔ６ｃと節点７を介して接続される。Further, the gate electrode 22 is connected to the P - well 16.
It is formed thereon with an insulating layer 21 interposed. As mentioned above,
A CM0S type Pch pass transistor 80 is configured. Then, the P + diffusion region 26 serving as the drain terminal 80d (see FIG. 1) is connected to the output terminal 3 and the N + serving as the back gate is provided.
Diffusion region 25 is connected to input terminal 2 via resistor 13. The P + diffusion region 24 serving as the source terminal 80s is connected to the input terminal 2, and the gate electrode 22 is connected to the output terminal T6c of the error amplifier 6 via the node 7.
【００２７】上述した第二の実施形態においても、第一
の実施形態と同様に天絡状態となると、図５におけるP+
拡散領域２６（ドレイン端子８０ｄ）をエミッター、N+
拡散領域２５（バックゲート）をベース、そして、P-基
板１４をコレクタとする寄生ＰＮＰバイポーラトランジ
スタ２３がオン状態となるが、P-基板１４に向かって流
れる電流ＩSUBは、第一の実施形態と同様に抵抗１３に
より制限される。この結果、電流ＩSUBが流れることに
より発生する熱エネルギによるCM0S型Pchパストランジ
スタ８０の絶縁破壊は防止される。In the above-described second embodiment, as in the first embodiment, when a short-to-power condition occurs, P + in FIG.
The diffusion region 26 (drain terminal 80d) is used as an emitter and N +
The parasitic PNP bipolar transistor 23 having the diffusion region 25 (back gate) as a base and the P - substrate 14 as a collector is turned on, but the current I SUB flowing toward the P - substrate 14 is the first embodiment. Is limited by the resistor 13 in the same manner as described above. As a result, dielectric breakdown of the CM0S type Pch pass transistor 80 due to thermal energy generated by the flow of the current I SUB is prevented.
【００２８】[0028]
【発明の効果】本発明によれば、回路電流がバックゲー
トとソースとの間に介挿された抵抗により制限され、所
定の値以上に増加することが無いCM0S型のトランジスタ
を用いるため、天絡状態においても、絶縁破壊が防止さ
れる電源回路を提供することができる。According to the present invention, a CM0S transistor whose circuit current is limited by a resistor inserted between the back gate and the source and does not increase beyond a predetermined value is used. It is possible to provide a power supply circuit in which dielectric breakdown is prevented even in a short-circuit state.
【図１】 本発明の一実施形態による電源回路の構成を
示すブロック図である。FIG. 1 is a block diagram showing a configuration of a power supply circuit according to an embodiment of the present invention.
【図２】 本発明の一実施形態によるCMOS型Nchトラン
ジスタの構造を示す横断面図である。FIG. 2 is a cross-sectional view showing the structure of a CMOS Nch transistor according to one embodiment of the present invention.
【図３】 本発明の一実施形態における天絡状態のパス
トランジスタ８の等価回路を示すものである。FIG. 3 shows an equivalent circuit of the pass transistor 8 in a short-to-power state according to the embodiment of the present invention.
【図４】 本発明の第二の実施形態による電源回路の構
成を示すブロック図である。FIG. 4 is a block diagram illustrating a configuration of a power supply circuit according to a second embodiment of the present invention.
【図５】 本発明の第二の実施形態によるCMOS型Pchト
ランジスタの構造を示す横断面図である。FIG. 5 is a cross-sectional view illustrating a structure of a CMOS Pch transistor according to a second embodiment of the present invention.
【図６】 従来例による電源回路の構成を示すブロック
図である。FIG. 6 is a block diagram showing a configuration of a power supply circuit according to a conventional example.
【図７】 従来例による電源回路における天絡時の大電
流防止回路の構成を示すブロック図である。FIG. 7 is a block diagram showing a configuration of a large current prevention circuit at the time of short-to-power in a power supply circuit according to a conventional example.
１ 電源回路 ２、４ 入力端子 ３ 出力端子 ５ 基準電圧源 ６ 誤差増幅器 ８ CMOS型Nchパストランジスタ ９ 、１０ 分割抵抗 １１ 逆流防止用ダイオード １２ バッテリ １４ P-基板 １５ N-ウェル １６ P-ウェル １７ N+拡散領域 １８ フィールド酸化膜 １９ P+拡散領域 ２０ N+拡散領域 ２１ 絶縁層 ２２ ゲート電極 ２３ 寄生PNPバイポーラトランジスタ ８０ CMOS型PchパストランジスタREFERENCE SIGNS LIST 1 power supply circuit 2, 4 input terminal 3 output terminal 5 reference voltage source 6 error amplifier 8 CMOS type Nch pass transistor 9, 10 dividing resistor 11 backflow prevention diode 12 battery 14 P - substrate 15 N - well 16 P - well 17 N + Diffusion region 18 field oxide film 19 P + diffusion region 20 N + diffusion region 21 insulating layer 22 gate electrode 23 parasitic PNP bipolar transistor 80 CMOS Pch pass transistor
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ // Ｇ０５Ｆ 1/56 ３１０ ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification symbol FI // G05F 1/56 310
Claims (5)
形成された第二の拡散層と、 前記第一の拡散層と前記第二の拡散層との間に介挿され
た抵抗とを具備することを特徴とする半導体集積回路。1. A MOS transistor, comprising: a semiconductor substrate; a first diffusion layer formed on the semiconductor substrate surface; and a second diffusion layer formed on the semiconductor substrate surface so as to be spaced apart from the first diffusion layer in a surface direction. And a resistor interposed between the first diffusion layer and the second diffusion layer.
て、前記第一の拡散層と前記第二の拡散層との間に形成
された絶縁膜上面に形成されることを特徴とする請求項
１記載の半導体集積回路。2. The semiconductor device according to claim 1, wherein the resistance is formed on an upper surface of an insulating film formed between the first diffusion layer and the second diffusion layer on the semiconductor substrate surface. A semiconductor integrated circuit as described in the above.
ことを特徴とする請求項１または請求項２記載の半導体
集積回路。3. The semiconductor integrated circuit according to claim 1, wherein said resistor is formed of polycrystalline silicon.
型であることを特徴とする請求項１ないし請求項３のい
ずれかに記載の半導体集積回路。4. The semiconductor integrated circuit according to claim 1, wherein said MOS transistor is an N-channel type.
型であることを特徴とする請求項１ないし請求項３のい
ずれかに記載の半導体集積回路。5. The semiconductor integrated circuit according to claim 1, wherein said MOS transistor is of a P-channel type.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9337472A JP3068540B2 (en) | 1997-12-08 | 1997-12-08 | Semiconductor integrated circuit and power supply circuit |
| CN98123170A CN1219801A (en) | 1997-12-08 | 1998-12-07 | Power source circuit of semiconductor integrated circuit |
| KR1019980053427A KR19990062860A (en) | 1997-12-08 | 1998-12-07 | Power Supply Circuit of Semiconductor Integrated Circuits |
| EP98123288A EP0921619A3 (en) | 1997-12-08 | 1998-12-07 | A power source circuit of a semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9337472A JP3068540B2 (en) | 1997-12-08 | 1997-12-08 | Semiconductor integrated circuit and power supply circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11176948A true JPH11176948A (en) | 1999-07-02 |
| JP3068540B2 JP3068540B2 (en) | 2000-07-24 |
Family
ID=18308972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9337472A Expired - Lifetime JP3068540B2 (en) | 1997-12-08 | 1997-12-08 | Semiconductor integrated circuit and power supply circuit |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0921619A3 (en) |
| JP (1) | JP3068540B2 (en) |
| KR (1) | KR19990062860A (en) |
| CN (1) | CN1219801A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005165716A (en) * | 2003-12-03 | 2005-06-23 | Toshiba Corp | Regulator unit and backward flow prevention diode circuit using the same |
| JP2006178702A (en) * | 2004-12-22 | 2006-07-06 | Ricoh Co Ltd | Voltage regulator circuit |
| JP2009134387A (en) * | 2007-11-29 | 2009-06-18 | Rohm Co Ltd | High-side switch |
| JP2015031639A (en) * | 2013-08-06 | 2015-02-16 | 日立オートモティブシステムズ株式会社 | Sensor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2647961B1 (en) | 2011-02-28 | 2019-09-18 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit and semiconductor physical quantity sensor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0376264A (en) * | 1989-08-18 | 1991-04-02 | Toshiba Corp | Input protective circuit device |
| JPH0348330U (en) * | 1989-09-12 | 1991-05-09 | ||
| JPH06151744A (en) * | 1992-10-31 | 1994-05-31 | Nec Corp | Semiconductor input-output protection device |
| JPH0722579A (en) * | 1993-06-17 | 1995-01-24 | Sanyo Electric Co Ltd | Input protective circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5625278A (en) * | 1993-06-02 | 1997-04-29 | Texas Instruments Incorporated | Ultra-low drop-out monolithic voltage regulator |
| JP3334290B2 (en) * | 1993-11-12 | 2002-10-15 | 株式会社デンソー | Semiconductor device |
-
1997
- 1997-12-08 JP JP9337472A patent/JP3068540B2/en not_active Expired - Lifetime
-
1998
- 1998-12-07 KR KR1019980053427A patent/KR19990062860A/en not_active Application Discontinuation
- 1998-12-07 EP EP98123288A patent/EP0921619A3/en not_active Withdrawn
- 1998-12-07 CN CN98123170A patent/CN1219801A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0376264A (en) * | 1989-08-18 | 1991-04-02 | Toshiba Corp | Input protective circuit device |
| JPH0348330U (en) * | 1989-09-12 | 1991-05-09 | ||
| JPH06151744A (en) * | 1992-10-31 | 1994-05-31 | Nec Corp | Semiconductor input-output protection device |
| JPH0722579A (en) * | 1993-06-17 | 1995-01-24 | Sanyo Electric Co Ltd | Input protective circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005165716A (en) * | 2003-12-03 | 2005-06-23 | Toshiba Corp | Regulator unit and backward flow prevention diode circuit using the same |
| JP2006178702A (en) * | 2004-12-22 | 2006-07-06 | Ricoh Co Ltd | Voltage regulator circuit |
| JP4587804B2 (en) * | 2004-12-22 | 2010-11-24 | 株式会社リコー | Voltage regulator circuit |
| JP2009134387A (en) * | 2007-11-29 | 2009-06-18 | Rohm Co Ltd | High-side switch |
| JP2015031639A (en) * | 2013-08-06 | 2015-02-16 | 日立オートモティブシステムズ株式会社 | Sensor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990062860A (en) | 1999-07-26 |
| EP0921619A2 (en) | 1999-06-09 |
| CN1219801A (en) | 1999-06-16 |
| EP0921619A3 (en) | 1999-12-22 |
| JP3068540B2 (en) | 2000-07-24 |
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