JPH11176923A - Trench forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming a trench isolation part. SOLUTION: A first insulating layer 21 is formed on a semiconductor substrate 20 through a chemical deposition means, and a photoresist layer is formed thereon. The photoresist layer is exposed, developed, and patterned by etching into a trench demarcating mask. Then, a first insulating part 21, a pad oxide layer, and a part of the semiconductor substrate 20 are etched continuously to provide trenches 22a and 22b to the semiconductor substrate 20. The trenches 22a and 22b are set different from each other in width so as to satisfy different needs of semiconductor devices. The trench 22b is wider in width than the trench 22a. The trench demarcating mask is removed. This trench isolation eliminates plate-like recess effect on the substrate, and a semiconductor device is improved in reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of forming an isolation part by a trench, and more particularly, to a method of forming an isolation part by a trench by two polishing steps.

[0002]

2. Description of the Related Art In a semiconductor manufacturing process, various methods are known for insulating a semiconductor device in an active region on a substrate. One of these methods is shallow trench isolation (isolation) (STI). Shallow trench isolation (insulation)
A conventional method of forming a portion is to form a photoresist layer on a substrate and use the photoresist layer as a mask to etch the substrate and form a trench in the substrate. The shallow trench isolation electrically insulates semiconductor devices on the substrate. Generally speaking, the gate of a semiconductor device electrically connects an interconnect line that extends widely over an integrated circuit (IC) and the shallow trench isolation.

FIGS. 1 to 5 show a process flow for forming an isolation portion by a conventional trench. As shown in FIG. 1, a pad oxide layer (not shown) is formed on semiconductor substrate 10 by a thermal oxidation action. Next, a silicon nitride layer 11 is formed on the pad oxide layer by a chemical vapor deposition (CVD) method. On this silicon nitride layer 11, a photoresist layer (not shown) is formed. The photoresist layer is exposed, developed, and etched to form a trench definition mask for defining a pattern of the plurality of trenches. Using the trench definition mask as a mask, the silicon nitride layer 1 is sequentially formed.
1. Etching the pad oxide layer and etching through the semiconductor substrate 10 to form a trench 12. Then, the trench definition mask is removed.

Referring now to FIG. 2, a silicon oxide layer 13 is deposited on the semiconductor substrate 10 by a chemical vapor deposition (CVD) method, and the trench 12 is filled with the silicon oxide layer, as shown in FIG. A preferred chemical vapor deposition method is atmospheric pressure chemical vapor deposition (AP) wherein the source gas is tetra-ethyl-ortho-siloxane (TEOS).
CVD). The trench 12 is always filled with a silicon oxide layer in anticipation of the contraction of the silicon oxide layer 13. This contraction phenomenon occurs during densification of the silicon oxide layer 13. Densification of the silicon oxide layer 13 is usually a step subsequent to the deposition step of the silicon oxide layer 13, and is performed at a temperature of about 1000 ° C. for a time of about 10 to 30 minutes. On the silicon oxide layer 13, a photoresist layer 14 is formed. Then, the photoresist layer 1
The pattern is exposed to 4, developed and etched to make a reverse diffusion mask.

Next, referring to FIG. 3, anisotropic etching is performed on the silicon oxide layer 13 using a reverse diffusion mask as a mask. The silicon oxide layer 13 is etched until the silicon nitride layer 11 is exposed.

Referring to FIG. 4, next, the photoresist layer 14 is removed, and the silicon oxide layer 13 remains in the trench 12. Next, referring to FIG. 5, the silicon oxide layer 13 is polished (polished) or etched back using the silicon nitride layer 11 as a stop layer. A preferred polishing (polishing) is chemical mechanical polishing (CMP). Therefore, the height of the silicon oxide layer 13 and the height of the silicon nitride layer 11 become the same,
Thus, the trench isolation part 15 is formed.

[0007]

SUMMARY OF THE INVENTION The above-mentioned integrated circuit (I
In the C) process, conventional methods of creating shallow trench isolation (isolation) (isolation) have a number of disadvantages. For example, when patterning the photoresist layer 14, the photoresist layer 14
Must be precisely aligned with the position of the trench 12. If this is not precisely controlled, the silicon oxide layer 13 will be over-etched due to misalignment of the photoresist layer 14. When polishing the silicon oxide layer 13, the silicon oxide layer 13
A shallow dish-shaped dent (dish) is generated on the surface of the substrate 10, and the degree of insulation of the substrate 10 is reduced by such a dent effect (dishing effect). Furthermore, a dummy pattern structure is formed on the semiconductor substrate 10 to reduce the dishing effect (dent effect). Cause problems. These problems are the solution of the present invention.

[0008]

SUMMARY OF THE INVENTION The present invention eliminates a dishing effect (dent effect) in a substrate and enhances the reliability of a semiconductor device by trench isolation (insulation).
To solve the above-mentioned problem.

Another object of the present invention is to provide a simple method of forming a trench isolation (insulation, isolation) which reduces the parasitic capacitance and improves the performance of a semiconductor device.

A method for forming a trench isolation portion includes the following steps. First, a semiconductor substrate is prepared. A first insulating layer and a trench are formed in a semiconductor substrate. Next, a second insulating layer is formed on the first insulating layer, the trench is filled with the second insulating layer, and a dish (dish) is formed on a surface of the second insulating layer covering the trench. Is formed. A third insulating layer is formed on the second insulating layer and the dish (dish-shaped recess). Next,
Performing a first polishing step on the third insulating layer,
The insulating mask is made by exposing the second insulating layer and leaving the portion of the third insulating layer in the dish as it is. Using the insulating mask as a mask, anisotropically etch the second insulating layer until the first insulating layer is exposed, leaving a portion of the second insulating layer below the mask. . The insulating mask and the remaining second insulating layer below the mask become a residue. Then, a second polishing step is performed to remove the residue covering the first insulating layer.

The present invention provides different etch selectivities for silicon nitride and silicon oxide.
And two polishing steps are used to form a reliable and planar trench isolation. The process of the present invention first covers the dishes with a protective mask and then performs the polishing step twice to eliminate dishing effects.
The two polishing steps remove portions of the silicon oxide layer that are not covered by the protective mask, and then remove the remainder of the silicon oxide layer that is covered by the protective mask. The formation of the trench isolation of the present invention removes all of the dishes on the substrate, thus further increasing the reliability of the semiconductor device.

[0012]

Next, a preferred embodiment of the present invention will be described. 6 to 10 are sectional views showing a process flow for forming a trench isolation portion according to the present invention. Referring to FIG. 6, a thin pad oxide layer (not shown)
Is formed on the semiconductor substrate 20 by a chemical vapor deposition (CVD) method to protect the semiconductor substrate 20. On the semiconductor substrate 20, a first insulating layer 21 is formed by chemical vapor deposition. The preferred first insulating layer 21 is a silicon nitride layer, which has strong resistance and compatibility with chemical mechanical polishing. A photoresist layer is formed on the first insulating layer 21. The photoresist is patterned by exposing, developing, and etching layers to create a trench definition mask. Next, the first insulating portion 21, the pad oxide layer, and the semiconductor substrate 2
The portion 0 is continuously etched to form a trench 22a and a trench 22b in the semiconductor substrate 20. As shown, the trench 22a and the trench 22b have different width dimensions to meet different needs of a semiconductor device. The trench 22b is a trench 22
Wider than a. Then, the trench definition mask is removed.

Referring to FIG. 7, the first insulating layer 21
And a second insulating layer 23 covering the trench 22a and the trench 22b is formed.
a and the trench 22b. A preferred second insulating layer 23 is a silicon oxide layer, which is, for example,
The source gas is tetra-ethyl-ortho-siloxane (T
It is formed by an atmospheric pressure chemical vapor deposition (APCVD) means which is EOS) or a sub-atmospheric pressure chemical vapor deposition (SAPCVD) means. Due to the uneven surface structure of the semiconductor substrate 20, a dish (dish-shaped recess) 25 is naturally formed on the upper surface of the trench 22b of the semiconductor substrate 20. Next, a third insulating layer 24 is formed on the second insulating layer 23 by CVD means. A preferred third insulating layer is a silicon nitride layer. A dish is also formed on the surface of the third insulating layer 24 so as to overlap the dish 25.
Of the surface of the insulating layer 23 of FIG.

As can be seen with reference to FIG.
The first insulating layer 24 (first polishing)
Then, the second insulating layer 23 is removed. A preferred polishing is chemical mechanical polishing (chemical mechanical polishing). By this process, only the portion of the third insulating layer 24 filled in the dish 25 remains, and the insulating mask 24a is formed.

Referring to FIG. 9, the second insulating layer 23
Is anisotropically etched using the insulating mask 24a as a mask to expose the first insulating layer 21. The etching selectivity of the second insulating layer 23 is different from the etching selectivity of the first insulating layer 21 and the third insulating layer 24. Therefore, the first insulating layer 21 can be used as an etching stop layer, thereby forming an insulating plug 23a and a protruding plug 23b, and the plug 23b is connected to the second insulating layer 24a below the remaining insulating mask 24a. Of the insulating layer 23 of FIG.
The height of the insulating plug 23a is the same as the height of the first insulating layer 21. The protruding plug 23b is
It includes an insulating mask 24a and a portion of the second insulating layer 23 below the insulating mask 24a.

Referring to FIG. 10, the first insulating layer 2
1 in the stop layer, the projecting plug 23b
Is polished (second polishing).
This polishing is preferably performed by chemical mechanical polishing (chemical mechanical polishing). The height of the plug 23b whose head has been polished and no longer protrudes is the same as the height of the first insulating layer 21. Since the structure of the projecting plug 23b in the semiconductor substrate 20 is small, the projecting portion can be easily polished and flattened by chemical mechanical polishing. Thus, the trench isolation (trench insulation, trench isolation) of the present invention is completed.

FIGS. 11 to 15 are sectional views showing another process flow for forming a trench isolation portion according to the present invention. Referring to FIG. 11, a thin pad oxide layer (not shown) is formed on a semiconductor substrate 30 by a chemical vapor deposition (CVD) method.
To protect the semiconductor substrate 30. Then
On the semiconductor substrate 30, the first
Is formed. Preferred first insulating layer 31
Is a silicon nitride layer, which has strong resistance and compatibility with chemical mechanical polishing (chemical mechanical polishing). A photoresist layer is formed on the first insulating layer 31. This photoresist layer is exposed, developed, etched and patterned,
Make a trench definition mask. Next, the first insulating layer 3
1, the pad oxide layer and the portion of the semiconductor substrate 30 are continuously etched to form a trench 32a and a trench 32
b is formed on the semiconductor substrate 30. As shown, the trench 32a and the trench 32b have different width dimensions to meet different needs of a semiconductor device. The trench 32b is wider than the trench 32a. Then, the trench definition mask is removed.

Referring to FIG. 12, the first insulating layer 3
1 and a second insulating layer 33 covering the trenches 32a and 32b is formed, and a part of the second insulating layer 33 is filled in the trenches 22a and 22b. A preferred second insulating layer 33 is a silicon oxide layer,
For example, it is formed by high density plasma chemical vapor deposition (HDP-CVD) means. This high-density plasma chemical vapor deposition means is one of new deposition methods and is employed in the present invention. Edges inclined at an angle of about 45 ° are formed in the trenches 32a and 32b by high-density plasma chemical vapor deposition as shown. Then, the third insulating layer 3
4 is formed on the second insulating layer 33 by the CVD means. Since the surface of the second insulating layer 33 is not flat, the surface of the formed third insulating layer 34 is not flat, and the trenches 32a and 32b of the semiconductor substrate 30 are formed.
A dish (dish-shaped dent) 35 is naturally formed on the upper surface of the plate. The preferred third insulating layer 34 is a silicon nitride layer.

Referring to FIG. 13, the third insulating layer 34 is polished (first polishing).
Then, the second insulating layer 33 is removed. A preferred polishing is chemical mechanical polishing (chemical mechanical polishing). In this process, the trenches 32a, 32b
Third insulating layer 3 filled in the dish 35 on the top
Only the portion 4 remains, and the insulating mask 24a is formed.

Referring to FIG. 14, the second insulating layer 3
3 uses the insulating mask 34a as a mask,
The first insulating layer 31 is exposed by anisotropic etching. The etching selectivity of the second insulating layer 33 is different from the etching selectivity of the first insulating layer 31 and the third insulating layer 34. Therefore, the first insulating layer 31 can be used as an etching stop layer, whereby a protruding plug 33a and a protruding plug 33b are formed, and the plug 33b is formed on the second insulating layer 34a below the remaining insulating mask 34a. Of the insulating layer 33 of FIG. The height of the protruding plugs 33a and 33b is higher than the height of the first insulating layer 31. Both the protruding plugs 33a and 33b include an insulating mask 34a and a portion of the second insulating layer 33 below the insulating mask 34a.

Referring to FIG. 15, the first insulating layer 3
1 as a stop layer, the projecting plug 33
a, 33b are polished (polished) (second polishing). This polishing is preferably a chemical mechanical polishing. Plug 33a whose head is polished and no longer protrudes,
The height of 33b is the same as the height of the first insulating layer 31. Projecting plugs 33a, 33 on semiconductor substrate 30
Since the structure of b is small, the protruding portion can be easily polished and flattened by chemical mechanical polishing. Thus, the trench isolation of the present invention is completed.

The embodiments described above are not intended to limit the present invention, and the present invention includes all modifications, variations, and arrangements, and the technical scope described in the claims is the broadest. It is to be construed broadly and encompasses all modifications, variations, arrangements and similar means.

[0023]

The trench isolation of the present invention has the following effects: According to the present invention, a dishing effect in a semiconductor substrate is eliminated by trench isolation (trench isolation), and the reliability of a semiconductor device is improved. 2. The trench isolation of the present invention reduces parasitic capacitance and improves semiconductor device performance.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional process flow for creating a shallow trench isolation.

FIG. 2 is a cross-sectional view illustrating a conventional process flow for creating a shallow trench isolation.

FIG. 3 is a cross-sectional view illustrating a conventional process flow for creating a shallow trench isolation.

FIG. 4 is a cross-sectional view illustrating a conventional process flow for creating a shallow trench isolation.

FIG. 5 is a cross-sectional view showing a conventional process flow for forming a shallow trench isolation.

FIG. 6 is a sectional view showing a process flow for forming a trench isolation portion according to the present invention.

FIG. 7 is a sectional view showing a process flow for forming a trench isolation portion according to the present invention.

FIG. 8 is a sectional view showing a process flow for forming a trench isolation portion according to the present invention.

FIG. 9 is a sectional view showing a process flow for forming a trench isolation portion according to the present invention.

FIG. 10 is a sectional view showing a process flow for forming a trench isolation portion according to the present invention.

FIG. 11 is a cross-sectional view showing another process flow for producing the trench isolation portion of the present invention.

FIG. 12 is a sectional view showing another process flow for producing the trench isolation portion of the present invention.

FIG. 13 is a cross-sectional view showing another process flow for producing the trench isolation portion of the present invention.

FIG. 14 is a cross-sectional view showing another process flow for forming the trench isolation portion of the present invention.

FIG. 15 is a cross-sectional view showing another process flow for making the trench isolation portion of the present invention.

[Explanation of symbols]

 20, 30 Semiconductor substrate 21, 31 First insulating layer 22a, 22b, 32a, 32b Trench 23, 33 Second insulating layer 23a, 23b, 33a, 33b Insulating plug 24, 34 Third insulating layer 24a, 34a Insulating Mask 25, 35 dish

Claims (21)

[Claims] 1. A method for forming a trench isolation part comprising the steps of: preparing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; and forming a first insulating layer on the semiconductor substrate.
Forming a trench and a second trench having a width larger than the width of the first trench; forming a second insulating layer on the first insulating layer; A second trench is filled with the second insulating layer, and a dish (a dish-shaped recess) is formed on a surface of the second insulating layer that covers the second trench.
Forming a third insulating layer on the second insulating layer; performing a first polishing step on the third insulating layer to expose the second insulating layer Let
Forming an insulating mask by leaving the portion of the third insulating layer in the dish as it is; using the insulating mask as a mask, until the first insulating layer is exposed, And a second polishing step of polishing the residue to the level of the first insulating layer. 2. The method according to claim 1, wherein the first polishing step is a chemical mechanical polishing. 3. The method according to claim 1, wherein the second polishing step is a chemical mechanical polishing. 4. The method of claim 1, wherein the etching selectivity of the first insulating layer is different from the etching selectivity of the second insulating layer. 5. The method according to claim 4, wherein said first insulating layer is a silicon nitride layer. 6. The method of claim 4, wherein said second insulating layer is a silicon oxide layer. 7. The method of claim 1, wherein the etching selectivity of the second insulating layer is different from the etching selectivity of the third insulating layer. 8. The method of claim 7, wherein said second insulating layer is a silicon oxide layer. 9. The method of claim 7, wherein said third insulating layer is a silicon nitride layer. 10. A method of forming a trench isolation portion comprising the steps of: preparing a semiconductor substrate; forming a first insulating layer in the semiconductor substrate; forming a trench in the semiconductor substrate; On the first insulating layer, the second
Forming an insulating layer, filling the trench with the second insulating layer, and forming a dish (dish-shaped recess) on a surface of the second insulating layer covering the trench; third step; Forming an insulating layer on the second insulating layer and the dish; performing a first polishing step on the third insulating layer to expose the second insulating layer; Forming an insulating mask by leaving the portion of the third insulating layer as it is; using the insulating mask as a mask, anisotropically forming the second insulating layer until the first insulating layer is exposed; Etching to leave part of the insulating mask and to leave the second insulating layer under the insulating mask; and a second polishing step of polishing the residue to the level of the first insulating layer . 11. The method as claimed in claim 10, wherein the first polishing step is a chemical mechanical polishing. 12. The method according to claim 10, wherein the second polishing step is a chemical mechanical polishing. 13. The etching selectivity of the first insulating layer is the second.
11. The method according to claim 10, wherein the etching selectivity of the insulating layer is different. 14. The method of claim 13, wherein said first insulating layer is a silicon nitride layer. 15. The method of claim 13, wherein said second insulating layer is a silicon oxide layer. 16. The etching selectivity of the second insulating layer is the third.
11. The method according to claim 10, wherein the etching selectivity of the insulating layer is different. 17. The method according to claim 16, wherein said second insulating layer is a silicon oxide layer. 18. The method of claim 16, wherein said third insulating layer is a silicon nitride layer. 19. The method according to claim 19, wherein said third insulating layer is formed by atmospheric pressure chemical vapor deposition (A).
A method as claimed in claim 10 formed by (PCVD) means. 20. The method of claim 10, wherein said third insulating layer is formed by sub-atmospheric pressure chemical vapor deposition (SACVD) means. 21. The method according to claim 1, wherein the third insulating layer is formed by high density plasma chemical vapor deposition (HDP-CVD).
The method charged to zero.