JPH1117093A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1117093A
JPH1117093A JP16757997A JP16757997A JPH1117093A JP H1117093 A JPH1117093 A JP H1117093A JP 16757997 A JP16757997 A JP 16757997A JP 16757997 A JP16757997 A JP 16757997A JP H1117093 A JPH1117093 A JP H1117093A
Authority
JP
Japan
Prior art keywords
semiconductor device
external connection
mounting
led out
flat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16757997A
Other languages
Japanese (ja)
Inventor
Junichi Asada
順一 浅田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16757997A priority Critical patent/JPH1117093A/en
Publication of JPH1117093A publication Critical patent/JPH1117093A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a vertically mounting type semiconductor device suitable for forming a high density mounting circuit device. SOLUTION: A semiconductor device 4 is provided with a flat plate type package 5, which has a flat sidewall at least on one side, and a group of terminals 6a for external connection, which are led out vertically from the flat side wall 5a on one side of the package 5. Lead terminals 6b and 6c for external connection are led out from at least one side 5b or 5c other than the flat side wall 5a from which the group of terminals 6a are led out.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に係り、
さらに詳しくは実装用配線板面に対し、縦方向に搭載・
実装する垂直実装型の半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
For more details, mount vertically in the mounting wiring board surface.
The present invention relates to a vertical mounting type semiconductor device to be mounted.

【0002】[0002]

【従来の技術】実装回路装置のコンパクト化ないしは高
機能化などに対応して、実装用配線板面に、たとえば樹
脂封止型の半導体パッケージなどの半導体装置を垂直方
向(縦型)に搭載・実装して成る実装回路装置が開発さ
れている。図9は垂直実装型の樹脂封止半導体パッケー
ジの構成を示す斜視図であり、各辺が平坦な側壁面であ
る平板状のモールドパッケージ部1と、前記モールドパ
ッケージ部1の一辺1aのみに、垂直に導出された外部接
続用端子群2とを有する構造と成っている。ここで、外
部接続用端子2群は、たとえば半導体素子をマウントし
たリードフレームで形成され、かつ平坦な一辺のみにほ
ぼ垂直に導出されており、その自由端側を水平2aに折り
曲げたJ字型を成している。そして、この半導体装置
は、図10に断面的に示すごとく、実装用配線板3の被接
続端子3a面に対し、外部接続用端子群2の折り曲げ水平
部2aを対接させ、半田付け(図示省略)などにより、電
気的および機械的に接続(実装)される。
2. Description of the Related Art A semiconductor device such as a resin-encapsulated semiconductor package is mounted on a surface of a mounting wiring board in a vertical direction (vertical type) in accordance with a reduction in the size of a mounting circuit device or an increase in functionality. A mounting circuit device formed by mounting is developed. FIG. 9 is a perspective view showing a configuration of a resin package semiconductor package of a vertical mounting type. The mold package section 1 has a flat plate shape with each side being a flat side wall, and only one side 1a of the mold package section 1 has The external connection terminal group 2 is vertically extended. Here, the external connection terminal 2 group is formed of, for example, a lead frame on which a semiconductor element is mounted, and is led out almost perpendicularly to only one flat side, and has a J-shaped shape whose free end side is bent horizontally 2a. Has formed. In this semiconductor device, as shown in a sectional view in FIG. 10, the bent horizontal portion 2a of the external connection terminal group 2 is brought into contact with the surface of the connected terminal 3a of the mounting wiring board 3 and soldered (shown in FIG. 10). (Omitted), etc., so that they are electrically and mechanically connected (mounted).

【0003】[0003]

【発明が解決しようとする課題】上記、垂直実装型の半
導体装置は、面実装型に比べて、実装用配線板に対する
実装面が大幅に低減されるので、平面的なコンパクト化
が図られる。しかし、垂直実装型の半導体装置(半導体
パッケージ)の寸法、あるいは外部接続用端子2群を垂
直に導出した一辺(実装面)1aの最小寸法は、外部接続
用端子2群のリードピッチおよびオーバーハングによっ
て一義的に決まる。つまり、垂直実装型の半導体装置
は、外部接続用端子2の数によって、外部接続用端子2
群を導出できる一辺1aの最小寸法が制約されるため、実
装用配線板3の実装面を大幅に低減できるとはいえ、コ
ンパクト化に限界がある。こうした問題は、外部接続用
端子2の数が必然的に増大化する高性能・高容量化の半
導体装置の垂直型実装を阻害することになり、結果的
に、高性能・高容量で、高密度な実装回路装置の実用化
の支障となる。
In the vertical mounting type semiconductor device, the mounting surface for the mounting wiring board is greatly reduced as compared with the surface mounting type semiconductor device. However, the dimensions of the vertical mounting type semiconductor device (semiconductor package) or the minimum dimension of one side (mounting surface) 1a from which the two external connection terminals are vertically derived are determined by the lead pitch and overhang of the two external connection terminals. Is uniquely determined by That is, the vertical mounting type semiconductor device depends on the number of external connection terminals 2 depending on the number of external connection terminals 2.
Since the minimum dimension of one side 1a from which the group can be derived is restricted, the mounting surface of the mounting wiring board 3 can be significantly reduced, but there is a limit to downsizing. Such a problem hinders the vertical mounting of a high-performance and high-capacity semiconductor device in which the number of external connection terminals 2 is inevitably increased. This hinders the practical use of high-density mounted circuit devices.

【0004】本発明は、このような事情に対してなされ
たもので、高密度な実装回路装置の形成に適する垂直実
装型の半導体装置および実装回路装置の提供を目的とす
る。
The present invention has been made in view of such circumstances, and has as its object to provide a vertically mounted semiconductor device and a mounted circuit device suitable for forming a high-density mounted circuit device.

【0005】[0005]

【課題を解決するための手段】請求項1の発明は、少な
くとも一辺が平坦な側壁面である平板状のパッケージ部
と、前記パッケージ部の平坦な一辺側壁面に垂直に導出
された外部接続用端子群とを有する半導体装置におい
て、前記外部接続用端子群を導出した平坦な一辺側壁面
以外の他の少なくとも一辺に、接続用リード端子を導出
配置したことを特徴とする半導体装置である。
According to a first aspect of the present invention, there is provided a flat package portion having at least one side having a flat side wall surface, and an external connection perpendicular to the flat one side wall surface of the package portion. A semiconductor device having a terminal group, wherein connection lead terminals are led out and arranged on at least one side other than the flat side wall surface from which the external connection terminal group is led out.

【0006】請求項2の発明は、請求項1記載の半導体
装置において、導出された外部接続用端子の自由端部が
ほぼ水平に折り曲げられていることを特徴とする。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the free end of the external connection terminal is bent substantially horizontally.

【0007】請求項3の発明は、請求項1または2記載
の半導体装置において、導出配置した外部接続用端子が
板状であることを特徴とする。
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the external connection terminals which are led out and arranged are plate-shaped.

【0008】請求項4の発明は、請求項1ないし3いず
れか一記載の半導体装置において、導出配置した外部接
続用端子に切欠部が形設されていることを特徴とする。
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a notch is formed in the external connection terminal that is led out and arranged.

【0009】請求項5の発明は、請求項1ないし4いず
れか一記載の半導体装置において、平坦な一辺の側面に
導出され外部接続用端子のうち、少なくとも一つの外部
接続用端子が他の辺側面に導出・配置された外部接続用
リード端子と電気的に接続していることを特徴とする。
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, at least one of the external connection terminals led out to one side surface of the flat side is connected to another side. It is characterized by being electrically connected to an external connection lead terminal which is led out and arranged on the side surface.

【0010】すなわち、本発明は、垂直実装型の半導体
装置(半導体パッケージ)において、平坦な一辺の実装
面のみに外部接続用端子を導出・配置せずに、前記実装
面以外の他の面にも一部の外部接続用端子を導出・配置
し、外部接続用端子数によって制約される半導体装置の
コンパクト化の限界を解消することを骨子としたもので
ある。
That is, according to the present invention, in a vertical mounting type semiconductor device (semiconductor package), external connection terminals are not led out and arranged only on one flat side mounting surface, but are mounted on other surfaces other than the mounting surface. Also, the main point is to derive and arrange some external connection terminals and to eliminate the limit of compactness of a semiconductor device which is limited by the number of external connection terminals.

【0011】本発明では、垂直実装型の半導体装置にお
いて、実装用配線基板に対して実装する外部接続用端子
を主として実装面に、他の外部接続用端子を実装面以外
の他の面にそれぞれ導出・配置されている。つまり、外
部接続用端子が多数個であっても、それら外部接続用端
子は、実装面を含む複数の面に導出・配置されるため、
導出・配置される外部接続用端子数によって、半導体装
置のコンパクト化が制約されることがなくなる。
According to the present invention, in a vertical mounting type semiconductor device, external connection terminals to be mounted on a mounting wiring board are mainly provided on a mounting surface, and other external connection terminals are provided on a surface other than the mounting surface. Derived and arranged. In other words, even if there are many external connection terminals, these external connection terminals are derived and arranged on a plurality of surfaces including the mounting surface,
The number of external connection terminals to be derived and arranged does not restrict the compactness of the semiconductor device.

【0012】[0012]

【発明の実施の形態】以下、図1ないし図8を参照して
実施例を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS.

【0013】図1および図2は、第1の実施例に係る半
導体装置の構成を示すもので、図1は斜視図、図2は正
面図である。図1および図2において、4は半導体装置
であり、少なくとも一辺が平坦な側壁面である平板状の
パッケージ部(たとえば樹脂封止型パッケージ)5と、
前記パッケージ部5の平坦な一辺の側面5aに垂直に導出
された外部接続用端子6a群と、前記外部接続用端子6a群
を導出した平坦な一辺の側面5a以外の他の少なくとも一
辺の側面5b,5cに導出・配置された外部接続用リード端
子6b,6cとを有する構成となっている。
FIGS. 1 and 2 show the structure of the semiconductor device according to the first embodiment. FIG. 1 is a perspective view and FIG. 2 is a front view. 1 and 2, reference numeral 4 denotes a semiconductor device, which is a flat package portion (for example, a resin-sealed package) 5 having at least one side having a flat side wall surface;
A group of external connection terminals 6a which are vertically derived from a flat side surface 5a of the package portion 5 and at least one side surface 5b other than the flat side surface 5a from which the group of external connection terminals 6a are derived. , 5c and external connection lead terminals 6b and 6c.

【0014】上記構成の半導体装置では、外部接続用端
子6aを導出・配置した平坦面5aが実装用配線板に対する
実装面となり、前記外部接続用端子6aが対応する実装用
配線板の被接続部に電気的および機械的に接続される。
一方、前記実装面以外の他の面5b,5cに導出・配置され
た外部接続用リード端子6b,6cは、隣接して実装される
他の半導体装置やチップ抵抗などの電子部品、あるいは
実装用配線板の他の被接続部に電気的および機械的に接
続される。
In the semiconductor device having the above configuration, the flat surface 5a on which the external connection terminals 6a are led out and arranged is a mounting surface for the mounting wiring board, and the external connection terminals 6a are connected to the corresponding connection parts of the mounting wiring board. Electrically and mechanically.
On the other hand, the external connection lead terminals 6b and 6c derived and arranged on the other surfaces 5b and 5c other than the mounting surface are used for mounting other adjacent semiconductor devices and electronic components such as chip resistors, or mounting components. It is electrically and mechanically connected to another connected portion of the wiring board.

【0015】上記半導体装置は、実装面5a以外の他の面
5b,5cも接続用リード端子6b,6cの導出・配置に利用さ
れるため、結果的に、実装用配線板面において半導体装
置が占有する実装面が低減され、実装密度の向上が図ら
れる。また、半導体装置自体における配線長を短縮でき
るので、実装回路装置としての電気的な特性向上などを
図ることができるし、さらに、外部接続用リード端子6
b,6cのリード幅を広めにしておくと、他の実装電子部
品、たとえばチップ抵抗などと安定した接続などを行う
こともできる。
The semiconductor device has a surface other than the mounting surface 5a.
Since 5b and 5c are also used for deriving and arranging the connection lead terminals 6b and 6c, the mounting surface occupied by the semiconductor device on the mounting wiring board surface is reduced, and the mounting density is improved. Further, since the wiring length of the semiconductor device itself can be shortened, the electrical characteristics of the mounted circuit device can be improved, and the external connection lead terminals 6 can be further improved.
If the lead widths of b and 6c are widened, stable connection with other mounted electronic components, for example, a chip resistor or the like can be performed.

【0016】なお、上記半導体装置は、次のような手順
で製造される。たとえば実装用リード部および接続用リ
ード部を有するリードフレームに、半導体素子(半導体
チップ)をマウントする。次いで、半導体チップをマウ
ントしたリードフレームを、所定の金型に位置決め配置
し、封止用樹脂でモールドした後、前記金型から取り外
して、リードフレームを所定位置で切断・分離する。
The above semiconductor device is manufactured by the following procedure. For example, a semiconductor element (semiconductor chip) is mounted on a lead frame having a mounting lead portion and a connection lead portion. Next, the lead frame on which the semiconductor chip is mounted is positioned and arranged in a predetermined mold, molded with a sealing resin, removed from the mold, and cut and separated at a predetermined position.

【0017】その後、前記樹脂モールド層から実装面5a
に導出されている実装用リード(実装用接続端子6aに相
当)の先端側を、一定の方向に、かつ平坦な面を形成す
るように折り曲げ・加工する。また、前記実装面以外の
他の面5b,5cに導出されている接続用リード(外部接続
用端子6b,6cに相当)を、要すれば、成形など加工処理
することにより、平板状の垂直実装型半導体パッケージ
4が得られる。
Thereafter, the mounting surface 5a is removed from the resin mold layer.
The leading end of the mounting lead (corresponding to the mounting connection terminal 6a) that is led out is bent and machined in a certain direction so as to form a flat surface. The connection leads (corresponding to the external connection terminals 6b and 6c) led out to the other surfaces 5b and 5c other than the mounting surface may be processed by molding or the like if necessary. A mounting type semiconductor package 4 is obtained.

【0018】図3 (a), (b)は、第2の実施例に係る半
導体装置の構成を示すもので、図3(a)は正面図、図3
(b)は側面図である。図3 (a), (b)において、4は半
導体装置であり、少なくとも一辺が平坦な側壁面である
平板状のパッケージ部(たとえば樹脂封止型パッケー
ジ)5と、前記パッケージ部5の平坦な一辺5aの側面に
垂直に導出された外部接続用端子6a群と、前記外部接続
用端子6a群を導出した平坦な一辺の側面5a以外の他辺側
面5bに導出・配置された外部接続用リード端子6bとを有
する構成となっている。
FIGS. 3A and 3B show the structure of a semiconductor device according to the second embodiment. FIG. 3A is a front view, and FIG.
(b) is a side view. 3A and 3B, reference numeral 4 denotes a semiconductor device, which is a flat package portion (for example, a resin-sealed package) 5 having at least one flat side wall, and a flat package portion 5. An external connection terminal 6a group which is vertically led out to the side surface of one side 5a, and an external connection lead which is derived and arranged on the other side surface 5b other than the flat side surface 5a from which the external connection terminal 6a group is derived. It has a configuration having a terminal 6b.

【0019】すなわち、この実施例の場合は、実装面5a
以外では側面5bに導出・配置された外部接続用リード端
子6bのみで、かつその外部接続用リード端子6b先端面が
切欠された形状を成している外は、前記第1の実施例の
場合と同様の構成と成っている。
That is, in the case of this embodiment, the mounting surface 5a
Other than the case of the first embodiment, only the external connection lead terminal 6b led out and arranged on the side surface 5b, and the outer connection lead terminal 6b has a cutout tip end surface It has the same configuration as.

【0020】上記構成の半導体装置では、外部接続用端
子6aを導出・配置した平坦面5aが実装用配線板に対する
実装面となり、前記外部接続用端子6aが対応する実装用
配線板の被接続部に電気的および機械的に接続される。
一方、前記実装面以外の他の面5bに導出・配置された外
部接続用リード端子6bは、隣接して実装される他の半導
体装置やチップ抵抗などの電子部品、あるいは実装用配
線板の他の被接続部に電気的および機械的に接続され
る。
In the semiconductor device having the above configuration, the flat surface 5a on which the external connection terminals 6a are led out and arranged becomes a mounting surface for the mounting wiring board, and the external connection terminals 6a correspond to the corresponding connection portions of the mounting wiring board. Electrically and mechanically.
On the other hand, the external connection lead terminals 6b led out and arranged on the other surface 5b other than the mounting surface are used for mounting other adjacent electronic devices such as semiconductor devices and chip resistors, or mounting wiring boards. Electrically and mechanically.

【0021】図4 (a), (b)は、第3の実施例に係る半
導体装置の構成を示すもので、図4(a)は正面図、図4
(b)は側面図である。この半導体装置の基本的な構成
は、前記第1の実施例の場合と同様であり、したがっ
て、図1における構成部と同じ構成部は、同じ符号で示
してしてある。そして、相違点は、外部接続用端子6a群
を導出した平坦な一辺の側面5a以外に、他の辺面5bに外
部接続用リード端子6bのみが導出・配置され、かつその
外部接続用リード端子6bが一部切欠された形状を成して
いることである。
FIGS. 4A and 4B show the structure of a semiconductor device according to the third embodiment. FIG. 4A is a front view and FIG.
(b) is a side view. The basic configuration of this semiconductor device is the same as that of the first embodiment. Therefore, the same components as those in FIG. 1 are denoted by the same reference numerals. The difference is that, in addition to the flat side surface 5a from which the external connection terminals 6a are derived, only the external connection lead terminals 6b are derived and arranged on the other side surface 5b, and the external connection lead terminals are arranged. 6b has a partially cut-out shape.

【0022】この実施例に係る構成の場合も、外部接続
用リード端子6bは、その一部切欠部を利用して、第2の
実施例の場合と同様に、隣接して実装される他の半導体
装置やチップ抵抗などの電子部品、あるいは実装用配線
板の他の被接続部に電気的および機械的に接続される。
Also in the case of the configuration according to this embodiment, the external connection lead terminal 6b utilizes another partially cut-out portion, as in the case of the second embodiment, to form another externally mounted lead terminal 6b. It is electrically and mechanically connected to electronic components such as semiconductor devices and chip resistors, or other connected parts of the mounting wiring board.

【0023】図5 (a), (b)は、第4の実施例に係る半
導体装置の構成を示すもので、図5(a)は正面図、図5
(b)は側面図である。この半導体装置の基本的な構成
は、前記第1の実施例の場合と同様であり、したがっ
て、図1における構成部と同じ構成部は、同じ符号で示
してしてある。そして、相違点は、外部接続用端子6a群
を導出した平坦な一辺の側面5a以外に、他の辺面5bに膨
大部を有する外部接続用リード端子6bのみが導出・配置
され、かつその外部接続用リード端子6bの膨大部が一部
切欠された形状を成していることである。
FIGS. 5A and 5B show the configuration of a semiconductor device according to the fourth embodiment. FIG. 5A is a front view, and FIG.
(b) is a side view. The basic configuration of this semiconductor device is the same as that of the first embodiment. Therefore, the same components as those in FIG. 1 are denoted by the same reference numerals. The difference is that, in addition to the flat side surface 5a from which the group of external connection terminals 6a is derived, only the external connection lead terminals 6b having an enlarged portion on the other side surface 5b are led out and arranged, and The enormous portion of the connection lead terminal 6b has a partially cut-out shape.

【0024】この実施例に係る構成の場合も、外部接続
用リード端子6bは、その先端側を折り曲げて他の半導体
装置4の外部接続用リード端子6bの一部切欠部に係合・
半田付けして、第2の実施例の場合と同様に、隣接して
実装される他の半導体装置と電気的に接続される。
Also in the case of the structure according to this embodiment, the external connection lead terminal 6b is bent at its tip end so as to engage with a partially cutout portion of the external connection lead terminal 6b of another semiconductor device 4.
By soldering, similarly to the second embodiment, it is electrically connected to another semiconductor device mounted adjacently.

【0025】図6は、半導体装置を実装用配線板に実装
した構成の概略を示す側面図である。すなわち、実装用
配線板7の所定領域に、前記第2もしくは第3の実施例
に係る半導体装置4の実装面(外部接続用端子6a群を導
出した平坦な面)5aを位置合わせし、対応する実装用配
線板7の被接続部7aおよび外部接続用端子6aを半田付け
・接合などにより、複数個の半導体装置4を実装用配線
板7に搭載・実装した構成例を示すものである。
FIG. 6 is a side view schematically showing a configuration in which the semiconductor device is mounted on a mounting wiring board. That is, the mounting surface (the flat surface from which the external connection terminals 6a are derived) 5a of the semiconductor device 4 according to the second or third embodiment is aligned with a predetermined region of the mounting wiring board 7, and This shows an example of a configuration in which a plurality of semiconductor devices 4 are mounted and mounted on a mounting wiring board 7 by soldering, joining, or the like, of a connected portion 7a of the mounting wiring board 7 and an external connection terminal 6a.

【0026】ここで、側面5bに導出・配置されている外
部接続用リード端子6bの一部切欠部には、それら一部切
欠部を利用して懸架され、かつ半田付けなどで接合・固
定された導電体8で、複数個の半導体装置4が電気的お
よび機械的に接合されている。 この実装構造の場合
は、搭載・実装された複数個の半導体装置4に、同電位
のたとえば電源電圧を供給できる。
The external connection lead terminal 6b led out and arranged on the side surface 5b is partially suspended by using the partial notch, and is joined and fixed by soldering or the like. The plurality of semiconductor devices 4 are electrically and mechanically joined by the conductor 8. In the case of this mounting structure, the same potential, for example, a power supply voltage can be supplied to the plurality of semiconductor devices 4 mounted and mounted.

【0027】図7は、半導体装置を実装用配線板に実装
した他の構成の概略を示す側面図である。すなわち、実
装用配線板7の所定領域に、前記第4の実施例に係る半
導体装置4の実装面(外部接続用端子6a群を導出した平
坦な面)5aを位置合わせし、対応実装用配線板7の被接
続部7aおよび外部接続用端子6aを半田付け・接合などに
より、複数個の半導体装置4を実装用配線板7に搭載・
実装した構成例を示すものである。
FIG. 7 is a side view schematically showing another configuration in which the semiconductor device is mounted on a mounting wiring board. That is, the mounting surface (the flat surface from which the external connection terminals 6a are derived) 5a of the semiconductor device 4 according to the fourth embodiment is aligned with a predetermined region of the mounting wiring board 7, and the corresponding mounting wiring is formed. The plurality of semiconductor devices 4 are mounted on the mounting wiring board 7 by soldering and joining the connected portions 7a of the board 7 and the external connection terminals 6a.
It shows a configuration example implemented.

【0028】ここで、半導体装置4の側面5bに導出・配
置されている外部接続用リード端子6bは、それぞれ折り
曲げられ、その先端部を隣接して実装されている他の半
導体装置4の外部接続用リード端子6bの一部切欠部に嵌
合ないし係合させ、半田付けなどで接合して、複数個の
半導体装置4が電気的および機械的に接合されている。
この実装構造の場合は、半導体装置4同士の電気的な接
続を容易に行えるだけでなく、搭載・実装された複数個
の半導体装置4に、同電位の電源電圧を供給できる。
Here, the external connection lead terminals 6b led out and arranged on the side surface 5b of the semiconductor device 4 are bent, and the ends thereof are connected to the external connection of another semiconductor device 4 mounted adjacently. The plurality of semiconductor devices 4 are electrically and mechanically joined by fitting or engaging with the partially cutout portions of the lead terminals 6b for use and joining them by soldering or the like.
In the case of this mounting structure, not only electrical connection between the semiconductor devices 4 can be easily performed, but also a plurality of mounted and mounted semiconductor devices 4 can be supplied with the same potential power supply voltage.

【0029】図8は、第5の実施例に係る半導体装置の
構成の概略を示す透視的な正面図である。この半導体装
置4の基本的な構成は、前記第2〜4の実施例の場合と
同様であるが、半導体チップを必ずしも搭載していなく
ともよい。第2〜第4の実施例との相違点は、平坦な一
辺の側面5a導出され外部接続用端子6aのうち、少なくと
も一つの外部接続用端子6aが他の辺側面5bに導出・配置
された外部接続用リード端子6bと電気的に接続した構成
と成っていることである。
FIG. 8 is a transparent front view schematically showing the configuration of the semiconductor device according to the fifth embodiment. The basic configuration of the semiconductor device 4 is the same as that of the second to fourth embodiments, but it is not always necessary to mount a semiconductor chip. The difference from the second to fourth embodiments is that at least one external connection terminal 6a is led out and arranged on the other side surface 5b among the flat side surfaces 5a and the external connection terminals 6a. That is, the configuration is such that it is electrically connected to the external connection lead terminal 6b.

【0030】この半導体装置4の場合は、前記第2〜4
の実施例のいずれかに係る半導体装置を組み合わせるこ
とにより、入・出力端子側の配線回路が簡略化した実装
回路装置を構成できる。すなわち、実装用配線板7に対
して,第5の実施例に係る半導体装置および第2の実施
例などに係る半導体装置4を、各実装面5aによって垂直
型に実装する一方、各半導体装置4の側面(上辺)5bに
導出・配置されているおける外部接続用リード端子6b間
同士を電気的に接続するか、あるいは導電体8で外部接
続用リード端子6b間を電気的に接続した実装回路装置を
構成する。
In the case of this semiconductor device 4, the second to fourth
By combining the semiconductor device according to any one of the embodiments, a mounting circuit device with a simplified wiring circuit on the input / output terminal side can be configured. That is, the semiconductor device according to the fifth embodiment and the semiconductor device 4 according to the second embodiment and the like are vertically mounted on the mounting wiring board 7 by the respective mounting surfaces 5a. A mounting circuit in which the external connection lead terminals 6b led out and arranged on the side surface (upper side) 5b are electrically connected to each other, or the conductor 8 electrically connects the external connection lead terminals 6b. Configure the device.

【0031】このようにして、実装構造を採った場合
は、前記実装回路装置の構成における搭載・実装する半
導体装置同士、あるいは他の電子部品との電気的な接続
など、より容易に行えるし、また、搭載・実装された半
導体装置4や電子部品に、同電位のたとえば電源電圧を
供給できる。
In this way, when the mounting structure is adopted, the semiconductor devices to be mounted / mounted in the configuration of the mounting circuit device can be more easily connected to each other, or electrically connected to other electronic components. In addition, the same potential, for example, a power supply voltage can be supplied to the mounted and mounted semiconductor device 4 and electronic components.

【0032】なお、本発明は、上記例示に限定されるも
のでなく、発明の趣旨を逸脱しない範囲で、いろいろの
変形を採ることができる。
The present invention is not limited to the above-described example, and various modifications can be made without departing from the spirit of the invention.

【0033】[0033]

【発明の効果】請求項1〜5の発明によれば、実装用配
線基板に対して実装する外部接続用端子を主として実装
面に、他の外部接続用端子を実装面以外の面にも導出・
配置した構成を採っている。つまり、外部接続用端子
は、実装面を含む複数の面に導出・配置されるため、導
出・配置される外部接続用端子数によって、半導体装置
のコンパクト化が左右されることがなくなる。
According to the first to fifth aspects of the present invention, the external connection terminals to be mounted on the mounting wiring board are mainly derived on the mounting surface, and the other external connection terminals are also derived on surfaces other than the mounting surface.・
It adopts a configuration that is arranged. That is, since the external connection terminals are led out and arranged on a plurality of surfaces including the mounting surface, the size of the semiconductor device does not depend on the number of the external connection terminals led out and arranged.

【0034】また、垂直型実装において、実装面以外の
面に導出・配置した外部接続用端子を介し、半導体装置
同士あるいは他の電子部品との電気的な接続を容易に行
うことができるし、さらに、その接続の選択によって
は、実装した複数個の半導体装置に共通の電位を付与す
ることもできるので、実装回路装置の構成、機能、用途
などの拡大が図られる。
Further, in the vertical mounting, electrical connection between semiconductor devices or other electronic components can be easily made via external connection terminals derived and arranged on a surface other than the mounting surface. Further, depending on the selection of the connection, a common potential can be applied to a plurality of mounted semiconductor devices, so that the configuration, functions, applications, and the like of the mounted circuit device can be expanded.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施例に係る半導体装置の概略構成を示
す斜視図。
FIG. 1 is a perspective view showing a schematic configuration of a semiconductor device according to a first embodiment.

【図2】第1の実施例に係る垂直実装型の半導体装置の
概略構成を示す正面図。
FIG. 2 is a front view showing a schematic configuration of a vertically mounted semiconductor device according to the first embodiment.

【図3】第2の実施例に係る垂直実装型の半導体装置の
概略構成を示すもので、 (a)は正面図、 (b)は側面図。
3A and 3B show a schematic configuration of a vertical mounting type semiconductor device according to a second embodiment, wherein FIG. 3A is a front view and FIG. 3B is a side view.

【図4】第3の実施例に係る垂直実装型の半導体装置の
概略構成を示すもので、 (a)は正面図、 (b)は側面図。
4A and 4B show a schematic configuration of a vertical mounting type semiconductor device according to a third embodiment, wherein FIG. 4A is a front view and FIG. 4B is a side view.

【図5】第4の実施例に係る垂直実装型の半導体装置の
概略構成を示すもので、 (a)は正面図、 (b)は側面図。
5A and 5B show a schematic configuration of a vertical mounting type semiconductor device according to a fourth embodiment, wherein FIG. 5A is a front view, and FIG. 5B is a side view.

【図6】本発明に係る垂直実装型半導体装置の複数個を
実装用配線板に搭載・実装した概略構造を示す側面図。
FIG. 6 is a side view showing a schematic structure in which a plurality of vertically mounted semiconductor devices according to the present invention are mounted and mounted on a mounting wiring board.

【図7】本発明に係る垂直実装型半導体装置の複数個を
実装用配線板に搭載・実装した他の概略構造を示す側面
図。
FIG. 7 is a side view showing another schematic structure in which a plurality of vertically mounted semiconductor devices according to the present invention are mounted and mounted on a mounting wiring board.

【図8】第5の実施例に係る垂直実装型の半導体装置の
概略構成を透視的に示す正面図。
FIG. 8 is a front view showing a schematic configuration of a vertically mounted semiconductor device according to a fifth embodiment in a see-through manner.

【図9】従来の垂直実装型の半導体装置の概略構成を示
す斜視図。
FIG. 9 is a perspective view showing a schematic configuration of a conventional vertical mounting type semiconductor device.

【図10】従来の垂直実装型半導体装置の複数個を実装
用配線板に搭載・実装した他の概略構造を示す側面図。
FIG. 10 is a side view showing another schematic structure in which a plurality of conventional vertical mounting semiconductor devices are mounted and mounted on a mounting wiring board.

【符号の説明】[Explanation of symbols]

4……垂直実装型の半導体装置 5……モールドパッケージ部 5a……半導体装置の実装面 5b,5c……実装面以外の半導体装置の辺面 6a……実装面の外部接続用端子 6b,6c……実装面以外の外部接続用端子 7……実装用配線板 8……導電体 4 Vertical mounting type semiconductor device 5 Mold package section 5a Semiconductor device mounting surface 5b, 5c Side surface of semiconductor device other than mounting surface 6a External connection terminals 6b, 6c on mounting surface ... Terminals for external connection other than the mounting surface 7... Wiring board for mounting 8.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも一辺が平坦な側壁面である平
板状のパッケージ部と、前記パッケージ部の平坦な一辺
側壁面に垂直に導出された外部接続用端子群とを有する
半導体装置において、 前記外部接続用端子群を導出した平坦な一辺側壁面以外
の他の少なくとも一辺に、接続用リード端子を導出配置
したことを特徴とする半導体装置。
1. A semiconductor device comprising: a flat package portion having at least one side having a flat side wall surface; and an external connection terminal group perpendicularly extended to the flat one side wall surface of the package portion. A semiconductor device wherein connection lead terminals are led out and arranged on at least one side other than the flat one side wall surface from which the connection terminal group is led out.
【請求項2】 導出された外部接続用端子の自由端部が
ほぼ水平に折り曲げられていることを特徴とする請求項
1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a free end of the derived external connection terminal is bent substantially horizontally.
【請求項3】 導出配置した外部接続用端子が板状であ
ることを特徴とする請求項1または2記載の半導体装
置。
3. The semiconductor device according to claim 1, wherein the external connection terminals led out and arranged are plate-shaped.
【請求項4】 導出配置した外部接続用端子に切欠部が
形設されていることを特徴とする請求項1ないし3いず
れか一記載の半導体装置。
4. The semiconductor device according to claim 1, wherein a notch is formed in the external connection terminal which is led out and arranged.
【請求項5】 平坦な一辺の側面に導出され外部接続用
端子のうち、少なくとも一つの外部接続用端子が他の辺
側面に導出・配置された外部接続用リード端子と電気的
に接続していることを特徴とする半導体装置。
5. At least one of the external connection terminals led out to one flat side surface is electrically connected to an external connection lead terminal led out and arranged on the other side surface. A semiconductor device.
JP16757997A 1997-06-24 1997-06-24 Semiconductor device Pending JPH1117093A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16757997A JPH1117093A (en) 1997-06-24 1997-06-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16757997A JPH1117093A (en) 1997-06-24 1997-06-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1117093A true JPH1117093A (en) 1999-01-22

Family

ID=15852373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16757997A Pending JPH1117093A (en) 1997-06-24 1997-06-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1117093A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2006061879A1 (en) * 2004-12-06 2008-06-05 株式会社ルネサステクノロジ Ignition device, semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2006061879A1 (en) * 2004-12-06 2008-06-05 株式会社ルネサステクノロジ Ignition device, semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP4264375B2 (en) Power semiconductor module
JPH0513666A (en) Complex semiconductor device
US5635760A (en) Surface mount semiconductor device
JP3656861B2 (en) Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
JPH1117093A (en) Semiconductor device
JP2524482B2 (en) QFP structure semiconductor device
JP2541532B2 (en) Semiconductor module
JP3159950B2 (en) Socket for mounting semiconductor package
KR100373149B1 (en) Semiconductor package
JP3308078B2 (en) Resin-sealed semiconductor device
JPH05343610A (en) Hybrid integrated circuit device
JPS62134945A (en) Molded transistor
JPH0343728Y2 (en)
JP2912813B2 (en) Electronic components
JPH04343257A (en) Semiconductor integrated circuit package
JP3589941B2 (en) Semiconductor device
KR0161813B1 (en) Semiconductor package
KR100206975B1 (en) Semiconductor package
KR200154508Y1 (en) Socket for semiconductor package module
JP2555991B2 (en) package
JPH05144996A (en) Surface mounting semiconductor device
JPH04167551A (en) Surface mounting ic package
JP2020068332A (en) Optical module, optical module mounting board, and container
JPH065732A (en) Semiconductor device
JPS59143355A (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20021210