JPH11168118A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH11168118A
JPH11168118A JP9332888A JP33288897A JPH11168118A JP H11168118 A JPH11168118 A JP H11168118A JP 9332888 A JP9332888 A JP 9332888A JP 33288897 A JP33288897 A JP 33288897A JP H11168118 A JPH11168118 A JP H11168118A
Authority
JP
Japan
Prior art keywords
metal
semiconductor chip
foil
thick
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9332888A
Other languages
Japanese (ja)
Inventor
Noriyoshi Arai
規由 新井
Hideki Tsukamoto
英樹 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9332888A priority Critical patent/JPH11168118A/en
Publication of JPH11168118A publication Critical patent/JPH11168118A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To contrive to reduce a size and costs by a method, wherein a step is formed in a metal thick foil of a substrate, and a shift-back region of a wire bonder is dispensed with, and a substrate size is reduced. SOLUTION: A metal thick foil jointed to a metal base plate 2 via an insulation layer 4 is set as a metal thick foil 13 with a step. Namely, a step is provided in the thickness of a wire joint part 13A and a semiconductor chip solder part 13B in the metal thick foil 13 with a step such that the height from the insulation layer 4 of the wire joint part 13A which joints a wire 7 is higher than that from the insulation layer 4 on a crest face of a semiconductor chip 5 soldered, and it is possible to shift back on a semiconductor chip 5A after wire bonding, and a shift-back region SB is dispensed with.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、金属厚箔付金属
基板若しくは金属厚箔付絶縁メタライズ基板を用いた半
導体装置及びその製造方法に関するものである。The present invention relates to a semiconductor device using a metal substrate with a thick metal foil or an insulated metallized substrate with a thick metal foil and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】図３は従来の半導体装置におけるパッケ
ージの平面図、図４は同パッケージの断面図であり、図
５は図４に示した半導体装置における金属厚箔付金属基
板部分の断面を示す拡大図である。図３〜図５におい
て、１は半導体装置の樹脂ケース、１Ａは樹脂ケース１
に形成された取付穴、２は金属ベース板、３は金属厚
箔、４は絶縁層であり、複数枚の金属厚箔３が金属ベー
ス板２における絶縁層４の表面上に設けられており、金
属ベース板２、複数の金属厚箔３及び絶縁層４にて金属
厚箔付金属基板を構成している。2. Description of the Related Art FIG. 3 is a plan view of a package in a conventional semiconductor device, FIG. 4 is a sectional view of the package, and FIG. 5 is a sectional view of a metal substrate with a thick metal foil in the semiconductor device shown in FIG. FIG. 3 to 5, reference numeral 1 denotes a resin case of a semiconductor device, and 1A denotes a resin case 1.
2, a metal base plate, 3 a metal thick foil, 4 is an insulating layer, and a plurality of metal thick foils 3 are provided on the surface of the insulating layer 4 in the metal base plate 2. , A metal base plate 2, a plurality of thick metal foils 3 and an insulating layer 4 constitute a metal substrate with a thick metal foil.

【０００３】５は半導体チップ、６は半田であり、半導
体チップ５は半田６にて金属厚箔３に半田付けされてい
る。７は金属厚箔３と半導体チップ５との間、その他を
電気的に接続する金、アルミ等の金属細線であり、以下
ワイヤーと記載する。８は外部電極（端子）、８Ａは内
部電極、９は半導体チップ５、ワイヤー７等を保護する
シリコンゲルである。[0005] Reference numeral 5 denotes a semiconductor chip, 6 denotes solder, and the semiconductor chip 5 is soldered to the thick metal foil 3 by solder 6. Reference numeral 7 denotes a thin metal wire such as gold or aluminum for electrically connecting between the thick metal foil 3 and the semiconductor chip 5 and others, and is hereinafter referred to as a wire. Reference numeral 8 denotes an external electrode (terminal), 8A denotes an internal electrode, 9 denotes a silicon gel for protecting the semiconductor chip 5, the wire 7, and the like.

【０００４】１０はエポキシ樹脂、１１は樹脂フタであ
り、樹脂ケース１の内部の防湿、防塵、その他、保護用
として用いる。１２はワイヤー７を半導体チップ５若し
くは金属厚箔３に超音波接合するワイヤボンド装置、１
２Ａは超音波接合後のワイヤー７を切断する為のシフト
バック後のワイヤボンド装置であり、ＳＢはワイヤー７
を切断する為に必要なシフトバック領域（距離）を示
す。尚、図３に示したパッケージの平面図は内部構造が
わかるように、図４に示した同パッケージの断面図にお
けるシリコンゲル９、エポキシ樹脂１０、樹脂フタ１１
が省略されている。[0004] Reference numeral 10 denotes an epoxy resin, and 11 denotes a resin lid, which is used for protecting the inside of the resin case 1 from moisture, dust, and the like. Reference numeral 12 denotes a wire bonding apparatus for ultrasonically bonding the wire 7 to the semiconductor chip 5 or the thick metal foil 3;
2A is a wire bonding device after shift back for cutting the wire 7 after the ultrasonic bonding, and SB is the wire bonding device after the shift back.
Indicates the shift-back area (distance) required to cut off the shift. In the plan view of the package shown in FIG. 3, the silicon gel 9, epoxy resin 10, and resin lid 11 in the sectional view of the package shown in FIG.
Has been omitted.

【０００５】次に、従来の半導体装置の製造方法につい
て説明する。金属厚箔付金属基板を構成する複数の金属
厚箔３にそれぞれ半導体チップ５を半田付けしたものが
樹脂ケース１に取付けられ、内部電極８と金属厚箔３に
半田付けされた半導体チップ５との間、この半導体チッ
プ５と別の金属厚箔３に形成されたワイヤー接合部３Ａ
との間等がワイヤー７により接続される。このワイヤー
７による接続はワイヤボンド装置１２を用いた超音波接
合による。ワイヤボンド装置１２はワイヤー７を金属厚
箔３に超音波接合後、ワイヤー７を切断する為に数ｍｍ
シフトバックを行ない、図５におけるシフトバック後の
ワイヤボンド装置１２Ａの位置まで後退する。Next, a conventional method for manufacturing a semiconductor device will be described. A semiconductor chip 5 soldered to a plurality of metal thick foils 3 constituting a metal substrate with a metal thick foil is attached to the resin case 1, and the internal chip 8 and the semiconductor chip 5 soldered to the metal thick foil 3 During this time, a wire bonding portion 3A formed on this semiconductor chip 5 and another metal thick foil 3
Are connected by a wire 7. The connection by the wire 7 is performed by ultrasonic bonding using a wire bonding device 12. The wire bonding device 12 ultrasonically bonds the wire 7 to the metal thick foil 3 and then cuts the wire 7 by several mm.
The shift back is performed, and the wire bonding apparatus 12A is retracted to the position of the wire bonding apparatus 12A after the shift back in FIG.

【０００６】従来の金属厚箔３はほぼフラットな形状で
あるから、ワイヤボンド装置１２のシフトバック領域Ｓ
Ｂに半導体チップ５が半田付けされていると、ワイヤボ
ンド装置１２が半導体チップ５と衝突し、ワイヤボンド
装置１２若しくは半導体チップ５を傷つけてしまう。そ
れ故に、ワイヤボンド装置１２の後退する側にシフトバ
ック領域ＳＢを確保する必要があるが、この事は金属ベ
ース板２、即ち、前記、金属厚箔付金属基板の面積が増
大し、半導体装置の縮小化を妨げる要因となっていた。Since the conventional thick metal foil 3 has a substantially flat shape, the shift back area S of the wire bonding apparatus 12
If the semiconductor chip 5 is soldered to B, the wire bonding apparatus 12 collides with the semiconductor chip 5 and damages the wire bonding apparatus 12 or the semiconductor chip 5. Therefore, it is necessary to secure the shift back area SB on the retreating side of the wire bonding apparatus 12, which means that the area of the metal base plate 2, that is, the metal substrate with a thick metal foil increases, and the semiconductor device This was a factor that hindered the reduction in size.

【０００７】図５に示した従来の半導体装置は、基板と
して、非絶縁板としての金属ヘ゛ース板２の片面に絶縁層４
を形成し、この絶縁層４に金属厚箔３を接合した金属厚
箔付金属基板を用いたものであったが、絶縁板の両面に
金属厚箔３を直接接合した金属厚箔付絶縁メタライズ基
板を用いたものであっても同様であり、前記金属厚箔付
絶縁メタライズ基板の面積が増大し、半導体装置の縮小
化を妨げる要因となっていた。In the conventional semiconductor device shown in FIG. 5, an insulating layer 4 is formed on one side of a metal base plate 2 as a non-insulating plate as a substrate.
And a metal substrate with a thick metal foil in which the thick metal foil 3 is bonded to the insulating layer 4 is used. However, an insulating metallization with a thick metal foil in which the thick metal foil 3 is directly bonded to both surfaces of the insulating plate is used. The same applies to the case where a substrate is used, and the area of the insulating metallized substrate with a thick metal foil is increased, which is a factor that hinders the miniaturization of the semiconductor device.

【０００８】[0008]

【発明が解決しようとする課題】従来の半導体装置は、
以上のように構成されているので、金属厚箔付金属基板
や金属厚箔付絶縁メタライズ基板において、ワイヤボン
ド装置１２のシフトバック領域ＳＢを確保しなければな
らず、金属厚箔３を広くする事が必要で、上記金属厚箔
付金属基板や金属厚箔付絶縁メタライズ基板の外形の縮
小化、即ち、半導体装置の外形の縮小化の妨げになり、
ひいては、半導体装置の製造コスト低減の妨げになるな
どの問題点があった。A conventional semiconductor device is:
With the above configuration, the shift back area SB of the wire bonding apparatus 12 must be secured in the metal substrate with a thick metal foil or the insulated metallized substrate with a thick metal foil, and the thick metal foil 3 is widened. It is necessary to reduce the outer shape of the metal substrate with the thick metal foil or the insulating metallized substrate with the thick metal foil, that is, hinder the reduction in the outer shape of the semiconductor device,
As a result, there has been a problem that reduction in manufacturing cost of the semiconductor device is hindered.

【０００９】この発明は、上記のような問題点を解消す
るためになされたものであり、金属厚箔付金属基板や金
属厚箔付絶縁メタライズ基板の縮小化を図ることによ
り、小型化及びコスト低減を図った半導体装置及びその
製造方法を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is intended to reduce the size of a metal substrate with a thick metal foil or an insulated metallized substrate with a thick metal foil to reduce the size and cost. It is an object of the present invention to obtain a reduced semiconductor device and a method for manufacturing the same.

【００１０】[0010]

【課題を解決するための手段】第１の発明に係る半導体
装置は、絶縁板若しくは表面に絶縁層を形成した非絶縁
板からなる基板と、該基板に設けられた金属厚箔と、該
金属厚箔上に半田付けした半導体チップとを備えた半導
体装置において、前記金属厚箔は、金属線を接合する金
属線接合部が形成され、該金属線接合部における前記基
板からの高さが半田付けされた前記半導体チップの上表
面における前記基板からの高さと略等しく若しくはより
高くなるように、前記金属線接合部と前記半導体チップ
の半田付部の厚さに段差を設けたものである。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a substrate formed of an insulating plate or a non-insulating plate having an insulating layer formed on a surface thereof; a metal thick foil provided on the substrate; In a semiconductor device comprising a semiconductor chip soldered on a thick foil, the metal thick foil is formed with a metal wire joining portion for joining a metal wire, and the height of the metal wire joining portion from the substrate is set to A step is provided in the thickness of the metal wire bonding portion and the soldered portion of the semiconductor chip so that the height of the upper surface of the attached semiconductor chip from the substrate is substantially equal to or higher than the height.

【００１１】第２の発明に係る半導体装置は、第１の発
明に係る半導体装置において、金属厚箔における金属線
接合部と半導体チップの半田付部との段差が前記金属線
接合部に別の金属厚箔を張合わせて形成されたものであ
る。A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein a step between the metal wire joint in the thick metal foil and the soldered portion of the semiconductor chip is different from the metal wire joint. It is formed by bonding thick metal foils.

【００１２】第３の発明に係る半導体装置は、第１の発
明に係る半導体装置において、金属厚箔における金属線
接合部と半導体チップの半田付部との段差は前記金属厚
箔の部分エッチングにより形成されたものである。A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect of the present invention, wherein a step between a metal wire bonding portion and a soldered portion of the semiconductor chip in the metal thick foil is partially etched by the metal thick foil. It was formed.

【００１３】第４の発明に係る半導体装置の製造方法
は、絶縁板若しくは表面に絶縁層を形成した非絶縁板か
らなる基板を準備する工程と、別途、半導体チップの半
田付部と金属線接合部とを備え、金属線接合部が前記半
導体チップの半田付部よりも該半田付部の半田厚さを含
む前記半導体チップの厚さと略等しい若しくはより厚い
段差を設けた段差付金属厚箔を準備する工程と、該段差
付金属厚箔を前記基板に接合する工程と、前記段差付金
属厚箔に前記半導体チップを半田付けする工程と、前記
段差付金属厚箔の金属線接合部に金属線をワイヤボンド
装置を用いて超音波接合する工程と、該ワイヤボンド装
置による超音波接合後に、前記金属線接合部に接合した
金属線を切断すべく、前記ワイヤボンド装置が半田付け
された前記半導体チップの頭上をシフトバックする工程
とからなる方法である。A method of manufacturing a semiconductor device according to a fourth aspect of the present invention includes a step of preparing a substrate made of an insulating plate or a non-insulating plate having an insulating layer formed on the surface, and separately connecting a soldered portion of a semiconductor chip to a metal wire. Step, the metal wire joint portion is provided with a stepped metal thick foil provided with a step substantially equal to or thicker than the thickness of the semiconductor chip including the solder thickness of the soldered portion than the soldered portion of the semiconductor chip. Preparing, bonding the stepped metal thick foil to the substrate, soldering the semiconductor chip to the stepped metal thick foil, and applying a metal to the metal wire joint of the stepped metal thick foil. The step of ultrasonically bonding the wire using a wire bonding device, and after the ultrasonic bonding by the wire bonding device, the wire bonding device is soldered to cut the metal wire bonded to the metal wire bonding portion. Semiconductor chip A method comprising the step of shifting back the overhead flop.

【００１４】[0014]

【発明の実施の形態】実施の形態１．この発明の実施の
形態１を図１に基づき説明する。図１は半導体装置にお
ける金属厚箔付金属基板の部分の断面を示す拡大図であ
る。図中、従来例と同じ符号で示されたものは従来例の
それと同一若しくは同等なものを示す。尚、半導体装置
におけるパッケージは図１及び図２に示した従来例とほ
ぼ同じであり、図示を省略する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is an enlarged view showing a cross section of a portion of a metal substrate with a thick metal foil in a semiconductor device. In the figure, those denoted by the same reference numerals as those of the conventional example indicate the same or equivalent parts as those of the conventional example. The package of the semiconductor device is almost the same as the conventional example shown in FIGS. 1 and 2, and the illustration is omitted.

【００１５】図において、１３は金属ベース板２に絶縁
層４を介して設けられた段差付金属厚箔である。段差付
金属厚箔１３における高い段差の位置にワイヤー接合部
１３Ａが形成されており、別の金属厚箔３に半田付けさ
れた半導体チップ５とワイヤー７にて接続される。ワイ
ヤー接合部１３Ａと半導体チップの半田付部１３Ｂとの
間の段差は半導体チップ５Ａの厚さより厚く形成されて
いる。即ち、段差付金属厚箔１３におけるワイヤー接合
部１３Ａの高さが、半導体チップ５Ａの半田付部１３Ｂ
における半導体チップ５Ａの上部面の高さより高く形成
されている。In FIG. 1, reference numeral 13 denotes a stepped metal thick foil provided on the metal base plate 2 with the insulating layer 4 interposed therebetween. A wire joint 13A is formed at a position of a high step in the stepped metal thick foil 13, and is connected to the semiconductor chip 5 soldered to another metal thick foil 3 by a wire 7. The step between the wire bonding portion 13A and the soldering portion 13B of the semiconductor chip is formed thicker than the thickness of the semiconductor chip 5A. That is, the height of the wire joining portion 13A in the stepped metal thick foil 13 is the same as the soldering portion 13B of the semiconductor chip 5A.
Is formed higher than the height of the upper surface of the semiconductor chip 5A.

【００１６】次に、半導体装置の製造方法について説明
する。まず、金属ベース板２を準備し、該金属ベース板
２に絶縁層４を形成する。別途、金属厚箔３、及び、ワ
イヤー接合部１３Ａと半導体チップ５Ａの半田付部１３
Ｂとを備え、ワイヤー接合部１３Ａが半田付部１３Ｂよ
りも半田付部１３Ｂの半田厚さを含む半導体チップ５Ａ
の厚さと略等しい若しくはより厚い段差を設けた段差付
金属厚箔１３を準備する。次に、複数の金属厚箔３及び
複数の段差付金属厚箔１３を金属ベース板２の絶縁層４
に接合して、金属ベース板２、絶縁層４、複数の金属厚
箔３及び複数の段差付金属厚箔１３からなる金属厚箔付
金属基板を製造する。Next, a method of manufacturing a semiconductor device will be described. First, a metal base plate 2 is prepared, and an insulating layer 4 is formed on the metal base plate 2. Separately, the metal thick foil 3, the wire bonding portion 13A and the soldering portion 13 of the semiconductor chip 5A
B, wherein the wire bonding portion 13A includes a solder thickness of the soldered portion 13B more than the soldered portion 13B.
The stepped metal thick foil 13 provided with a step approximately equal to or thicker than the thickness of the step is prepared. Next, the plurality of metal thick foils 3 and the plurality of stepped metal thick foils 13 are connected to the insulating layer 4 of the metal base plate 2.
Then, a metal substrate with a metal thick foil including the metal base plate 2, the insulating layer 4, the plurality of metal thick foils 3, and the plurality of stepped metal thick foils 13 is manufactured.

【００１７】次に、複数の金属厚箔３及び複数の段差付
金属厚箔１３の半田付部１３Ｂのそれぞれに半導体チッ
プ５、５Ａを半田付けする。次に、半導体チップ５、５
Ａを半田付けした前記金属厚箔付金属基板を外部電極８
及び該外部電極８と導通した内部電極８Ａを備えた半導
体ケース１に装着する。次に、内部電極８Ａと金属厚箔
３に半田付けされた半導体チップ５との間、この半導体
チップ５と段差付金属厚箔１３に形成されたワイヤー接
合部１３Ａとの間等がワイヤー７により、ワイヤボンド
装置１２を用いて超音波接合により接続される。Next, the semiconductor chips 5, 5A are soldered to the soldered portions 13B of the plurality of metal thick foils 3 and the plurality of stepped metal thick foils 13, respectively. Next, the semiconductor chips 5, 5
A is soldered to the metal substrate with a thick metal
And, it is mounted on the semiconductor case 1 provided with the internal electrode 8A electrically connected to the external electrode 8. Next, a wire 7 connects between the internal electrode 8A and the semiconductor chip 5 soldered to the metal thick foil 3, and between the semiconductor chip 5 and a wire joint 13A formed on the stepped metal thick foil 13. Are connected by ultrasonic bonding using a wire bonding apparatus 12.

【００１８】そして、例えばワイヤー接合部１３Ａにワ
イヤー７を超音波接合後は、ワイヤー７を切断する為に
数ｍｍシフトバックを行ない、図１におけるシフトバッ
ク後のワイヤボンド装置１２Ａの位置まで後退する。し
かし、前述の様に、段差付金属厚箔１３におけるワイヤ
ー接合部１３Ａの高さが、半導体チップ半田付部１３Ｂ
における半導体チップ５Ａの上部面の高さより高いの
で、シフトバック領域ＳＢに半導体チップ５Ａが半田付
けされていても、ワイヤボンド装置１２が半導体チップ
５Ａと衝突することはなく、従って、ワイヤボンド装置
１２若しくは半導体チップ５Ａが傷つく恐れはない。After the wire 7 is ultrasonically bonded to the wire bonding portion 13A, for example, the wire 7 is shifted back by several mm in order to cut the wire 7 and retracted to the position of the wire bonding device 12A after the shift back in FIG. . However, as described above, the height of the wire bonding portion 13A in the stepped metal thick foil 13 is different from that of the semiconductor chip soldering portion 13B.
Is higher than the height of the upper surface of the semiconductor chip 5A, the wire bonding apparatus 12 does not collide with the semiconductor chip 5A even if the semiconductor chip 5A is soldered to the shift back area SB. Alternatively, there is no possibility that the semiconductor chip 5A will be damaged.

【００１９】即ち、シフトバック領域ＳＢの確保が不要
であるために、半導体チップ５Ａはシフトバック領域Ｓ
Ｂを考慮することなく、半田付け位置を設定できる。こ
れは、金属ベース板２のサイズ縮小を可能とする。That is, since it is not necessary to secure the shift-back area SB, the semiconductor chip 5A
The soldering position can be set without considering B. This enables the size of the metal base plate 2 to be reduced.

【００２０】実施の形態２．この発明の実施の形態２を
図２に基づき説明する。図２は半導体装置における金属
厚箔付絶縁メタライズ基板の断面を示す拡大図である。
図において、１４は絶縁板であり、図における絶縁板１
４の下面側に金属厚箔３が、上面側に金属厚箔３及び段
差付金属厚箔１３がメタライズされている。尚、絶縁板
１４及びこの両面に接合された金属厚箔３、片面にのみ
接合された段差付金属厚箔１３等により金属厚箔付絶縁
メタライズ基板を構成する。１５は金属ベース板（放熱
板）であり、絶縁板１４の下面側の金属厚箔３と半田付
けされ、前記金属厚箔付絶縁メタライズ基板と一体化さ
れている。Embodiment 2 Embodiment 2 of the present invention will be described with reference to FIG. FIG. 2 is an enlarged view showing a cross section of an insulating metallized substrate with a thick metal foil in a semiconductor device.
In the figure, reference numeral 14 denotes an insulating plate.
4, the metal thick foil 3 is metallized on the lower surface side, and the metal thick foil 3 and the metal thick foil 13 with steps are metallized on the upper surface side. The insulating metallized substrate with a thick metal foil is constituted by the insulating plate 14, the thick metal foil 3 bonded to both surfaces thereof, the thick metal foil 13 with a step bonded to only one surface, and the like. Reference numeral 15 denotes a metal base plate (heat radiating plate) which is soldered to the metal thick foil 3 on the lower surface side of the insulating plate 14 and is integrated with the insulating metallized substrate with the metal thick foil.

【００２１】図１に示した実施の形態１における金属厚
箔付金属基板が、非絶縁板として金属ベース板２に絶縁
層４を介して段差付金属厚箔１３等が接合されているの
に対して、実施の形態２における金属厚箔付絶縁メタラ
イズ基板は、絶縁板１４に直接、段差付金属厚箔１３等
が接合されている点が異なるだけで、その他の構成は両
者同じである。従って、金属厚箔付絶縁メタライズ基板
を用いた半導体装置も、この金属厚箔付絶縁メタライズ
基板のサイズ縮小による半導体装置の小型化とコスト低
減を可能とする。Although the metal substrate with a thick metal foil in the first embodiment shown in FIG. 1 has a metal thick plate with a step 13 and the like bonded to a metal base plate 2 via an insulating layer 4 as a non-insulating plate. On the other hand, the insulated metallized substrate with the thick metal foil in the second embodiment is different from the first embodiment only in that the metal thick foil with a step 13 and the like are directly joined to the insulating plate 14, and the other configurations are the same. Therefore, a semiconductor device using an insulating metallized substrate with a thick metal foil can also reduce the size and cost of the semiconductor device by reducing the size of the insulating metallized substrate with a thick metal foil.

【００２２】図１、図２に示した実施の形態１、２にお
ける段差付金属厚箔１３は、（１）従来の厚さの金属厚
箔における段差付部に別の金属厚箔を貼り合せる方法に
より製造したものであるが、（２）金属厚箔における段
差付部にマスキングを行い、金属厚箔のエッチング時間
をコントロールして段差を設ける方法、即ち、エッチン
グ時間を長くすると金属厚箔は薄くなり、短くすると厚
くなるので、エッチング時間により厚みをコントロール
する方法、（３）成形により段差付部を作る方法等によ
っても、比較的安価に製造することができる。The stepped metal thick foils 13 in the first and second embodiments shown in FIGS. 1 and 2 are as follows: (1) Another metal thick foil is bonded to a stepped portion of a conventional thick metal foil. (2) A method of providing a step by masking the stepped portion of the metal thick foil and controlling the etching time of the metal thick foil, that is, if the etching time is increased, the metal thick foil becomes Since it becomes thinner when it is made thinner and becomes thinner when it is shortened, it can be manufactured relatively inexpensively by a method of controlling the thickness by etching time, (3) a method of forming a stepped portion by molding, or the like.

【００２３】尚、段差付金属厚箔１３におけるワイヤボ
ンド箇所の金属厚箔１３Ａの高さを同段差付金属厚箔１
３に半田付けされた半導体チップ５の頂上面より高くし
たが、水平方向にシフトバックするワイヤボンド装置１
２が半田付けされた半導体チップ５に衝突しなければよ
く、超音波接合時にワイヤボンド装置１２により押しつ
ぶされた後のワイヤー７の厚さ相当の余裕の範囲内で略
同一であってもよい。The height of the metal thick foil 13A at the wire bonding position in the stepped metal thick foil 13 is set to
3 is higher than the top surface of the semiconductor chip 5 soldered to the wire bonding device 3, but shifts back in the horizontal direction.
As long as the wire 2 does not collide with the soldered semiconductor chip 5, the wire 2 may be substantially the same within a margin corresponding to the thickness of the wire 7 after being crushed by the wire bonding device 12 during ultrasonic bonding.

【００２４】[0024]

【発明の効果】第１の発明によれば、基板に接合された
金属厚箔における金属線接合部の前記基板からの高さが
半田付けされた半導体チップ頂上面の前記基板からの高
さと略等しく若しくはより高くなるように、前記金属線
接合部と前記半導体チップの半田付部の厚さに段差を設
けたので、又、第４の発明によれば、前記の如き段差付
きの金属厚箔を用いて半導体チップを半田付した基板を
製造したので、ワイヤボンド装置が半田付けされた前記
半導体チップの頭上を後退でき、シフトバック領域確保
が不要となり、この結果として前記基板面積を小さくで
き、小型化とコスト低減を図った半導体装置及びその製
造方法が得られる効果がある。According to the first aspect of the present invention, the height of the metal wire bonding portion of the metal thick foil bonded to the substrate from the substrate is substantially equal to the height of the top surface of the soldered semiconductor chip from the substrate. According to the fourth aspect of the present invention, a step is provided in the thickness of the metal wire bonding portion and the soldered portion of the semiconductor chip so as to be equal or higher. Since the substrate to which the semiconductor chip was soldered was manufactured by using the above, the wire bonding apparatus can retreat above the soldered semiconductor chip, and it is not necessary to secure a shift back area, and as a result, the substrate area can be reduced, There is an effect that a semiconductor device and a method of manufacturing the semiconductor device which are reduced in size and cost can be obtained.

【００２５】又、第２の発明によれば、金属厚箔におけ
るワイヤー接合部と半導体チップを半田付けした部分間
の段差を、前記ワイヤー接合部に別の金属厚箔を張合わ
せることにより形成したので、又、第３の発明によれ
ば、金属厚箔におけるワイヤー接合部と半導体チップを
半田付けした部分間の段差を、金属厚箔のエッチング時
間を調整することにより形成したので、共に、前記段差
付きの金属厚箔を比較的安価に製造でき、比較的安価な
半導体装置が得られる効果がある。According to the second aspect of the present invention, the step between the wire joint and the portion where the semiconductor chip is soldered in the thick metal foil is formed by attaching another thick metal foil to the wire joint. Therefore, according to the third invention, the step between the wire bonding portion and the portion where the semiconductor chip is soldered in the thick metal foil is formed by adjusting the etching time of the thick metal foil. A stepped metal thick foil can be manufactured relatively inexpensively, and a relatively inexpensive semiconductor device can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 第１〜第４の発明の実施の形態１としての半
導体装置における金属厚箔付金属基板部分の断面を示す
拡大図である。FIG. 1 is an enlarged view showing a cross section of a metal substrate portion with a thick metal foil in a semiconductor device as a first embodiment of the first to fourth inventions.

【図２】 第１〜第４の発明の実施の形態２としての半
導体装置における金属厚箔付絶縁メタライズ基板の断面
を示す拡大図である。FIG. 2 is an enlarged view showing a cross section of an insulating metallized substrate with a thick metal foil in a semiconductor device as a second embodiment of the first to fourth inventions;

【図３】 従来の半導体装置におけるパッケージの内部
構造を示した平面図である。FIG. 3 is a plan view showing an internal structure of a package in a conventional semiconductor device.

【図４】 図３に示した半導体装置におけるパッケージ
の断面図である。FIG. 4 is a sectional view of a package in the semiconductor device shown in FIG. 3;

【図５】 従来の半導体装置における金属厚箔付金属基
板部分の断面を示す拡大図である。FIG. 5 is an enlarged view showing a cross section of a metal substrate portion with a thick metal foil in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 樹脂ケース、１Ａ 取付穴、２ 金属ベース板、３
金属厚箔、４ 絶縁層、５、５Ａ 半導体チップ、６
半田、７ ワイヤー、８ 外部電極（端子）、８Ａ
内部電極、９ シリコンゲル、１０ エポキシ樹脂、１
１ 樹脂フタ、１２、１２Ａ ワイヤボンド装置、１３
段差付金属厚箔、１３Ａ ワイヤー接合部、１３Ｂ
半導体チップ半田付部、１４ 絶縁板、１５ 金属ベー
ス板1 resin case, 1A mounting hole, 2 metal base plate, 3
Metal thick foil, 4 insulating layers, 5 and 5A semiconductor chips, 6
Solder, 7 wire, 8 external electrode (terminal), 8A
Internal electrode, 9 Silicon gel, 10 Epoxy resin, 1
1 Resin lid, 12, 12A Wire bonding device, 13
Stepped metal thick foil, 13A Wire joint, 13B
Semiconductor chip soldering part, 14 insulating plate, 15 metal base plate

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 絶縁板若しくは表面に絶縁層を形成した
非絶縁板からなる基板と、該基板に設けられた金属厚箔
と、該金属厚箔上に半田付けした半導体チップとを備え
た半導体装置において、前記金属厚箔は、金属線を接合
する金属線接合部が形成され、該金属線接合部における
前記基板からの高さが半田付けされた前記半導体チップ
の上表面における前記基板からの高さと略等しく若しく
はより高くなるように、前記金属線接合部と前記半導体
チップの半田付部の厚さに段差を設けたことを特徴とす
る半導体装置。1. A semiconductor comprising: a substrate made of an insulating plate or a non-insulating plate having an insulating layer formed on a surface thereof; a metal thick foil provided on the substrate; and a semiconductor chip soldered on the metal thick foil. In the apparatus, the metal thick foil is formed with a metal wire bonding portion for bonding a metal wire, and the height of the metal wire bonding portion from the substrate on the upper surface of the semiconductor chip to which the metal wire bonding portion is soldered. A semiconductor device, wherein a step is provided in the thickness of the metal wire bonding portion and the soldered portion of the semiconductor chip so that the height is substantially equal to or higher than the height. 【請求項２】 請求項１記載の半導体装置において、金
属厚箔における金属線接合部と半導体チップの半田付部
との段差は前記金属線接合部に別の金属厚箔を張合わせ
て形成したことを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the step between the metal wire joint and the soldered portion of the semiconductor chip in the metal thick foil is formed by bonding another metal thick foil to the metal wire joint. A semiconductor device characterized by the above-mentioned. 【請求項３】 請求項１記載の半導体装置において、金
属厚箔における金属線接合部と半導体チップの半田付部
との段差は前記金属厚箔の部分エッチングにより形成し
たことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein a step between the metal wire bonding portion and the soldered portion of the semiconductor chip in the metal thick foil is formed by partial etching of the metal thick foil. . 【請求項４】 絶縁板若しくは表面に絶縁層を形成した
非絶縁板からなる基板を準備する工程と、別途、半導体
チップの半田付部と金属線接合部とを備え、金属線接合
部が前記半導体チップの半田付部よりも該半田付部の半
田厚さを含む前記半導体チップの厚さと略等しい若しく
はより厚い段差を設けた段差付金属厚箔を準備する工程
と、該段差付金属厚箔を前記基板に接合する工程と、前
記段差付金属厚箔に前記半導体チップを半田付けする工
程と、前記段差付金属厚箔の金属線接合部に金属線をワ
イヤボンド装置を用いて超音波接合する工程と、該ワイ
ヤボンド装置による超音波接合後に、前記金属線接合部
に接合した金属線を切断すべく、前記ワイヤボンド装置
が半田付けされた前記半導体チップの頭上をシフトバッ
クする工程とからなる半導体装置の製造方法。4. A step of preparing a substrate made of an insulating plate or a non-insulating plate having an insulating layer formed on the surface thereof, and separately providing a soldering portion of a semiconductor chip and a metal wire bonding portion, wherein the metal wire bonding portion is A step of preparing a stepped metal thick foil having a step substantially equal to or thicker than the thickness of the semiconductor chip including the solder thickness of the soldered part of the semiconductor chip, and the stepped metal thick foil Bonding the semiconductor chip to the stepped metal thick foil, and ultrasonically bonding a metal wire to the metal wire bonding portion of the stepped metal thick foil using a wire bonding apparatus. And a step of shifting back the head of the semiconductor chip to which the wire bonding device is soldered in order to cut the metal wire bonded to the metal wire bonding portion after the ultrasonic bonding by the wire bonding device. What Semiconductor device manufacturing method.
JP9332888A 1997-12-03 1997-12-03 Semiconductor device and its manufacture Pending JPH11168118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9332888A JPH11168118A (en) 1997-12-03 1997-12-03 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9332888A JPH11168118A (en) 1997-12-03 1997-12-03 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH11168118A true JPH11168118A (en) 1999-06-22

Family

ID=18259931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9332888A Pending JPH11168118A (en) 1997-12-03 1997-12-03 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH11168118A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110828324A (en) * 2019-10-31 2020-02-21 格物感知（深圳）科技有限公司 Continuous aluminum wire bonding method for small welding point chip and small welding point chip connecting structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110828324A (en) * 2019-10-31 2020-02-21 格物感知（深圳）科技有限公司 Continuous aluminum wire bonding method for small welding point chip and small welding point chip connecting structure

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