JPH11163702A - Resetting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a stable power-on-reset to a semiconductor by providing a delay circuit and a shift register a reset input terminal of which is connected to the delay circuit and whose an output terminal is connected to the reset input terminal of a semiconductor circuit. SOLUTION: When a power source is charged, a capacitor 3 is discharged, a node 33 and a reset input terminal 5 of a shift register 1 are at a ground level, and the register 1 is reset. After the power source is charged, the capacitor is charged through resistance 31, and the potential of the node 33 rises. When the potential of the node 33 becomes the threshold of a buffer circuit 32 or more, the potential of the reset input terminal 5 of the register 1 changes from the ground level to a level of a power supply voltage, and the reset of the register is released. When a clock is inputted as many as the number of stages of the register 1 from a clock input 4, the input value of a leading register propagates, an output terminal 7 of the register 1 becomes a power supply level and the reset of a semiconductor circuit is released.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit for performing a power-on reset operation on a semiconductor circuit having a reset input.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional reset circuit for performing a reset operation on a semiconductor having a reset input.

In FIG. 3, 21 is a resistor, 22 is a semiconductor circuit having a reset input, 24 is a capacitor, 25 is a buffer circuit for waveform shaping, and 23 is a buffer circuit 25
, A reset input terminal of the semiconductor circuit 22, is configured to be reset when it is at the ground level. One terminal of the resistor 21 is connected to a power supply, and the other terminal is connected to a capacitor 24 and a buffer circuit 25.
, The other terminal of the capacitor 24 is connected to the ground level, and the output of the buffer circuit 25 is connected to the reset input terminal 28 of the semiconductor circuit 22 via the node.

FIG. 4 is a timing chart for explaining the operation of the conventional reset circuit.

When the power is turned on, the capacitor 23 is discharged, so that the node 23 and the reset input terminal 28 of the semiconductor circuit 22 are at the ground level.
Reference numeral 2 indicates a reset state.

After the power is turned on, the capacitor 24 is charged through the resistor 21, so that the potential of the node 23 gradually increases. When the potential of the node 23 (input potential of the buffer circuit 25) becomes equal to or higher than the threshold voltage of the buffer circuit 25, the potential of the reset input terminal 28 of the semiconductor circuit 22 changes from the ground level to the power supply voltage level. Is reset.

[0007]

In the above-mentioned conventional semiconductor circuit having a reset input, when a power-on reset is performed, a stable operation may not be obtained depending on the reset pulse width. In some cases, the reset must be released after inputting the clock a plurality of times, and a stable operation has not been guaranteed in the conventional semiconductor circuit.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a reset circuit capable of obtaining a stable power-on reset operation for a semiconductor circuit.

[0009]

In order to achieve the above object, a reset circuit of the present invention is a reset circuit for resetting a semiconductor circuit, wherein a delay circuit and a reset input terminal are connected to the delay circuit. The output terminal includes a shift register connected to a reset input terminal of the semiconductor circuit.

With this configuration, the reset is not released unless the external clock is input to the shift register a predetermined number of times or more, so that the semiconductor circuit can ensure a stable reset operation without malfunction.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a reset circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a shift register having a reset input, 2 is a semiconductor circuit having a reset input,
Is a capacitor, 31 is a resistor, 32 is a buffer circuit for waveform shaping, 33 is a node serving as an input to the buffer circuit 32, 4 is an external clock input, 5 is a reset input terminal of the shift register 1, and 6 is a shift register. Reference numeral 1 denotes a clock input terminal, 7 denotes an output terminal of the shift register 1, 8 denotes a reset input terminal of the semiconductor circuit 2, and 9 denotes a shift register 1.
Is the input terminal of the first register.

One terminal of the resistor 31 is connected to a power supply,
The other terminal is connected to capacitor 3 and buffer circuit 32 via node 33. The other terminal of the capacitor 3 is connected to the ground level, the output of the buffer circuit 32 is connected to the reset input terminal 5 of the shift register 1 via the node 33, and the output terminal 7 of the shift register 1 is connected to the reset input of the semiconductor circuit 2. Clock input 4 is connected to terminal 8 and clock input 4 is connected to clock input terminal 6. The shift register 1 and the semiconductor circuit 2 are configured to be reset at the ground level. Also, shift register 1
Output is at ground level at reset. The input terminal 9 of the first register of the shift register 1 is fixed to the power supply.

The reset circuit having the above configuration will be described with reference to the drawings. FIG. 2 is a timing chart showing the operation of the reset circuit.

Since the capacitor 3 is discharged when the power is turned on, the node 33 and the reset input terminal 5 of the shift register 1 are at the ground level, and the shift register 1 is in a reset state. Therefore, the ground level is output from the output terminal 7 of the shift register 1, and the semiconductor circuit 2 is in a reset state.

After the power is turned on, the capacitor 3 is charged through the resistor 31, so that the potential of the node 33 gradually increases. When the potential of the node 33 (input potential of the buffer circuit 32) becomes equal to or higher than the threshold value of the buffer circuit 32, the potential of the reset input terminal 5 of the shift register 1 changes from the ground level to the power supply voltage level. The reset that was applied is released.

At this time, the output terminal 7 of the shift register 1
Remains at the ground level, and the semiconductor circuit 2 remains reset. After the reset is released, when clocks are input by the number of stages of the shift register 1 from the clock input 4, the input value of the first register propagates, the output terminal 7 of the shift register 1 becomes the power supply level, and the semiconductor circuit 2
Is reset. The number of stages of the shift register 1 can be set arbitrarily, and the time from power-on to reset release of the semiconductor circuit 2 can be set to a numerical value required by the semiconductor circuit 2.

Although a shift register is used in this embodiment, a similar effect can be obtained by using a counter.

[0020]

As described above, according to the present invention, a reset circuit capable of obtaining a stable power-on reset operation for a semiconductor can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a reset circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of a reset circuit according to one embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a conventional reset circuit.

FIG. 4 is a timing chart showing the operation of a conventional reset circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 shift register 2 semiconductor circuit 3 capacitor 4 external clock input 5 shift register reset input terminal 6 shift register clock input terminal 7 shift register output terminal 8 semiconductor circuit reset input terminal 31 resistor 32 buffer circuit

Claims (1)

[Claims] 1. A reset circuit for resetting a semiconductor circuit, comprising: a delay circuit; and a shift register having a reset input terminal connected to the delay circuit and an output terminal connected to a reset input terminal of the semiconductor circuit. Reset circuit.