CN113556111A - Power-on reset circuit and power-on reset method based on FPGA - Google Patents

Power-on reset circuit and power-on reset method based on FPGA Download PDF

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Publication number
CN113556111A
CN113556111A CN202111077920.XA CN202111077920A CN113556111A CN 113556111 A CN113556111 A CN 113556111A CN 202111077920 A CN202111077920 A CN 202111077920A CN 113556111 A CN113556111 A CN 113556111A
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reset
bit accumulator
carry
input
power
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吴佳
李礼
吴叶楠
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Zhejiang Weigu Information Technology Co ltd
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Zhejiang Weigu Information Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

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  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The application relates to a power-on reset circuit and a power-on reset method based on an FPGA (field programmable gate array), which comprise a DA (digital-to-analog) trigger circuit and a DR (digital-to-analog) trigger circuit which are sequentially connected, wherein the DA trigger circuit comprises a DA trigger group, an n-bit accumulator and a first carry fixing circuit, and the DA trigger circuit comprises the DA trigger group, the n-bit accumulator and the first carry fixing circuit. According to the power-on RESET method, signals are continuously provided to the n-bit accumulator through the input clock signal CLK and continuously added with 1 until carry occurs, the first carry fixing circuit keeps the carry signal of the n-bit accumulator, the DR trigger group cancels RESET, finally, the m-bit accumulator continuously adds 1 until carry occurs and generates a carry signal, when the RESET signal is generated, the RESET signal of the RESET output connecting end is changed from 0 to 1 and is fixed to 1, RESET is further achieved, namely, a power-on RESET circuit does not need to be added outside an FPGA chip, the RESET time is adjustable, the cost is low, and the flexibility is high.

Description

Power-on reset circuit and power-on reset method based on FPGA
Technical Field
The application relates to the technical field of FPGA reset circuits, in particular to a power-on reset circuit and a power-on reset method based on an FPGA.
Background
An FPGA is a digital integrated circuit that can implement arbitrary combinational and sequential logic from configuration data. When the FPGA is powered on, the implemented sequential logic, such as logic values stored by a flip-flop, a state machine, etc., are at random 1 or 0, that is, a random high level or low level state is output, and the sequential logic needs to be in a controllable initial state through reset to perform correct operation downward, that is, reset is needed.
Generally, a reset signal input by the FPGA comes from a button, as shown in fig. 5, after the FPGA is powered on, and after a stable power supply voltage is provided through VDD, the reset button is manually pressed, at this time, a low-level reset signal is generated to reset the FPGA, then the reset button is manually released, the reset signal returns to a high level, and the FPGA starts to operate. However, when the FPGA is used in an unattended application environment, the FPGA cannot be reset manually, and often needs to start to operate automatically after the FPGA is powered on, and therefore, a power-on reset circuit is needed to reset the FPGA.
In addition, conventionally, a capacitor charging effect is needed to be utilized for power-on RESET, as shown in fig. 6, before the power supply voltage of the FPGA is stabilized, a capacitor C outside the FPGA chip is slowly charged from a low level to generate a stable low level RESET signal, when the voltage of the capacitor rises to exceed the turning threshold of the RESET port inverter after the power supply voltage is stabilized, the RESET port judges that the RESET signal recovers to a high level, and the FPGA starts to operate.
Obviously, the FPGA needs a power-on reset circuit provided outside the chip to complete power-on reset, which is high in cost and poor in flexibility.
Disclosure of Invention
Therefore, it is necessary to provide a power-on reset circuit and a power-on reset method based on an FPGA without adding a power-on reset circuit outside an FPGA chip in order to solve the above technical problems.
A power-on reset circuit based on an FPGA comprises a DA trigger circuit and a DR trigger circuit which are sequentially connected, wherein the DA trigger circuit comprises a DA trigger group, an n-bit accumulator and a first carry fixing circuit; wherein the content of the first and second substances,
the clock input end of the DA trigger group is connected with an input clock signal CLK, the input end of the n-bit accumulator is connected with the output end of the DA trigger group, the first input end of the first carry fixing circuit is connected with the first output end of the n-bit accumulator, the second input end of the first carry fixing circuit is connected with the second output end of the n-bit accumulator, and the output end of the first carry fixing circuit is connected with the trigger input end of the DA trigger group;
the DR trigger circuit comprises a DR trigger group, an m-bit accumulator and a second carry fixing circuit; wherein the content of the first and second substances,
the first input end of the DR trigger group is connected with the third output end of the n-bit accumulator, the clock input end of the DR trigger group is connected with the input clock signal CLK, the input end of the m-bit accumulator is connected with the output end of the DR trigger group, the first input end of the second carry fixing circuit is connected with the first output end of the m-bit accumulator, the second input end of the second carry fixing circuit is connected with the third output end of the m-bit accumulator, the output end of the second carry fixing circuit is connected with the second input end of the DR trigger group, and the second input end of the second carry fixing circuit and the third output end of the m-bit accumulator are both connected with the reset output connection end RESTE.
Preferably, the DA flip-flop group includes n DA flip-flops, clock input ends of the n DA flip-flops are all connected to the input clock signal CLK, trigger input ends of the n DA flip-flops are all connected to an output end of the first carry fixing circuit, and output ends of the n DA flip-flops are respectively connected to n-bit input ends IN0 to IN (n-1) of the n-bit accumulator IN sequence.
Preferably, the DR trigger group includes m DR triggers, the clock input ends of the m DR triggers are all connected to the input clock signal CLK, the first input ends of the m DR triggers are connected to the third output end of the n-bit accumulator, the second input ends of the m DR triggers are respectively and sequentially connected to the m-bit output ends OUT0 to OUT (m-1) of the second carry fixing circuit, and the output ends of the m DR triggers are respectively and sequentially connected to the m-bit input ends IN0 to IN (m-1) of the m-bit accumulator.
Preferably, the number of the DA flip-flops is 3-1024.
The FPGA-based power-on-reset circuit of claim 3, wherein the number of DR flip-flops is 3-1024.
Preferably, a power-on reset method according to the FPGA-based power-on reset circuit includes the following steps:
the method comprises the following steps: after power-on, the input clock signal CLK provides a clock signal to the DA flip-flop group, and a third output end of the n-bit accumulator is 1;
step two: the DR trigger set is set to be zero, the third output end of the m-bit accumulator is 0, and the reset output connection end RESTE is 0;
step three: when the input clock signal CLK continues to provide signals to the n-bit accumulator to continue to add 1 until a carry occurs;
step four: the first carry fixing circuit keeps a carry signal of the n-bit accumulator, and the DR trigger group cancels resetting;
step five: and the m-bit accumulator continuously adds 1 until carry occurs and generates a carry signal, and when a RESET signal is generated, the RESET output connection end RESET signal is changed from 0 to 1 and is fixed to 1.
Preferably, the step one: after power-on, the input clock signal CLK provides a clock signal to the DA flip-flop group, and a third output terminal of the n-bit accumulator is 1, which specifically includes the following steps:
step (1): after power-on, the input clock signal CLK provides a clock signal to the n DA flip-flops;
step (2): after the n DA triggers are electrified, the data stored by the n DA triggers are random 0 or 1, and the third output end of the n-bit accumulator is 1.
Preferably, step three: when the input clock signal CLK continuously provides a signal to the n-bit accumulator to continuously add 1 until a carry occurs, the method specifically includes:
the n-bit accumulator continues to add 1 to generate a carry when the time does not exceed T x (2n-1) while the input clock signal CLK continues to provide a signal;
wherein T provides the clock period of the clock signal for the input clock signal CLK.
Preferably, step five: the m-bit accumulator continuously adds 1 until carry occurs, generates a carry signal, and when a RESET signal is generated, the RESET output connection terminal RESET signal is changed from 0 to 1 and fixed as 1, specifically comprising:
and the m-bit accumulator continuously adds 1, carries after time T (2m-1) and generates a carry signal, and when a RESET signal is generated, the RESET output connection end RESET signal is changed from 0 to 1 and is fixed to 1.
Preferably, the total time range of the power-on reset is: t × (2m-1) < Tr < T × (2m +2 n-2); wherein, Tr is the total time of power-on reset.
The power-on reset circuit and the power-on reset method based on the FPGA have the technical effects that:
the invention sets a DA trigger circuit and a DR trigger circuit which are connected in sequence, and enables the DA trigger circuit to comprise a DA trigger group, an n-bit accumulator and a first carry fixing circuit, the DA trigger circuit comprises the DA trigger group, the n-bit accumulator and the first carry fixing circuit, after being electrified, the input clock signal CLK provides a clock signal to the DA trigger group, the third output end of the n-bit accumulator is 1, then the third output end of the m-bit accumulator is 0, the reset output connecting end RESTE is 0, and the first carry fixing circuit keeps the carry signal of the n-bit accumulator, the DR trigger group cancels the reset, and finally the m-bit accumulator continuously adds 1 until the carry occurs and generates the carry signal, when a RESET signal is generated, the RESET signal at the RESET output connecting end is changed from 0 to 1 and is fixed to 1, so that RESET is realized, namely, a power-on RESET circuit is not required to be added outside an FPGA chip, and the RESET signal can be integrated and burned into the FPGA by a person skilled in the art by writing an RTL code, so that power-on RESET of the FPGA is completed, and the RESET time is adjustable, the cost is low, and the flexibility is high.
Drawings
FIG. 1 is a block diagram of a circuit structure of a power-on reset circuit and a power-on reset method based on an FPGA;
FIG. 2 is a block diagram of another circuit configuration of a power-on reset circuit and a power-on reset method based on an FPGA;
FIG. 3 is a block diagram of a DA flip-flop;
FIG. 4 is a block diagram of a DR flip-flop;
FIG. 5 is a circuit schematic of a prior art button-based FPGA power-on-reset circuit;
fig. 6 is a circuit schematic diagram of a capacitance-based FPGA power-on-reset circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, a power-on reset circuit based on an FPGA is provided, which includes a DA flip-flop circuit and a DR flip-flop circuit connected in sequence, where the DA flip-flop circuit includes a DA flip-flop group, an n-bit accumulator, and a first carry fixing circuit.
The clock input end of the DA trigger group is connected with an input clock signal CLK, the input end IN [ n-1: O ] of the n-bit accumulator is connected with the output end of the DA trigger group, the first input end IN [ n-1:0] of the first carry fixing circuit is connected with the first output end S [ n-1:0] of the n-bit accumulator, the second input end P of the first carry fixing circuit is connected with the second output end C of the n-bit accumulator, and the output end OUT [ n-1:0] of the first carry fixing circuit is connected with the trigger input end D of the DA trigger group;
the DR trigger circuit comprises a DR trigger group, an m-bit accumulator and a second carry fixing circuit; wherein the content of the first and second substances,
the first input of the DR flip-flop group is connected to the third output CN of the n-bit accumulator, the clock input terminal of the DR flip-flop group is connected to the input clock signal CLK, the input terminal IN [ m-1:0] of the m-bit accumulator is connected to the output terminal of the DR flip-flop group, the first input end IN [ m-1:0] of the second carry fixing circuit is connected with the first output end S [ m-1:0] of the m-bit accumulator, the second input end P of the second carry fixing circuit is connected with the third output end C of the m-bit accumulator, the output end OUT [ m-1:0] of the second carry fixing circuit is connected with the second input end of the DR trigger group, and the second input end P of the second carry fixing circuit and the third output end C of the m-bit accumulator are also connected with a reset output connecting end RESTE.
In an embodiment, as shown in fig. 2, the DA flip-flop group includes n DA flip-flops, where in this embodiment, the n DA flip-flops in fig. 2 are combined to form the DA flip-flop group denoted in fig. 1.
Specifically, the clock input terminals CLK of the n DA flip-flops are all connected to the input clock signal CLK, the trigger input terminals D of the n DA flip-flops are all connected to the output terminal OUT [ n-1:0] of the first carry fixing circuit, and the output terminals Q of the n DA flip-flops are respectively connected to the n-bit input terminals IN0 to IN (n-1) of the n-bit accumulator IN sequence, that is, the input terminals IN [ n-1: 0].
In an embodiment, as shown in fig. 2, the DR flip-flop group includes m DR flip-flops, wherein in this embodiment, the m DR flip-flops in fig. 2 are combined to form the DR flip-flop group denoted in fig. 1.
Specifically, the clock input terminals CLK of m DR flip-flops are all connected to the input clock signal CLK, the first input terminals R of the m DR flip-flops are connected to the third output terminal CN of the n-bit accumulator, the second input terminals D of the m DR flip-flops are respectively connected to the m-bit output terminals OUT0 to OUT (m-1) of the second carry fixing circuit IN sequence, and the output terminals Q of the m DR flip-flops are respectively connected to the m-bit input terminals IN0 to IN (m-1) of the m-bit accumulator IN sequence.
In one embodiment, the DA flip-flop is a D flip-flop without a reset terminal as shown in fig. 3, and the typical structure is as shown in fig. 3, since it has no reset terminal, the stored logic value and the output Q are random values when it is powered up, and the stored logic value and the output Q follow the input D on the rising edge of CLK after power up.
In one embodiment, as shown in fig. 4, the DR flip-flop is a D flip-flop with a reset terminal, and the typical structure is shown in fig. 4. When R is 1, the stored logic value and the output Q are kept to be 0, when R is 0, the stored logic value and the output Q are random values when the power is on, and the stored logic value and the output Q follow the input D on the rising edge of CLK after the power is on.
Further, as shown in fig. 1-2, the accumulator is a combinational logic circuit that performs an add-1 operation on the input data. For an n-bit accumulator, the input data IN [ n-1:0] is n bits wide, namely IN0 through IN (n-1). After adding 1 to the input data IN, the output result is S [ n-1:0], and the bit width is n bits, namely S0 to S (n-1). The output terminals C and CN are carry signals. When the input signal IN [ n-1:0] = n 'b 1 is accumulated, a carry occurs, and then the output S [ n-1:0] = n' b0, C =1 'b 1, CN = 1' b 0; when the input signal IN [ n-1:0] = a ≠ n ' b1 is accumulated, no carry occurs at this time, and S [ n-1:0] = a +1, C =1 ' b0, CN =1 ' b1 are output.
The carry fixing circuit is a circuit for performing bit-wise or operation on each bit of the input IN and the input P. For an n-bit accumulator, when the n-bit accumulator input IN [ n-1:0] ≠ n 'b 1, then C = 1' b0, carry-OUT of fixed circuit [ n-1:0] = IN [ n-1:0 ]; when n is the accumulator input IN [ n-1:0] = n ' b1, then C =1 ' b1, OUT [ n-1:0] = n ' b1 of the carry fixing circuit. Thereafter the inputs IN n-1:0 of the accumulator are kept at n' b1 each clock cycle, the output C of the accumulator is kept at 1 and CN is kept at 0.
In one embodiment, the number of DA flip-flops is 3-1024. That is, n has a value of 3 to 1024.
In one embodiment, the number of DR flip-flops is 3-1024. I.e. m has a value of 3-1024.
In one embodiment, the present invention further provides a power-on reset method according to the FPGA-based power-on reset circuit, including the steps of:
the method comprises the following steps: after power-on, the input clock signal CLK provides a clock signal to the DA flip-flop group, and a third output end of the n-bit accumulator is 1;
specifically, the input clock signal CLK continues to provide a clock signal with a clock period set to T.
Further, when power is on, the data stored by each DA flip-flop in the DA flip-flop group is random 0 or 1, and the probability that all n DA flip-flops store 1 is almost 0, then the result of adding 1 is not carried, and the output CN of the n-bit accumulator is 1 at this time.
Step two: the DR trigger set is set to zero, a third output end C of the m-bit accumulator is 0, and a reset output connection end RESTE is 0;
furthermore, m of the DR triggers are set to 0, and if the input of the m-bit accumulator is all 0, the result of adding 1 will not carry, and the signal of the reset output connection terminal rest is 0.
Step three: when the input clock signal CLK continues to provide signals to the n-bit accumulator to continue to add 1 until a carry occurs;
since the CLK continues to provide the clock signal, the n-bit accumulator continues to add 1 until a carry occurs, the carry not taking place for more than T (2)n-1)。
Step four: the first carry fixing circuit keeps a carry signal of the n-bit accumulator, and the DR trigger group cancels resetting;
when the n-bit accumulator carries out carry, the carry fixing circuit can keep the carry signal of the n-bit accumulator, and the m DR triggers cancel resetting.
Step five: and the m-bit accumulator continuously adds 1 until carry occurs and generates a carry signal, and when a RESET signal is generated, the RESET output connection end RESET signal is changed from 0 to 1 and is fixed to 1.
The RESET signal is changed from 0 to 1 when a carry signal is generated by the m-bit accumulator continuously adding 1 until a carry occurs, and is fixed to 1 thereafter.
In one embodiment, step one: after power-on, the input clock signal CLK provides a clock signal to the DA flip-flop group, and a third output terminal of the n-bit accumulator is 1, which specifically includes the following steps:
step (1): after power-on, the input clock signal CLK provides a clock signal to the n DA flip-flops;
step (2): after the n DA triggers are electrified, the data stored by the n DA triggers are random 0 or 1, and the third output end of the n-bit accumulator is 1.
In one embodiment, step three: when the input clock signal CLK continuously provides a signal to the n-bit accumulator to continuously add 1 until a carry occurs, the method specifically includes:
when the input clock signal CLK continues to provide a signal, does not exceed T (2) at a timen-1) the n-bit accumulator is continuously added by 1 to generate a carry;
wherein T provides the clock period of the clock signal for the input clock signal CLK.
In one embodiment, step five: the m-bit accumulator continuously adds 1 until carry occurs, generates a carry signal, and when a RESET signal is generated, the RESET output connection terminal RESET signal is changed from 0 to 1 and fixed as 1, specifically comprising:
the m bit accumulator continues to add 1 for a time T × (2)m-1) generating a carry after the RESET signal, and generating a carry signal, wherein when generating the RESET signal, the RESET input connection RESET signal changes from 0 to 1 and is fixed to 1.
In one embodiment, the total time range for the power-on reset is: t × (2)m-1)＜Tr＜T×(2m+2 n-2); wherein, Tr is the total time of power-on reset.
Further, the time from the cancellation of reset to the occurrence of carry of the m DR flip-flops is T × (2)m-1), so that the total time Tr of the power-on reset satisfies T × (2)m-1)＜Tr＜T×(2m+2n-2)。
In one embodiment, by changing the logic value stored and output when the partial DR flip-flop is reset to 1, the time for the m-bit accumulator to generate the carry signal, i.e., the length of the reset time, can be changed more finely.
Also, by configuring m and n with different numbers of bits, the reset time length can be changed.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A power-on reset circuit based on FPGA comprises a DA trigger circuit and a DR trigger circuit which are connected in sequence, and is characterized in that the DA trigger circuit comprises a DA trigger group, an n-bit accumulator and a first carry fixing circuit; wherein the content of the first and second substances,
the clock input end of the DA trigger group is connected with an input clock signal CLK, the input end of the n-bit accumulator is connected with the output end of the DA trigger group, the first input end of the first carry fixing circuit is connected with the first output end of the n-bit accumulator, the second input end of the first carry fixing circuit is connected with the second output end of the n-bit accumulator, and the output end of the first carry fixing circuit is connected with the trigger input end of the DA trigger group;
the DR trigger circuit comprises a DR trigger group, an m-bit accumulator and a second carry fixing circuit; wherein the content of the first and second substances,
the first input end of the DR trigger group is connected with the third output end of the n-bit accumulator, the clock input end of the DR trigger group is connected with the input clock signal CLK, the input end of the m-bit accumulator is connected with the output end of the DR trigger group, the first input end of the second carry fixing circuit is connected with the first output end of the m-bit accumulator, the second input end of the second carry fixing circuit is connected with the third output end of the m-bit accumulator, the output end of the second carry fixing circuit is connected with the second input end of the DR trigger group, and the second input end of the second carry fixing circuit and the third output end of the m-bit accumulator are both connected with the reset output connection end RESTE.
2. The FPGA-based power-on reset circuit according to claim 1, wherein the DA flip-flop group comprises n DA flip-flops, the clock input ends of the n DA flip-flops are all connected with the input clock signal CLK, the trigger input ends of the n DA flip-flops are all connected with the output end of the first carry fixing circuit, and the output ends of the n DA flip-flops are respectively and sequentially connected with n-bit input ends IN0 to IN (n-1) of an n-bit accumulator.
3. The FPGA-based power-on reset circuit of claim 1, wherein the group of DR flip-flops comprises m DR flip-flops, the clock input terminals of the m DR flip-flops are all connected to the input clock signal CLK, the first input terminals of the m DR flip-flops are connected to the third output terminal of the n-bit accumulator, the second input terminals of the m DR flip-flops are sequentially connected to m-bit output terminals OUT0 to OUT (m-1) of the second carry fixing circuit, respectively, and the output terminals of the m DR flip-flops are sequentially connected to m-bit input terminals IN0 to IN (m-1) of the m-bit accumulator, respectively.
4. The FPGA-based power-on-reset circuit of claim 2, wherein the number of DA flip-flops is 3-1024.
5. The FPGA-based power-on-reset circuit of claim 3, wherein the number of DR flip-flops is 3-1024.
6. A power-on reset method of the FPGA-based power-on reset circuit according to any one of claims 3 to 5, characterized in that the method comprises the following steps:
the method comprises the following steps: after power-on, the input clock signal CLK provides a clock signal to the DA flip-flop group, and a third output end of the n-bit accumulator is 1;
step two: the DR trigger set is set to be zero, the third output end of the m-bit accumulator is 0, and the reset output connection end RESTE is 0;
step three: when the input clock signal CLK continues to provide signals to the n-bit accumulator to continue to add 1 until a carry occurs;
step four: the first carry fixing circuit keeps a carry signal of the n-bit accumulator, and the DR trigger group cancels resetting;
step five: and the m-bit accumulator continuously adds 1 until carry occurs and generates a carry signal, and when a RESET signal is generated, the RESET output connection end RESET signal is changed from 0 to 1 and is fixed to 1.
7. The power-on reset method according to claim 6, wherein the first step: after power-on, the input clock signal CLK provides a clock signal to the DA flip-flop group, and a third output terminal of the n-bit accumulator is 1, which specifically includes the following steps:
step (1): after power-on, the input clock signal CLK provides a clock signal to the n DA flip-flops;
step (2): after the n DA triggers are electrified, the data stored by the n DA triggers are random 0 or 1, and the third output end of the n-bit accumulator is 1.
8. The power-on reset method according to claim 6, wherein step three: when the input clock signal CLK continuously provides a signal to the n-bit accumulator to continuously add 1 until a carry occurs, the method specifically includes:
when the input clock signal CLK continues to provide a signal, does not exceed T (2) at a timen-1) the n-bit accumulator is continuously added by 1 to generate a carry;
wherein T provides the clock period of the clock signal for the input clock signal CLK.
9. The power-on reset method according to claim 8, wherein step five: the m-bit accumulator continuously adds 1 until carry occurs, generates a carry signal, and when a RESET signal is generated, the RESET output connection terminal RESET signal is changed from 0 to 1 and fixed as 1, specifically comprising:
the m bit accumulationThe device continues to add 1 for a time T (2)m-1) generating carry after the RESET, and generating a carry signal, wherein when generating a RESET signal, the RESET output connection terminal RESET signal changes from 0 to 1 and is fixed to 1.
10. A power-on reset method according to claim 9, wherein the total time range of the power-on reset is: t × (2)m-1)＜Tr＜T×(2m+2n-2); wherein, Tr is the total time of power-on reset.
CN202111077920.XA 2021-09-15 2021-09-15 Power-on reset circuit and power-on reset method based on FPGA Pending CN113556111A (en)

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CN202111077920.XA CN113556111A (en) 2021-09-15 2021-09-15 Power-on reset circuit and power-on reset method based on FPGA

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CN202111077920.XA CN113556111A (en) 2021-09-15 2021-09-15 Power-on reset circuit and power-on reset method based on FPGA

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