KR940001104B1 - Method and circuit for power reset and manual reset - Google Patents

Abstract

The power reset and manual reset identification circuit in a reset circuit having a resistor, a capacitor, a diode, a resistor, a manual reset switch, a first Schmitt trigger circuit and a second Schmitt circuit is operated by checking whether a received reset signal is of a power reset signal or not, initializing the overall system when the received signal is not the power reset signal, and initializing only peripheral chips when being not the power reset signal or completing the system initializing step to return to a main routine. Thus, data being stored on the RAM is preserved if for a manual reset, and the initialization with respect to the peripheral chips is selectively performed to a required portion only.

Description

Circuit and method of power reset and manual reset

1 is a conventional reset circuit diagram.

2 is an operation waveform diagram of a conventional circuit.

3 is a conventional system diagram.

4 is a reset circuit diagram according to the present invention.

5 is an operational waveform diagram according to the present invention.

6 is a flow chart in accordance with the present invention.

7 is a system diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

0,10-1: Reset circuit 20: CPU

30: Roman 40: Ram

50: peripheral chip

The present invention relates to a circuit and a method in a system using a central processing unit (CPU) such as a computer, and more particularly, to a reset circuit and a method capable of separating a power reset and a manual reset.

In general, the reset signal to the reset terminal (RESET) of the CPU must be given at power on. If necessary, give the same signal to the peripheral devices.

A complete reset requires the next constant block cycle time given that the supply voltage is stable and the clock is stable.

When the reset signal is released ("H"), the CPU starts by first fetching the command at address 0000H. If the reset signal is given manually during the operation of the CPU, it is initialized again as described above. However, other registers and memory contents remain unchanged.

FIG. 1 shows a manual reset circuit which also serves as a power reset, and also shows a reset valid period upon power-on.

The reason why the Schmitt trigger circuit U1 is used is that a slight vibration or noise may be included in a curve in which the potential V _B of the point A rises. At the same time to suppress the noise. The connection of the diode D1 in parallel with the resistor R1 differs in the time constant of the capacitor C1 at the time of power supply (charge) and at the time of power supply OFF (discharge), that is, the power ON. This is to reduce the charging speed at the time of charging and to increase the discharge speed at the time of OFF, so that accurate reset is performed even at frequent on-off.

When power is applied from the first even the potential of the point A is C T = KR _{1 1} enters the time point t ₁ and gradually rises as in the second degree with the 2-2 (K is a constant) to the normal state after the last time constant Done. In this case, the Schmitt trigger circuit U1 has an upper trigger level (UTL) and a lower trigger level (LTL). If UTL is set to V _1H and LTL is set to V _1L as in 2-2 of FIG. 2, the Schmitt trigger circuit U1 generates a power reset signal from the beginning to t1, and resets manually. The hour generates and outputs a manual reset signal during the t4 section at time t2.

When the reset circuit is actually applied, the configuration shown in FIG. 3 is realized. If the reset signal (power reset or manual reset) is generated, the CPU 20, the ROM 30, and the variable data are inputted and outputted. The RAM 40 and peripheral chips that exchange data with the external environment are cleared and initialized. However, if the manual reset signal is applied due to a mistake or a cause during operation, the result of the work up to that time is the RAM 40 and the peripheral chip 50 are initialized all at once, causing the contents to be lost. This is because the CPU 20 cannot distinguish whether it is a power reset signal or a manual reset signal when the reset signal is supplied.

In this respect, the above problems must be solved at the present time when computers are commercially available, and users are constantly demanding them.

Accordingly, an object of the present invention is to provide an apparatus that allows a CPU to distinguish between a power reset generated at initial power-up and a manual reset generated by a manual reset operation.

Another object of the present invention is to provide a method for the CPU to distinguish between a power reset generated at initial power-on and a manual reset generated by a manual reset operation.

Another object of the present invention is to initialize all of the memory and the peripheral chip at the time of power reset, and only the peripheral chip at the time of manual reset.

In order to achieve the above object, the reset signal is a 2-bit signal and the power reset state and the signal state of each other in manual reset are different so that when the CPU accesses the 2-bit reset signal, the power reset or Be aware of the manual reset status.

4 is a circuit diagram according to the present invention, in which a resistor R1 and a capacitor C1 are connected in series between a ground and a power supply, a diode D1 connected in parallel with the resistor R1, and connected in series with each other. A first Schmitt trigger circuit having an input terminal connected to a resistor R2 and a manual reset switch S1 connected in parallel with the capacitor C1 and an interconnection point of the resistor R1 and the capacitor C1 connected in series with each other; And a second Schmitt trigger circuit U2 having an input terminal connected to the interconnection point of the series-connected resistor R2 and the manual reset switch S1.

6 is a flow chart according to the present invention, in which a first step of checking whether a reset signal input at a predetermined reset is a power reset signal and a second step of initializing all systems when a power reset signal is applied as a result of the check in the first step are shown in FIG. And a third step of initializing only the peripheral chip and returning to the main routine when the check result is not the power reset signal in the first step or when the second step is completed.

The reset circuit according to the present invention of FIG. 4 is connected in the form of supplying a 2-bit signal to the CPU 20 as shown in FIG.

The flowchart according to the invention of FIG. 6 is stored as a system program in the ROM 30 of FIG.

5 shows waveforms of respective parts that appear when the present invention is performed.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

The reset circuit of the present invention further comprises a resistor R2 and a Schmitt trigger circuit U2 as compared with the conventional circuit.

The resistor R2 is inserted between the manual reset switch S1 of the diode D1 as shown in FIG. 1, which is a conventional circuit, and the second Schmitt trigger circuit U2 is connected to the added resistor R2. An input terminal was added to the connection point between the manual reset switches S1.

There are two reset signals generated in the present invention, a power reset signal and a manual reset signal, which are two-bit digital signals. The power reset signal and the manual reset signal are output from the first and second Schmitt trigger circuits U1 and U2 in FIG. 4, and in FIG. 7, the CPU 20 generates the first and second Schmitt trigger circuits U1 and U2. Access the output of) to detect the reset status. If any reset signal is generated, the CPU 20 first checks the output state of the second Schmitt trigger circuit U2. Then, the output state of the first Schmitt trigger circuit U1 is checked.

When " low " is active, if the output of the second Schmitt trigger circuit U2 is " low ", the CPU does not know which reset signal but recognizes that a reset signal has occurred, and then the first Schmitt trigger circuit. Check the output level of (U1). At this time, if the output of the first Schmitt trigger circuit (U1) is also active, the CPU 20 recognizes as a power reset, and if only the output of the first Schmitt trigger circuit (U1) is not active, the CPU Recognize it as a manual reset.

If the user presses the manual reset switch S1 at the time t2 of FIG. 5, the potential of the point C is directly grounded as shown in FIG. 5-4 of FIG. 5, but the potential of the point A is connected to the capacitor C1. Since the charged charge cannot be rapidly discharged due to the resistor R2, the charged charge gradually decreases as shown in 5-2 of FIG.

Therefore, as shown in 5-5 and 5-3 of FIG. 5, the outputs of the second and first Schmitt trigger circuits U2 and U1 have different states.

After a while, when the user releases the manual reset switch S1 at the t4 position of FIG. 5, the discharged capacitor C1 gradually starts charging again with the resistor R1 as a path, and the The electric potential starts to increase gradually as in 5-2 of FIG. 5 and finally reaches a steady state again.

At this time, when the manual reset switch S1 is pressed, the resistor R1 and the resistor R2 must satisfy the relationship of R1 >> R2 in order for the transition of the point A to approach the ground potential. That is, at the time of manual reset, the output of the first schmitt trigger circuit U1 and the output of the second schmitt trigger circuit U2 fall from " 1 " to " 0 " The output of U2) is faster by the period t3-t2 than the output of the first Schmitt trigger circuit U1, and this time is determined by the time constant by the resistor R2 and the capacitor C1.

When the reset signal is generated as described above, the CPU 20 reads the reset signal in the same manner as in FIG.

First, when the CPU 20 receives the "low" active signal from the second Schmitt trigger circuit U2, the CPU 20 performs the flow of FIG. First, in step 6a, it is checked whether the output logic of the first Schmitt trigger circuit U1 is "low" in an active state. At this time, if the output of the first Schmitt trigger circuit (U1) is not active in the "high" state, the CPU 20 is determined to be a manual reset state and separated to step 6C to initialize only peripheral chips and return to the main routine. do.

However, if the output state of the first schmitt trigger circuit U1 is "low" in step 6a, the CPU 20 determines that the power is reset by power and branches to step 6b to divide the peripheral chip and the memory. Include Initialize everything that needs to be initialized. However, in the flow of FIG. 6, when the output of the second Schmitt trigger circuit U2 becomes active and is called, the time taken to confirm the output of the first Schmitt trigger circuit U1 is shown in FIG. It should be shorter than the t3-t2 section. And for this purpose, the present invention should be placed in front of other programs.

As described above, the present invention can distinguish between a power reset and a manual reset, so in the case of a simple manual reset, the system can preserve data on the RAM worked up to that point without losing data, and also initialize the peripheral chips. There is an advantage that you can optionally do only what you need.

Claims (2)

A reset circuit comprising: a resistor (R1) and a capacitor (C1) connected in series between a ground and a supply power source, a diode (D1) connected in parallel with the resistor, and in series with each other and in series with the capacitor (C1). The first Schmitt trigger circuit U1 having an input terminal connected to an interconnection point of the parallel connected resistor R2 and the manual reset switch S1, the series connected resistor R1 and the capacitor C1, and the series connection And a second Schmitt trigger circuit (U2) having an input terminal connected to the interconnection point of the resistor (R2) and the manual reset switch (S1). A reset method comprising: a first step of checking whether a reset signal input at a predetermined reset is a power reset signal; a second step of initializing all systems when the check result is not a power reset signal in the first step; And a third step of initializing only the peripheral chip and returning to the main routine when the check result is not the power reset signal or the completion of the second step.