JPH11163688A - Superconducting pulse signal generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a superconducting pulse signal generation circuit capable of generating a single pulse signal and pulse signals at every prescribed cycle. SOLUTION: This pulse signal generation circuit outputs the pulse signal only once synchronized with the input of an AC bias current which is an AC current. In this case, a first SQUID (superconducting quantum interference device) 1 is provided and the AC bias current is supplied to it. Further, a control wire arranged so as to be magnetically coupled to the first SQUID 1 and supplied with a DC current and a second SQUID 2 inserted in the control wire for interrupting a DC current flowing to the control wire corresponding to the output signals of the first SQUID 1 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pulse signal generating circuit for generating a pulse signal, and more particularly to a superconducting pulse signal generating circuit for generating a pulse signal used in a superconducting integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, as a superconducting pulse signal generating circuit that generates a pulse signal in synchronization with an AC bias power supply,
A circuit having one Josephson junction element and a resistor as shown in FIG. 8 is known.

FIG. 8 is an equivalent circuit diagram showing a configuration of a conventional superconducting pulse signal generating circuit.

In FIG. 8, a conventional superconducting pulse signal generating circuit includes a bias feed resistor Rb21, a Josephson junction element J21 having one end connected to the bias feed resistance Rb21 and the other end grounded, and a Josephson junction J
21 and a load resistor RL21 connected in parallel.

[0005] In such a configuration, a bias current (hereinafter, referred to as an AC bias current), which is an AC current, is supplied to the Josephson junction element J21 via a bias feed resistor Rb21. The AC bias current flowing through the Josephson junction element J21 is set so that the peak value is equal to or higher than the superconducting critical current value.

When a current exceeding the superconducting critical current value flows, the Josephson junction element J21 switches from the superconducting state to the voltage state and cuts off the current. Therefore, at this time, the current flowing through the Josephson junction element J21 flows through the load resistance RL21, which is the output terminal, and the load resistance RL
A pulse signal is output to both ends of the inverter 21 in synchronization with each cycle of the AC bias current.

[0007]

However, in the conventional superconducting pulse signal generating circuit as described above, a pulse signal is generated for each cycle of the AC bias current, so that the pulse signal is synchronized with the input of the AC bias current. Could not be generated only once.

Such a superconducting pulse signal generating circuit for generating a single pulse signal can be implemented, for example, by various circuits as a circuit for initializing a circuit when a power supply of a device is turned on or for generating a pulse signal to be applied to a specific logic circuit. Can be used for applications.

[0009] Even when the pulse signal is generated periodically, it is desirable that the pulse signal can be generated not only at each cycle of the AC bias current but also at a predetermined cycle set in advance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and is directed to a superconducting device capable of generating a single pulse signal and a pulse signal at predetermined intervals. It is an object to provide a pulse signal generation circuit.

[0011]

In order to achieve the above object, a superconducting pulse signal generating circuit according to the present invention comprises a superconducting pulse signal for outputting a pulse signal only once in synchronization with the input of an alternating current bias current. A generator circuit, wherein the first SQUID to which the AC bias current is supplied is arranged to be magnetically coupled to the first SQUID;
A control wiring to which a DC current is supplied, and a DC current inserted into the control wiring and flowing through the control wiring,
Second SQUID to be interrupted in response to output signal of QUID
And

At this time, the first SQUID may have a positive-negative symmetric threshold characteristic with respect to the AC bias current. In this case, the first SQUID is
Two inductances connected in series, a damping resistor connected in parallel with the two inductances,
And two Josephson junction elements connected to both ends of the damping resistor and grounded at one end, and the AC bias current may be supplied to a connection point between the two inductances.

Further, the first SQUID may have a positive-negative asymmetric threshold characteristic with respect to the AC bias current. In this case, the first SQUID may include an inductance and a parallel connection with the inductance. And two Josephson junction elements respectively connected to both ends of the damping resistor and having one end grounded, wherein the AC bias current is supplied to one end of the inductance. Good.

Further, there is provided any one of the superconducting pulse signal generating circuits described above, and a plurality of latch circuits using the AC bias current as an operation clock, wherein each of the plurality of latch circuits has an output of a preceding latch circuit. The output signal of the superconducting pulse signal generation circuit is connected in series by being connected to the input of the subsequent-stage latch circuit, is input to the first-stage latch circuit connected in series, and the output signal of the last-stage latch circuit is A configuration may be employed in which feedback is provided to the input of the first-stage latch circuit.

In the superconducting pulse signal generating circuit configured as described above, the superconducting critical current value of the first SQUID is reduced by supplying a direct current to the control wiring. When an AC bias current is supplied to the first SQUID in this state, the first SQUID transitions to a voltage state. At this time, the current flowing in the first SQUID flows to the output side of the superconducting pulse signal generation circuit, and the second SQUID transitions to a voltage state by the output signal, and cuts off the DC current flowing in the control wiring. I do. Therefore, even if the current increases in the next cycle of the AC bias current, the first SQUID does not decrease the superconducting critical current value, and thus maintains the superconducting state. Therefore, a pulse signal is output from the superconducting pulse signal generating circuit only once in synchronization with the input of the AC bias current.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is an equivalent circuit diagram showing a configuration of a first embodiment of a superconducting pulse signal generating circuit according to the present invention.

In FIG. 1, a superconducting pulse signal generating circuit according to the present embodiment includes an inductance L1 connected in series,
L2, a damping resistor Rd1 connected in parallel with the inductances L1 and L2, and a first SQUID (Supercondudu) comprising Josephson junction elements J1 and J2 connected to both ends of the damping resistor Rd1 and having one end grounded.
cting Quantum Interference Device) 1 and the first S
Control wires L3 and L4 magnetically coupled to inductances L1 and L2 of QUID1, inductances L5 and L6 connected in series, damping resistors Rd2 connected in parallel to inductances L5 and L6, and both ends of damping resistors Rd2. And one end is connected to the control line L4
A second SQUID2 composed of Josephson junction elements J3 and J4 connected to the control circuit L7 and a control wiring L7 magnetically coupled to the inductances L5 and L6 of the second SQUID2.
L8, bias feed resistors Rb1 and Rb2, and load resistors RL1 and RL2.

Note that one end of the bias feed resistor Rb1 is connected to a connection point of the inductances L1 and L2 connected in series, and an AC bias current AC is supplied from the other end. One end of the bias feed resistor Rb2 is
It is connected to the connection point of the inductances L5 and L6 connected in series, and a direct current DC is supplied from the other end.

In such a configuration, the control line L3,
L4 includes a bias feed resistor Rb2 and a second SQ
DC current DC is supplied via UID2. The value of the direct current DC is set to, for example, about 75% of the zero magnetic field critical current value of the second SQUID2. At this time, the second SQUID 2 is in a superconducting state. The zero magnetic field critical current value is a superconducting critical current value when no current is flowing through the control wiring of the SQUID, and this value is set to 100%.

In such a state, each circuit constant of the first SQUID 1 is set so that the superconducting critical current value of the first SQUID 1 becomes 50% or less of the zero magnetic field critical current value.

Here, when an AC bias current AC having a peak value of about 75% of the zero magnetic field critical current value is supplied to the first SQUID1 via the bias feed resistor Rb1, the current flows to the first SQUID1. Since the current exceeds its superconducting critical current value, the first SQUID 1 switches from the superconducting state to the voltage state in synchronization with the rise of the AC bias current AC. As a result, the AC bias current AC is injected into the load resistor RL2, which is the output terminal, via the control lines L7 and L8.

The control lines L7 and L8 are connected to the second SQUID2
, The superconducting critical current value of the second SQUID 2 is reduced to about 50% of the zero-field critical current value. Since a DC current of about 75% of the zero-field critical current value flows through the second SQUID2 via the bias feed resistor Rb2, the second SQUID2
UID2 switches to the voltage state and switches control lines L3 and L4.
The current that was flowing through is cut off. As a result, the DC current DC
Flows into the ground potential via the load resistor RL1. Also,
Since the current flowing through the control lines L3 and L4 has been interrupted, the first SQUID 1 transitions to the superconducting state.

Therefore, even if a current flows through the first SQUID 1 in the next cycle of the AC bias current AC, the control line L
3. Since no current flows through L4, the first SQUID
D1 does not switch to the voltage state and maintains the superconducting state.

Therefore, the AC bias current A
A pulse signal is output only once in synchronization with the input of C.

FIG. 2 is a waveform diagram showing threshold characteristics of the first SQUID and the second SQUID shown in FIG.
FIG. 3 is a diagram showing a state of an output waveform of the superconducting pulse signal generating circuit shown in FIG. 1. FIG. 3 (a) is an output waveform diagram when an AC bias current AC first starts from a positive polarity. FIG. 3B is an output waveform diagram when the AC bias current AC first starts from a negative polarity. Note that the vertical axis in FIG. 2 is the AC bias current value, and the horizontal axis is the current value flowing through the control wiring. Further, the SQUID is in a superconducting state inside the threshold characteristics shown in FIG. 2, and is a voltage state outside. Point A is the critical current value of the SQUID at zero magnetic field, and point B is
Is 75% of the zero-field critical current value, point C is 50% of the zero-field critical current value, and point D is the SQUID superconducting critical current value of 50% or less of the zero-field critical current value. Value of the current flowing through the control wiring.

As shown in FIG. 2, the first SQ of this embodiment
Since the threshold characteristic of UID1 is symmetric with respect to the positive and negative polarities of the AC bias current AC, the same operation is performed for a negative bias current. Therefore, as shown in FIG. 3A, if the AC bias current AC starts from a positive polarity, a single pulse signal of a positive polarity is generated, and as shown in FIG. Starts with a negative polarity, a single pulse signal of a negative polarity is generated.

As described above, according to the present embodiment, a superconducting circuit that generates a pulse signal only once in synchronization with the input of an AC bias current can be realized.

Although the present embodiment shows an example in which a two-junction SQUID is used as the SQUID, the same effect can be obtained by using another magnetic coupling type gate, for example, a three-junction SQUID.

(Second Embodiment) FIG. 4 is an equivalent circuit diagram showing a configuration of a second embodiment of the superconducting pulse signal generating circuit of the present invention.

The superconducting pulse signal generating circuit of the present embodiment is different from the first embodiment in the configuration of the first SQUID. The other configuration is the same as that of the first embodiment, and a description thereof will be omitted.

In FIG. 4, the first SQUID of this embodiment is shown.
D11 is an inductance L11, an inductance L1
1 is connected to both ends of the damping resistor Rd11 and the two ends of the damping resistor Rd11, one end of which is connected to the Josephson junction elements J11 and J12, and the control wire L12 magnetically coupled to the inductance L11. Have.

In such a configuration, the first embodiment
The SQUID 11 has a threshold characteristic that is asymmetric with respect to the AC bias current as shown in FIG. Therefore, the superconducting pulse signal generation circuit of this embodiment operates in the same manner as the first embodiment, but since the threshold characteristic of the first SQUID 11 is asymmetric, even if an AC bias current is supplied, the positive polarity Is output only.

According to the threshold characteristics shown in FIG.
SQUID 11 goes into a voltage state (operating point A) in synchronization with the rising of the positive polarity of the AC bias current, and outputs a single pulse of the positive polarity only once (for the rising of the negative polarity of the AC bias current). Is the first SQUID11
Becomes the point B, and the superconducting state is maintained).

In this embodiment, the configuration of the circuit for outputting a single pulse signal of a positive polarity only once is shown. However, by connecting the AC bias point of the first SQUID 11 and the ground potential in reverse, the circuit is reversed. Polarity (negative polarity) threshold characteristics can be easily obtained. In this case, a single negative polarity pulse signal can be output only once.

Therefore, according to the configuration of this embodiment, a single pulse signal having a predetermined polarity (positive or negative) can be generated only once in synchronization with the input of the AC bias current.

Although this embodiment shows an example in which a two-junction SQUID is used as the SQUID, the same effect can be obtained by using another magnetic coupling type gate, for example, a three-junction SQUID.

(Third Embodiment) FIG. 6 is a block diagram showing the configuration of a third embodiment of the superconducting pulse signal generating circuit according to the present invention. The superconducting pulse signal generating circuit of the present embodiment includes the superconducting pulse signal generating circuit shown in the second embodiment and three latch circuits (a first latch circuit 13 and a second latch circuit 1).
4 and a third latch circuit 15).

Each of the first to third latch circuits 13 to 15 is composed of, for example, a D flip-flop, and the true signal output of the first latch circuit 13 is input to the second latch circuit 14, The true signal output of the latch circuit 14 is input to the third latch circuit 15 and connected in series. Further, a true signal output of the third latch circuit 15 is fed back to the first latch circuit 13 to form a loop. The output of the superconducting pulse signal generation circuit is input to the first latch circuit 13.

In such a configuration, when a positive pulse signal is output from the superconducting pulse signal generating circuit shown in the second embodiment in the first cycle of the AC bias current AC, this pulse signal becomes the first pulse. , And the first latch circuit 13 holds the signal of “1”.

In the next cycle, the signal held in the first latch circuit 13 is sent to the second latch circuit 14, and
"1" is held by the latch circuit 14 of FIG. At this time, since the superconducting pulse signal generating circuit generates a pulse signal only once, "0" is held in the first latch circuit.

Further, in the next cycle, the signal held in the second latch circuit 14 is sent to the third latch circuit 15, and "3" is held in the third latch circuit 15. At this time, the first latch circuit 13 and the second latch circuit 14
Since no signal is input to, "0" is held for each.

Further, in the next cycle, the signal held in the third latch circuit 15 is sent to the first latch circuit 13, and "1" is held in the first latch circuit 13.

Thereafter, the same operation is repeated while the AC bias current AC is being supplied.

Therefore, according to the superconducting pulse signal generating circuit of this embodiment, it is possible to realize a superconducting pulse signal generating circuit that generates a pulse signal every three periods of the AC bias current.

FIG. 7 is a waveform diagram showing an output waveform of the superconducting pulse signal generating circuit shown in FIG.

In this embodiment, the first latch circuit 13
It is assumed that the third to third latch circuits 15 operate with positive polarity and unipolar, respectively, and operate from one positive polarity of the AC bias current AC to the next positive polarity as one clock.

In this embodiment, the case where three latch circuits are used has been described. However, by connecting n latch circuits with the same configuration, a circuit for generating a pulse signal every n clocks is constructed. can do.

Further, in this embodiment, the case where the superconducting pulse signal generating circuit shown in the second embodiment is used has been described.
Even if the superconducting pulse signal generation circuit shown in the first embodiment is used, a circuit that operates in the same manner can be configured.

[0050]

Since the present invention is configured as described above, the following effects can be obtained.

First SQ to which AC bias current is supplied
A control wiring arranged to be magnetically coupled to the UID and the first SQUID and supplied with a DC current; and a DC current inserted into the control wiring and flowing through the control wiring to the first SQ.
By having the second SQUID that shuts off according to the output signal of the UID, a superconducting circuit that generates a pulse signal only once in synchronization with the input of the AC bias current can be realized.

Further, by adding a plurality of latch circuits using an AC bias current as an operation clock, it is possible to realize a superconducting circuit that generates a pulse signal at predetermined intervals.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a configuration of a first embodiment of a superconducting pulse signal generation circuit according to the present invention.

FIG. 2 shows a first SQUID and a second SQ shown in FIG.
FIG. 4 is a waveform chart showing a threshold characteristic of a UID.

FIG. 3 is a diagram showing a state of an output waveform of the superconducting pulse signal generation circuit shown in FIG. 1; FIG. 3 (a) is an output waveform diagram when an AC bias current AC first starts from a positive polarity; FIG. 7B is an output waveform diagram when the AC bias current AC first starts from a negative polarity.

FIG. 4 is an equivalent circuit diagram showing a configuration of a second embodiment of the superconducting pulse signal generation circuit of the present invention.

FIG. 5 is a waveform chart showing a threshold characteristic of the first SQUID shown in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a third embodiment of the superconducting pulse signal generation circuit of the present invention.

FIG. 7 is a waveform chart showing an output waveform of the superconducting pulse signal generation circuit shown in FIG. 6;

FIG. 8 is an equivalent circuit diagram showing a configuration of a conventional superconducting pulse signal generation circuit.

[Explanation of symbols]

 1, 11 First SQUID 2 Second SQUID 13 First Latch Circuit 14 Second Latch Circuit 15 Third Latch Circuit L1, L2, L5, L6, L11 Inductance L3, L4, L7, L8, L12 Control Wiring J1 to J4, J11, J12 Josephson junction element Rb1, Rb2 Bias feed resistance RL1, RL2 Load resistance

Claims (6)

[Claims] 1. A superconducting pulse signal generating circuit for outputting a pulse signal only once in synchronization with an input of an AC bias current as an AC current, wherein the first SQUID to which the AC bias current is supplied is provided.
And a control wiring arranged to be magnetically coupled to the first SQUID and supplied with a DC current; and a DC current inserted into the control wiring and flowing through the control wiring, A superconducting pulse signal generating circuit, comprising: a second SQUID that cuts off in response to an output signal. 2. The superconducting pulse signal generating circuit according to claim 1, wherein said first SQUID has a threshold characteristic which is symmetric with respect to said AC bias current. 3. The first SQUID includes: two inductances connected in series; a damping resistor connected in parallel with the two inductances; and two ends connected to both ends of the damping resistor, one end of which is grounded. 3. The superconducting pulse signal generating circuit according to claim 2, further comprising two Josephson junction elements, wherein the AC bias current is supplied to a connection point between the two inductances. 4. The superconducting pulse signal generating circuit according to claim 1, wherein said first SQUID has a positive-negative asymmetric threshold characteristic with respect to said AC bias current. 5. The first SQUID includes: an inductance; a damping resistor connected in parallel with the inductance; two Josephson junction elements respectively connected to both ends of the damping resistor and having one end grounded; 5. The superconducting pulse signal generation circuit according to claim 4, wherein the AC bias current is supplied to one end of the inductance. 6. The superconducting pulse signal generating circuit according to claim 1, further comprising: a plurality of latch circuits that use the AC bias current as an operation clock. The output of the preceding latch circuit is connected in series by being connected to the input of the subsequent latch circuit, and the output signal of the superconducting pulse signal generation circuit is input to the first latch circuit connected in series, A superconducting pulse signal generating circuit in which an output signal of a first-stage latch circuit is fed back to an input of the first-stage latch circuit.