JPH11163498A - Method for designing printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for manpower and shorten design time and enhance design quality by determining bounds within which a specific part is mounted on a printed wiring board, and changing design of a resist pattern by data of an area which needs design changes within the determined bounds. SOLUTION: The position of a mounting plane of a specific part is found as P1=C plane, P2 = S plane, and the coordinates of the specific part is known as P1=X1, Y1, P2=X2, Y2, and an area D1×E1, D2×E2 where solder resist is applied to Via within the bounds to block an opening is recognized. The design of Via under the specific part is changed so as to block Via by making a batch deletion of an instruction for solder resist opening, and Via 17 becomes Via 19, and solder resist is applied. On the other hand, in Via 18 outside the area, the instruction for solder resist opening is left effective, resulting in obtaining a solder resist pattern. This allows design time to be shorten and reliable boards to be designed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming solder resist data (or masking data) in a through-hole (hereinafter referred to as "Via") of a printed wiring board (hereinafter referred to as "substrate").

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional solder resist (or masking) data generator disclosed in Japanese Patent Application Laid-Open No. 5-54101. In the figure, the apparatus obtains input data from the component placement information c to the design reference information h, and develops a masking escape graphic storage area m from an external file input apparatus a, a masking data generation apparatus b, and a masking area storage area j. It consists of each element of the data table up to. FIG. 8A is a cross-sectional view of a substrate on which a portion including a general array grid component is mounted.
FIG. 8B is an enlarged view thereof.

Next, the operation of this apparatus will be described with reference to FIGS. In FIG. 7, input data from the component placement information c to the design reference information h is read into the external file input device a,
Create masking area data, masking escape graphic data, etc. necessary in the masking data generator b,
These are combined to create masking data i. However, in such a method, the Vias 23 and 25 are not masked, so that the array grid component 21 or a component whose lower surface is not insulated such as the array grid component in FIG. Also, a masking escape graphic is generated in the Via 25 designed below. In a conventional solder resist pattern (masking pattern) design program, there is no choice but to simply perform or not perform masking. If the data created by this program is used as it is, the Via portion is not masked, and therefore, if soldering is performed in a later step, there is a possibility that the component terminal or the like and the Via will be short-circuited by the solder or the like. In order to avoid this, it is necessary to delete the via portion masking relief pattern below the array grid component or the like in a later process to obtain the state of the mask pattern 22 in FIG. 8B.

[0004]

The conventional masking data generator is constructed as described above, and the masking portion cannot be corrected more finely, so that a practical masking pattern for a substrate is designed. Had the problem that human intervention was required. This requires a great deal of work time and results in variations in the resulting design quality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a method of designing a board which eliminates manual intervention, reduces design time, and improves design quality.

[0006]

A printed wiring board designing method according to the present invention is a flow for arranging predetermined components on a printed wiring board to determine a wiring pattern and designing a resist pattern related to the wiring pattern. In, a specific component mounting surface recognition step of determining the mounting range of the specific component on the printed wiring board, and obtaining data of an area requiring a design change within the range obtained in the specific component mounting surface recognition step, A design change step of obtaining a resist data by changing a design of a corresponding portion of the resist pattern based on the obtained data.

Further, in the design change step, the data is collectively processed after the data of the wiring pattern is obtained.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a diagram showing an example of a flowchart of an operation for obtaining solder resist data by applying the substrate design method according to the present invention. FIG. 1 shows a method for obtaining a closed pattern by removing opening instruction data of a via-part solder resist set under a specific component such as an array grid component after the completion of wiring design of a substrate. In the figure, reference numeral 1 denotes connection information from the circuit design side, for example, a connection diagram or net information. Reference numeral 2 denotes a step of receiving the connection information 1 and performing a component layout design on the board wiring CAD as a design tool. In this step, the component shape and the mounting shape on the board side are defined in the component library of 4. The shape information is referred to in the component placement step. For a specific component for which the solder resist opening is to be closed in a via thereunder, information such as the component name and dimensions is defined in this component library. 3
Is a step of performing pattern wiring design after component placement is completed. In this step, information such as the wiring rule and the opening shape of the solder resist in the via portion is defined in the fifth wiring technology. Step 6 is a step of generating solder resist data after completion of wiring. 7 is a step of recognizing the presence or absence of a component whose solder resist opening below the corresponding component is desired to be closed from the data on which the pattern wiring design is completed;
Is a step of recognizing a mounting surface of the specific component, 9 is a step of recognizing an area under the component in which a via-resist is to be performed to close the opening, that is, a design change is required, and 10 is a solder-resist data. This is an opening removing step (design changing step) in which the via-part solder resist opening instruction data of the area is collectively removed from the solder resist data obtained in the generation step 6 and changed to a closed state.

Next, an operation of obtaining a resist pattern by applying the operation flow of FIG. 1 will be described. FIG. 2 is a diagram for explaining an operation in each step of board design.
7 to 10 in (a) to (c) and (e) of the drawing explain the operation in the corresponding step of FIG. First, FIG.
In step (a) of step 7 for recognizing the presence / absence of a specific component, it is determined whether or not a component to be closed is provided by applying a solder resist to the via below the component on the board after the design is completed. In this case, the corresponding specific part P
1. Recognize P2. In the specific component mounting surface recognition step 8, the positions of the specific component P1 = C surface and P2 = S surface are recognized. In the specific part area recognition step 9, the coordinates P1 = X1, Y1, P2 = X2, Y2 of the specific part are known,
Areas D1.times.E1 and D2.times.E2 in which the openings are desired to be closed by applying a via solder resist.
Recognize.

In these steps, information on the part and the area is referred to by extracting a code for recognizing the part and data of the area from data in the part library 4. 2D and 2E show the specific part P.
FIG. 2 is an enlarged view of a 1 (array grid component) mounting portion substrate side. In the resist opening removing step 10, reference numeral 14 denotes an area where a via hole is not desired to be provided in the via, 15 denotes a solder resist, 16 denotes an array grid component mounting pad, and 17 denotes a V in a specific component area.
ia and 18 indicate Vias outside the component area.

The resist opening removing step will be described with reference to FIG. Whether or not certain Via portion opening data in the solder resist data 6 is to be deleted is determined, for example, as follows. In P1, the coordinates (X
When the area from (11, Y11) to (X12, Y12) is a specific component area, it is determined whether the resist opening data K at a certain coordinate (Xk, Yk) is to be deleted or not at the coordinates (Xk, Yk) of the resist opening data K. ) Is compared with the coordinate range (X11, Y11 to X12, Y12) of the specific component area. That is, [X11 <Xk <X12] and [Y
If 11 <Yk <Y12], the resist K is determined to be the coordinate range of the specific component area. In the resist opening removing step 10, the vias under the specific component are collectively deleted and the design change is made so as to cover the solder resist opening instruction, and the corresponding Via 17 in FIG. 2D is the Via 17 in FIG.
At 19, a solder resist is applied. On the other hand, the via 18 outside the area has the solder resist opening instruction as it is, and the solder resist pattern of FIG. 2E is obtained.

As described above, the resist opening removing step may be provided during the batch processing after the pattern design is completed. However, when the individual vias are arranged and designed in the pattern wiring design step, the resist opening removing step is required. To determine if it is under the specified part
You may make it output as data. FIG. 4 is a flowchart of a method of changing the design so as to delete a via-part solder resist opening instruction under a specific component in a wiring design and apply a resist. In the figure, connection information 1, component layout design step 2, and component library 4 are the same as those of the same numbers in FIG. In the wiring technology 5b, a via specification with a solder resist opening and a via specification without an opening are provided. Reference numeral 12 denotes a step of arranging vias in one process of wiring design. Where V
In the ia specification, the presence of an opening is standard (default). 7 is a step of applying a solder resist to the Via from the data under design to recognize whether or not the component is a component for closing the opening;
Is a step of recognizing a surface on which the specific component is mounted; 9 is a step of recognizing an area in which design is changed so as to cover an opening by applying a solder resist under the component;
Reference numeral 3 denotes a via having an opening and a via having no opening when it is detected that a via is provided in the area of the specific component.
This is the step of changing the design to specifications. Reference numeral 6 denotes the solder resist data created as described above.

The operation of obtaining a resist pattern will be described with reference to the flowchart of FIG. FIG. 5 is a diagram for explaining the operation of the Via type changing step (design changing step) in FIG. In FIG. 5, reference numeral 20 denotes a via whose design has been changed from a via with a resist opening to a specification without a resist opening, and other numbers are the same as the elements of the same numbers in FIG. In a pattern wiring design step or a solder resist data generation step 6d parallel to the pattern wiring design step, a Via layout design is performed with Vias in a Via design step 12 with reference to the wiring technology 5b. Thereafter, via steps 7 to 9 similar to those in FIG.
It reaches the line type change step 13. In this step, the via provided in the area 14 to be changed in design is recognized, and the via is changed from the via with the solder resist opening to the via without the opening. The method of determining the coordinate position is performed by the method described with reference to FIG. FIG. 5 shows the Via 20 (D02) thus redesigned.
On the other hand, as the Via provided outside the area, a normal Via 18 (D01) having a solder resist opening is arranged and designed. FIG. 6 shows a via (D01) having a normal opening and a via (D0) having no opening arranged and designed in the area.
It is the figure which showed the example of specification of 2).

[0014]

As described above, according to the present invention, the resist pattern of Via is partially changed by recognizing the range of a specific component, so that the design time can be shortened and the substrate can be designed with high reliability. .

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an operation flow of a printed wiring board design method of the present invention.

FIG. 2 is a diagram for explaining an operation in each step of FIG. 1;

FIG. 3 is a diagram for explaining an operation of a resist opening removing step in FIG. 2;

FIG. 4 is a diagram illustrating another operation flow of the printed wiring design method.

FIG. 5 is a diagram for explaining the operation of a Via type changing step in FIG. 4;

FIG. 6 is a diagram illustrating an example of Via in FIG. 5;

FIG. 7 is a configuration diagram of a conventional masking data generation device.

FIG. 8 is a sectional view showing a relationship between an array grid component and a through hole.

[Explanation of symbols]

1 connection information, 2 component placement design step, 3 pattern wiring design step, 4 component library, 5 wiring technology, 6 solder resist data generation step, 7 specific component presence / absence recognition step, 8 specific component mounting surface recognition step, 9 specification Parts area recognition step,
10 Step of removing resist opening in area, 12 Vi
a design step, 13 area via type change step, 14 area to be resisted, 15 solder resist, 16 array grid component mounting pad, 1
7 Via with opening in the area, 18 Via outside the area, 19 Vi with opening instruction deleted in the corresponding area
a, 20 Via without opening in the area, 21 Array grid component, 22, 26 Solder resist, 2
3 Via outside the area, resist opening at 24 Via section, 25 Via inside the area.

Claims (2)

[Claims] In a flow of arranging predetermined components on a printed wiring board to determine a wiring pattern and designing a resist pattern related to the wiring pattern, a mounting range of a specific component is set on the printed wiring board. A specific component mounting surface recognition step to be determined, and data of an area requiring a design change within the range obtained in the specific component mounting surface recognition step are obtained, and the corresponding portion of the resist pattern is changed in design based on the data. And a design change step of obtaining resist data by using the method. 2. The printed wiring board design method according to claim 1, wherein the design change step is performed collectively after the data of the wiring pattern is obtained.