JPH11163392A - Semiconductor relay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor relay which can be made compact and thin and is capable of improving yield in mounting. SOLUTION: On one surface of a flat-shaped circuit substrate 1, where a wiring pattern is formed into a predetermined shape, an LED2 and a photoelectromotive element 3 is subjected to die bonding through Ag paste or the like, and wire bonding is performed so as to electrically connect wiring pattern by Au wire 4 or the like. LED2 and the photoelectromotive element 3 are covered with a transparent resin 5 through which light is able to transmit, and the transparent resin 5 is further covered with a light-shielding resin 6 which does not transmit light. Also, at the mounting surface side for the photoelectromotive element 3 of the circuit substrate 1, MOSFETs 7a, 7b are flip-chip mounted via a bump 8 and the MOSFETs 7a, 7b are encapsulated by the light-proof resin 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor relay using isolation by optical coupling, and more particularly to a photomos relay.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional photomos relay. A light emitting diode (LED: Light Emitting) as a light emitting element is provided between the relay input terminals 9a and 9b.
A photodiode array 3 is connected, and a photodiode array 10 is optically coupled to the LED 2.

The anode of the photodiode array 10 has an M-channel output for an N-channel enhancement mode output.
The OSFETs 7a, 7b are connected to the gates, and the cathodes are connected via resistors R to the sources of the MOSFETs 7a, 7b.

A drain-source of an N-channel depletion mode driving MOSFET 11 is connected between the gates and sources of the output MOSFETs 7a and 7b. The gate of the driving MOSFET 11 is connected to the cathode of the photodiode array 10.

The drains of MOSFETs 7a and 7b are connected to the relay output terminals 12a and 12b, respectively.
The sources of the ETs 7a and 7b are connected to the relay output terminal 12c.

The operation of the conventional photomos relay will be described below with reference to FIG. Relay input terminals 9a, 9
When an input current flows between b, the LED 2 generates a light signal. Upon receiving this optical signal, the photodiode array 10 generates a current. This current flows to the resistor R via the driving MOSFET 11 which is always on, and when the voltage generated by the resistor R exceeds the threshold voltage of the driving MOSFET 11, the driving MOSFET 11 is turned off. As a result, the current from the photodiode array 10 charges the gates and sources of the output MOSFETs 7a and 7b. When the charged voltage exceeds the threshold voltage of the output MOSFETs 7a and 7b, the output MOSFETs 7a and 7b Is turned on, and the relay output terminals 12a to 12c conduct. Thereafter, a small current flows through the resistor R through the drain and source of the driving MOSFET 11, and the driving MOSFET 11 is held at a high impedance by the bias voltage generated at the resistor R.

Next, when the current between the relay input terminals 9a and 9b is cut off and there is no light signal from the LED 2, there is no current from the photodiode array 10. As a result, the gate-source voltage of the driving MOSFET 11 drops, and the driving MOSFET 11 is turned on, and the output MOSFET 11 is turned on.
The charges accumulated between the gates and sources of the MOSFETs 7a and 7b are rapidly discharged through the driving MOSFET 11.
As a result, the output MOSFETs 7a and 7b are turned off, and the relay output terminals 12a to 12c are shut off.

In the above circuit, the output MOSFETs 7a, 7
In the steady state where b is on, the driving MOSF
Even if the current flowing through the ET 11 is small, it is possible to obtain a bias voltage sufficient to hold the driving MOSFET 11 in the off state by increasing the value of the resistor R.

FIG. 4 is a schematic cross-sectional view showing the entire structure of a conventional photomoss relay. Lead frame 13
The MOSFETs 7a and 7b and the photovoltaic element 3 are die-bonded on Ag, using Ag paste or the like, and wire-bonded. Here, the photovoltaic element 3 refers to
This is an element in which the photodiode array 10, the driving MOSFET 11, and the resistor R are integrated into one chip.

On the other hand, an LED is mounted on the lead frame 13b.
2 is die-bonded with Ag paste or the like, and wire-bonded, and the lead frames 13a and 13b are
2 and the photovoltaic element 3 are arranged to face each other.

Then, between the LED 2 and the photovoltaic element 3,
It is filled with a light-transmitting resin 5 that transmits light, and is entirely molded by a package 14 made of a light-shielding resin.
At this time, the lead frame 13 is removed from the package 14.
One end of each of a and 13b is configured to protrude.

Here, if the MOSFETs 7a and 7b are mounted on two chips, both can be used for DC / AC, but if one chip is used, only DC is used due to the diode characteristics of the MOSFET.

[0013]

However, in the semiconductor relay having the above-mentioned structure, each chip is die-bonded on a lead frame and wire-bonded, so that the LED and the photovoltaic element are arranged to face each other. However, there has been a problem that it is difficult to realize a reduction in thickness and size.

Further, when the whole is molded by the package 14, the lead frames 13a and 13b may be bent due to the flow of the resin to be molded, and it becomes difficult to secure a facing distance between the LED 2 and the photovoltaic element 3. However, there is a problem that the mounting yield is deteriorated.

As a method for solving the above-mentioned problem, there is a method disclosed in Japanese Patent Application Laid-Open No. 4-356974. This is a structure in which a light emitting element, a photovoltaic element, and a MOS transistor are arranged on the same surface of a base material, and after performing wire bonding, the light emitting element and the photovoltaic element are sealed with a translucent resin. It is.

However, in the above configuration, since it is necessary to wire-bond the MOS transistor,
It was necessary to form a pad for wire bonding on the base material, and it was not possible to reduce the size much.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor relay which can be reduced in size and thickness and can improve a mounting yield. is there.

[0018]

According to the first aspect of the present invention,
A light emitting element and a photovoltaic element are mounted on the same surface of one substrate on which a wiring pattern is formed, and the light emitting element and the photovoltaic element are covered with a light transmitting resin, and the light transmitting resin is shielded from light. MOSFET is flip-chip mounted on the substrate, and light from the light emitting element is reflected at the interface between the light transmitting resin and the light shielding resin, and is received by the photovoltaic element. It is characterized by doing so.

According to a second aspect of the present invention, in the semiconductor relay according to the first aspect, the MOSFET is flip-chip mounted on the photovoltaic element mounting surface and / or a different surface of the substrate. It is characterized by the following.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. The circuit configuration of the photo MOS relay according to the present embodiment is the same as the circuit configuration of the photo MOS relay shown in FIG. 3 as a conventional example. Further, in the present embodiment, a case where an N-channel type is used as the MOSFETs 7a, 7b, 11 will be described. In this case, the photodiodes 10 are connected so that the polarities of the photodiode arrays 10 are reversed.
Further, the same reference numerals are given to the same components as those of the photo MOS relay shown in FIG. 4 as a conventional example, and the description is omitted.

FIG. 1 is a schematic sectional view showing the entire configuration of a photomos relay according to an embodiment of the present invention. In the photo MOS relay according to the present embodiment, an LED 2 and a photovoltaic element 3 are made of Ag paste on one surface of a flat circuit board 1 on which a wiring pattern (not shown) patterned in a predetermined shape is formed. And the like, and are wire-bonded by the Au wire 4 or the like so as to be electrically connected to the wiring pattern.

The LED 2 and the photovoltaic element 3 are covered with a light-transmitting resin 5 that transmits light, and the light-transmitting resin 5 is further covered with a light-shielding resin 6 that does not transmit light.

The MOSFETs 7 a and 7 b are flip-chip mounted on the photovoltaic element 3 side of the circuit board 1 via bumps 8, and the MOSFETs 7 a and 7 b are sealed with a light-shielding resin 6.

In this embodiment, the circuit board 1
In order to mount the MOSFETs 7a and 7b on the flip chip,
As the MOSFETs 7a and 7b, for example, an LDMOSFET (La MOSFET) having gate, source and drain electrodes existing on the same plane of the chip
teral Double Diffused MOSFET).

Therefore, in this embodiment, the LED 2, the photovoltaic element 3, the MOSFET 7a,
7b and the MOSFETs 7a and 7b are flip-chip mounted, so that the MOSFETs 7a and 7b are mounted on the circuit board 1.
Therefore, it is not necessary to form a pad for wire bonding, so that the photoMOS relay can be made thinner and smaller.

Further, since the LED 2 and the photovoltaic element 3 are die-bonded on one circuit board 1, the lead frame does not bend due to sealing, and the mounting yield can be improved.

The LED 2 and the photovoltaic element 3 are covered with a light-transmitting resin 5, and the light-transmitting resin 5 is covered with a light-shielding resin 6.
Since the light from the LED 2 is reflected at the interface between the translucent resin 5 and the light-shielding resin 6, the alignment accuracy of the LED 2 and the photovoltaic element 3 may be low.

In this embodiment, two MOSFs are used.
The ETs 7a and 7b are flip-chip mounted on the photovoltaic mounting surface side of the circuit board 1. However, the present invention is not limited to this, and one of the MOSFETs 7a and 7b may be flip-chip mounted on the back surface. As shown in FIG.
a and 7b may be flip-chip mounted, thereby further reducing the size.

Further, in the above-described embodiment, the case where the LED 2 is die-bonded and the wire bonding is performed has been described. However, a wire bondless LED for horizontal mounting may be used as the LED 2.

In the above embodiment, the case where two MOSFETs are mounted has been described. However, the present invention is not limited to this, and only one MOSFET may be mounted only for DC. .

[0031]

According to the first aspect of the present invention, a light emitting element and a photovoltaic element are mounted on the same surface of one substrate on which a wiring pattern is formed, and the light emitting element and the photovoltaic element are translucent. Covered with resin, the translucent resin is covered with the light-blocking resin, the MOSFET is flip-chip mounted on the substrate, and light from the light emitting element is reflected at the interface between the light-transmitting resin and the light-blocking resin. Since the light is received by the power element, there is no bending of the lead frame, and there is no need to form a pad for wire bonding the MOSFET on the substrate, so that the size and thickness can be reduced and the mounting yield can be improved. A semiconductor relay could be provided.

According to a second aspect of the present invention, in the semiconductor relay of the first aspect, the MOSFET is flip-chip mounted on a photovoltaic element mounting surface and / or a different surface of the substrate, so that the size is further reduced. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating an overall configuration of a photomos relay according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view illustrating an overall configuration of a photo MOS relay according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of a photo MOS relay according to a conventional example.

FIG. 4 is a schematic cross-sectional view showing the entire configuration of a photomos relay according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit board 2 LED 3 Photovoltaic element 4 Au wire 5 Translucent resin 6 Light-shielding resin 7a, 7b MOSFET 8 Bump 9a, 9b Relay input terminal 10 Photodiode array 11 MOSFET 12a-12c Relay output terminal 13a, 13b Lead Frame 14 Package R Resistance

Claims (2)

[Claims] 1. A light emitting element and a photovoltaic element are mounted on the same surface of one substrate on which a wiring pattern is formed, and the light emitting element and the photovoltaic element are covered with a translucent resin.
The light-transmitting resin is covered with a light-shielding resin, a MOSFET is flip-chip mounted on the substrate, and light from the light-emitting element is reflected at an interface between the light-transmitting resin and the light-shielding resin, and A semiconductor relay characterized in that light is received by an electromotive element. 2. The semiconductor relay according to claim 1, wherein said MOSFET is flip-chip mounted on said photovoltaic element mounting surface and / or on a different surface of said substrate.