JPH11163025A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH11163025A JPH11163025A JP33217297A JP33217297A JPH11163025A JP H11163025 A JPH11163025 A JP H11163025A JP 33217297 A JP33217297 A JP 33217297A JP 33217297 A JP33217297 A JP 33217297A JP H11163025 A JPH11163025 A JP H11163025A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- chip
- lead frame
- temperature
- slow cooling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/78—Apparatus for connecting with wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
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- H01L2924/01004—Beryllium [Be]
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/01029—Copper [Cu]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01065—Terbium [Tb]
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- H01L2924/01073—Tantalum [Ta]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子（半導体
チップまたは半導体ペレットなど）等を搭載する半導体
装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device on which a semiconductor element (such as a semiconductor chip or a semiconductor pellet) is mounted.
【０００２】[0002]
【従来の技術】図２は側面からみた従来のワイヤーボン
ディング工程と各工程位置でのブロックの温度或いは雰
囲気温度を示している。まず、トレー１からリードフレ
ーム３が搬送方向４で示されるように搬出され、ヒータ
ー８ａにより温度調整されている予熱ブロック５の上で
リードフレーム３を予熱温度Ｔｐまで加熱する。なお、
リードフレーム３には、図５に示されているように半導
体素子１４（以下単にＩＣチップという）が搭載されて
おり（図５において、リードフレームは符号１５で示さ
れており、ボンディングワイヤーは符号１６で示されて
いる）、ＩＣチップもリードフレームと同様に温度Ｔｐ
まで加熱される。次にヒーター８ｂにより温度調整され
ているヒートブロック６の上までリードフレーム３の搬
送が行われ、リードフレームとＩＣチップをボンディン
グ温度Ｔｂまで加熱した後、ＩＣチップ上の電極とリー
ドフレーム側の電極であるリードを電気的に接合するた
めのワイヤーボンディングが行われる。１枚のリードフ
レームには通常数個のＩＣチップが搭載されており、リ
ードフレーム上の全ＩＣチップのボンディング終了後、
リードフレームは収納トレー２に搬送されボンディング
工程は終了する。各位置での予熱ブロックとヒーターブ
ロック及び雰囲気の温度は図２で示されるようになって
おり、ボンディング後のＩＣチップは雰囲気温度Ｔａま
で自然冷却されることになる。このときリードフレーム
及びＩＣチップの温度は図４に示すような履歴１２を示
すことが、本発明者の評価により明らかになっており、
雰囲気温度Ｔａが２５℃、ボンディング温度Ｔｂが２０
０℃であるとき、該ボンディング温度Ｔｂから雰囲気温
度Ｔａ＋５℃に達するまでの時間ｔ０はＩＣチップとリ
ードフレームの種類に依存するが約１５秒〜３０秒であ
り、（Ｔａ＋５−Ｔｂ）／ｔ０であらわされる平均温度
勾配は約−６℃／秒〜−１２℃／秒となっている。2. Description of the Related Art FIG. 2 shows a conventional wire bonding process as viewed from the side, and a block temperature or an ambient temperature at each process position. First, the lead frame 3 is carried out from the tray 1 as shown in the transport direction 4, and the lead frame 3 is heated to the preheating temperature Tp on the preheating block 5 whose temperature is adjusted by the heater 8a. In addition,
As shown in FIG. 5, a semiconductor element 14 (hereinafter simply referred to as an IC chip) is mounted on the lead frame 3 (in FIG. 5, the lead frame is denoted by reference numeral 15 and the bonding wires are denoted by reference numeral 15). 16), the IC chip has the same temperature Tp as the lead frame.
Heated until. Next, the lead frame 3 is transported over the heat block 6 whose temperature is adjusted by the heater 8b, and the lead frame and the IC chip are heated to the bonding temperature Tb. Then, the electrodes on the IC chip and the electrodes on the lead frame side are heated. Wire bonding for electrically joining the leads is performed. Usually, several IC chips are mounted on one lead frame. After bonding of all the IC chips on the lead frame is completed,
The lead frame is conveyed to the storage tray 2 and the bonding step is completed. The temperatures of the preheating block, the heater block, and the atmosphere at each position are as shown in FIG. 2, and the IC chip after bonding is naturally cooled to the ambient temperature Ta. At this time, the temperature of the lead frame and the IC chip shows a history 12 as shown in FIG.
Atmospheric temperature Ta is 25 ° C., bonding temperature Tb is 20
When the temperature is 0 ° C., the time t0 from the bonding temperature Tb to the ambient temperature Ta + 5 ° C. is about 15 seconds to 30 seconds depending on the type of the IC chip and the lead frame, and is (Ta + 5−Tb) / t0. The average temperature gradient represented is about -6C / sec to -12C / sec.
【０００３】また、最近はパッケージの熱抵抗低下を目
的とし銅合金製のリードフレーム等が用いられている
が、銅合金製リードフレームでは熱膨張率が大きく加熱
時のリードフレームの熱変化が大きいため、搬送時のト
ラブル防止を目的として乾燥空気や窒素等でボンディン
グ中やボンディング後のリードフレームの冷却が行われ
ている。その場合リードフレームに搭載されたＩＣチッ
プは図４で示した温度履歴１２よりもさらに急激な温度
降下を示すことになる。Recently, a lead frame made of a copper alloy has been used for the purpose of reducing the thermal resistance of a package. However, a copper alloy lead frame has a large coefficient of thermal expansion and a large thermal change of the lead frame during heating. Therefore, the lead frame is cooled during or after bonding with dry air, nitrogen, or the like for the purpose of preventing trouble during transport. In that case, the IC chip mounted on the lead frame will show a more rapid temperature drop than the temperature history 12 shown in FIG.
【０００４】このように温度勾配が激しいと、接合部に
生じる圧着ボールと電極の熱膨張差によって生じる熱応
力が電極の表層を構成するアルミニウム膜内で充分に緩
和されず、最悪の場合アルミニウム膜下のバリア層や層
間膜、あるいはシリコンで剥離やクラックが発生し、電
極にダメージが生じるという問題が生じるようになって
きている。[0004] When the temperature gradient is so steep, the thermal stress caused by the difference in thermal expansion between the press-bonded ball and the electrode generated at the joint is not sufficiently relaxed in the aluminum film constituting the surface layer of the electrode. There has been a problem that peeling or cracking occurs in a lower barrier layer, interlayer film, or silicon, causing damage to electrodes.
【０００５】[0005]
【発明が解決しようとする課題】近年、ＩＣチップの微
細加工技術が進み、同一規模の回路構成ではＩＣチップ
の大きさは小さくなりつつあり、回路を構成する配線の
幅が細くなるに伴い、配線並びに電極を構成するアルミ
ニウム膜の厚さも薄くなりつつある。In recent years, the fine processing technology for IC chips has advanced, and the size of IC chips has been reduced in a circuit configuration of the same scale. The thickness of the aluminum film forming the wiring and the electrode is also becoming thinner.
【０００６】一方、従来のワイヤーボンディング工程で
は図６（Ａ），（Ｂ）で示されるように、アルミニウム
膜１８ａ，１８ｂ上に圧着ボール１７の接合が行われる
が、ＩＣチップは前述のように自然冷却、或いは乾燥空
気等により強制冷却されているため、電極の接合部は図
４の温度履歴１２で示されるような急冷状態となり２１
ａ，２１ｂに示されるような熱応力が圧着ボールとアル
ミニウム膜１８ａ，１８ｂの界面に生じる。ここで図６
（Ａ）はアルミニウム膜厚が充分に厚い場合であり、図
６（Ｂ）はアルミニウム膜厚が薄い場合を示す。アルミ
ニウム膜厚が厚い場合は２１ａで示される応力は、アル
ミニウム膜内の塑性変形により十分緩和されるため、ア
ルミニウム膜とバリア層１９との界面での熱応力２２ａ
ならびにバリア層１９と層間膜２０の界面での熱応力２
３ａは小さなものとなるが、アルミニウム膜厚が薄い場
合は２１ｂの熱応力がアルミニウム膜内で充分に緩和さ
れないために、それぞれの界面での応力２２ｂ，２３ｂ
は２２ａ，２３ａと比較して大きなものとなる。On the other hand, in the conventional wire bonding process, as shown in FIGS. 6A and 6B, the press-bonded ball 17 is bonded onto the aluminum films 18a and 18b. Because of natural cooling or forced cooling by dry air or the like, the joints of the electrodes are rapidly cooled as shown by the temperature history 12 in FIG.
Thermal stress as shown at a and 21b occurs at the interface between the press-bonded ball and the aluminum films 18a and 18b. Here, FIG.
6A shows the case where the aluminum film thickness is sufficiently large, and FIG. 6B shows the case where the aluminum film thickness is small. When the thickness of the aluminum film is large, the stress indicated by reference numeral 21a is sufficiently relaxed by the plastic deformation in the aluminum film, so that the thermal stress 22a at the interface between the aluminum film and the barrier layer 19 is reduced.
Thermal stress 2 at the interface between the barrier layer 19 and the interlayer film 20
3a is small, but when the aluminum film thickness is small, the thermal stress of 21b is not sufficiently relaxed in the aluminum film.
Is larger than 22a and 23a.
【０００７】このように電極の表層を構成するアルミニ
ウム膜が薄くなるにつれて、圧着ボールとアルミニウム
膜間で発生する熱応力が緩和されずに直接アルミニウム
膜下の層間膜やさらにその下のシリコン層に及ぶように
なってきている。そのため、従来技術でボンディングさ
れた最近のＩＣチップにおいては層間膜の剥離やシリコ
ンにマイクロクラックが発生するなど、ボンディング後
の電極にダメージが入る現象が目につくようになってき
た。電極のダメージは、導電抵抗の増加やシリコンと端
子の間でリーク電流を引き起こすばかりでなく、これら
の不良が発生しない場合でも電極を構成する層間の接着
強度の低下を招くため、信頼性に大きな問題が残ること
になる。As described above, as the thickness of the aluminum film constituting the surface layer of the electrode becomes thinner, the thermal stress generated between the press-bonded ball and the aluminum film is not alleviated and the interlayer film directly under the aluminum film or the silicon layer thereunder is not reduced. Is becoming more widespread. For this reason, in recent IC chips bonded by the conventional technology, the phenomenon of damage to the electrodes after bonding, such as peeling of an interlayer film and generation of microcracks in silicon, has become noticeable. Electrode damage not only increases the conductive resistance and causes a leak current between the silicon and the terminal, but also causes a decrease in the adhesive strength between the layers constituting the electrode even when these defects do not occur. The problem will remain.
【０００８】本発明は以上の問題点に鑑みてなされたも
ので、その目的は、熱応力による電極の破壊を生ずるこ
となくボンディングし、ボンディング後の電極を構成す
る層間の接着信頼性の向上を実現させることにある。The present invention has been made in view of the above problems, and an object of the present invention is to improve bonding reliability between layers constituting electrodes after bonding by bonding without destruction of electrodes due to thermal stress. To make it happen.
【０００９】[0009]
【課題を解決するための手段】本発明によれば、以上の
如き目的を達成するものとして、半導体素子及び該半導
体素子と外部との電気的接続のために用いられる部材を
含む半導体装置を製造する方法において、前記半導体素
子の電極と前記外部との電気的接続のために用いられる
部材とを加熱下でボンディングする工程と、該ボンディ
ング工程後に前記半導体素子を徐冷する工程とを有する
ことを特徴とする半導体装置の製造方法、が提供され
る。半導体素子と外部との電気的接続のために用いられ
る部材としては、金属製リードフレーム（のリード）が
例示されるが、この部材は金属製のリードフレームに限
らず、例えばポリイミド樹脂に配線パターンを施したフ
ィルム状のものや、ＩＣチップが搭載される配線基盤な
どであっても良い。また、この部材は、ボンディング工
程及び徐冷工程では最終的な半導体装置における形態と
必ずしも同一である必要はなく、徐冷工程後に適宜の整
形あるいは加工が施されて最終的な半導体装置となるも
のであってもよい。According to the present invention, a semiconductor device including a semiconductor element and a member used for electrical connection between the semiconductor element and the outside is manufactured to achieve the above object. A method of bonding an electrode of the semiconductor element and a member used for electrical connection with the outside under heating, and a step of gradually cooling the semiconductor element after the bonding step. A method for manufacturing a semiconductor device is provided. As a member used for electrical connection between the semiconductor element and the outside, a metal lead frame (lead) is exemplified, but this member is not limited to a metal lead frame, and for example, a wiring pattern may be formed on a polyimide resin. Or a wiring board on which an IC chip is mounted. This member is not necessarily required to have the same form as the final semiconductor device in the bonding step and the slow cooling step, and is appropriately shaped or processed after the slow cooling step to become the final semiconductor device. It may be.
【００１０】本発明の一態様においては、前記徐冷工程
におけるボンディング温度から室温＋５℃までの平均温
度勾配を−２．０℃／秒またはそれより緩やかにする。In one embodiment of the present invention, the average temperature gradient from the bonding temperature to room temperature + 5 ° C. in the slow cooling step is set to −2.0 ° C./sec or less.
【００１１】本発明の一態様においては、前記ボンディ
ング工程に続いて前記徐冷工程を行う。本発明の一態様
においては、前記徐冷工程をヒータープレートを用いて
行う。In one embodiment of the present invention, the annealing step is performed following the bonding step. In one embodiment of the present invention, the slow cooling step is performed using a heater plate.
【００１２】本発明の一態様においては、前記ボンディ
ング工程に続いて保温工程を行い、該保温工程に続いて
前記徐冷工程を行う。本発明の一態様においては、前記
保温工程をヒータープレートを用いて行う。本発明の一
態様においては、前記徐冷工程を収納手段内で行う。本
発明の一態様においては、前記徐冷工程をホットエアー
噴射を用いて行う。In one embodiment of the present invention, a heat retaining step is performed after the bonding step, and the slow cooling step is performed after the heat retaining step. In one embodiment of the present invention, the heat retaining step is performed using a heater plate. In one aspect of the present invention, the slow cooling step is performed in a storage unit. In one embodiment of the present invention, the slow cooling step is performed using hot air injection.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態を添付
図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【００１４】［第１の実施形態］本発明の第１の実施の
形態を図１に示す。トレー１より、ヒーター８ａによっ
て温度調整された予熱ブロック５上にリードフレーム３
が矢印４で示される搬送方向に搬送され、雰囲気温度Ｔ
ａと同じ温度であったリードフレームとリードフレーム
に搭載されたＩＣチップは予熱温度Ｔｐまで加熱され
る。なお予熱ブロックについてはリードフレームとＩＣ
チップに予熱を与えるのが目的であるためリードフレー
ムに接触させても非接触でも構わない。その後ヒーター
８ｂによって温度調整されたヒーターブロック６上にリ
ードフレームの搬送が行われ、ボンディング温度Ｔｂま
で加熱が行われた後、ＩＣチップ上の電極とリードフレ
ーム側の電極であるリードとの間でワイヤーボンディン
グが行われる。[First Embodiment] FIG. 1 shows a first embodiment of the present invention. From the tray 1, the lead frame 3 is placed on the preheating block 5 whose temperature has been adjusted by the heater 8a.
Are transported in the transport direction indicated by arrow 4 and the ambient temperature T
The lead frame having the same temperature as a and the IC chip mounted on the lead frame are heated to the preheating temperature Tp. For preheating block, lead frame and IC
Since the purpose is to preheat the chip, it may be in contact with the lead frame or not. Thereafter, the lead frame is transported onto the heater block 6 whose temperature has been adjusted by the heater 8b, and is heated to the bonding temperature Tb. Then, between the electrode on the IC chip and the lead which is the electrode on the lead frame side. Wire bonding is performed.
【００１５】ボンディング終了後、ヒーターブロックと
収納トレー２の間に位置する徐冷ブロック（ヒータープ
レートからなる）７へリードフレームの搬送が行われる
ことになるが、通常ヒーターブロックはボンディング時
にはリードフレームに接触させており、搬送時にはリー
ドフレームとのクリアランスを得るために降下動作を行
う。このヒーターブロックの降下時にはリードフレーム
はヒーターブロックと非接触になり、ＩＣチップの温度
降下が発生するので、ホットエアー１０ａをノズル９ａ
を用いてＩＣチップ表面に噴射するなどして徐冷ブロッ
ク７へＩＣチップが到達するまでの温度降下を防止する
ことが望ましい。また、ホットエアーの噴射のタイミン
グはボンディング後にのみ行う。あるいはホットエアー
でなくても温度低下を防止するためであれば赤外線等を
ＩＣチップ表面に照射しても良い。After the bonding is completed, the lead frame is conveyed to a slow cooling block (made of a heater plate) 7 located between the heater block and the storage tray 2. Usually, the heater block is attached to the lead frame at the time of bonding. They are in contact with each other, and perform a lowering operation to obtain clearance with the lead frame during transport. When the heater block descends, the lead frame comes out of contact with the heater block, and the temperature of the IC chip drops.
It is desirable to prevent the temperature from dropping until the IC chip reaches the slow cooling block 7 by spraying it onto the surface of the IC chip using, for example. Hot air is injected only after bonding. Alternatively, the surface of the IC chip may be irradiated with infrared rays or the like if it is not hot air to prevent a temperature drop.
【００１６】この後リードフレームとリードフレームに
搭載された複数のＩＣチップはヒーター８ｃ，８ｄ，８
ｅでそれぞれ温度調整されている各徐冷ブロック７上に
順次搬送され、ＩＣチップの徐冷が行われる。徐冷ブロ
ックは図１で示すように複数の徐冷ブロック上に温度差
を設けたものである。徐冷ブロックとリードフレームの
間隔については、接触させても、非接触としても本発明
の目的は達成できるが、リードフレームと徐冷ブロック
とは若干のクリアランスを設け、非接触とすることが徐
冷ブロック間の温度差に起因する温度変化をより緩やか
なものにするためにも望ましい。実際のＩＣチップの温
度履歴はリードフレームの搬送タイミングとの組み合わ
せで決まり、例えばステップ状に搬送を行った場合、Ｉ
Ｃチップの図４で示されるような温度履歴１３が決定さ
れる。また、その際電極のダメージ防止に効果のあるボ
ンディング温度から室温＋５℃に至るまでの平均温度勾
配は−２．０℃／秒またはそれより緩やかにすることが
望ましいことが、表１に示すように本発明者らの評価に
より判明している。Thereafter, the lead frame and the plurality of IC chips mounted on the lead frame are connected to heaters 8c, 8d, 8
The IC chips are sequentially conveyed onto the respective slow cooling blocks 7 whose temperature is adjusted in step e, and the IC chips are gradually cooled. The slow cooling block is one in which a temperature difference is provided on a plurality of slow cooling blocks as shown in FIG. Regarding the interval between the slow cooling block and the lead frame, the object of the present invention can be achieved both in contact and in non-contact, but it is preferable to provide a slight clearance between the lead frame and the slow cooling block to make It is also desirable to make the temperature change caused by the temperature difference between the cold blocks gentler. The actual temperature history of the IC chip is determined by the combination with the lead frame transfer timing.
The temperature history 13 of the C chip as shown in FIG. 4 is determined. In addition, as shown in Table 1, it is desirable that the average temperature gradient from the bonding temperature that is effective in preventing electrode damage to room temperature + 5 ° C. be -2.0 ° C./sec or less. Have been found by the present inventors' evaluation.
【００１７】[0017]
【表１】 このように徐冷ブロックで十分に徐冷が行われた後、リ
ードフレームは収納トレーに収納される。[Table 1] After the annealing is sufficiently performed by the annealing block, the lead frame is stored in the storage tray.
【００１８】なお、本実施の形態では徐冷ブロックの温
度勾配は８ｃ〜８ｅに示されるような３本のヒーター等
を用いることで温度設定を行っており、また図１では徐
冷ブロックはヒーター毎に分割され３つからなるように
示されているが、ヒーターの本数と徐冷ブロックの数に
制限はなく、徐冷ブロック間の温度差を小さくするため
にさらに増やしても良い。また逆にヒーターや徐冷ブロ
ックは単一のものとし、徐冷ブロックの一部を冷却する
などして温度勾配を同一徐冷ブロック上に設定するよう
なものであっても当然良い。In the present embodiment, the temperature gradient of the slow cooling block is set by using three heaters as shown in 8c to 8e. In FIG. 1, the slow cooling block is a heater. Although the number of heaters and the number of slow cooling blocks are not limited, the number of heaters and the number of slow cooling blocks may be further increased in order to reduce the temperature difference between the slow cooling blocks. Conversely, a single heater or slow cooling block may be used, and a temperature gradient may be set on the same slow cooling block by cooling a part of the slow cooling block.
【００１９】また、本発明の目的はＩＣチップの徐冷で
あるから、ＩＣチップの徐冷と同時にリードフレームの
熱変形防止のためリードフレームの冷却を乾燥空気等で
行っても良く、本発明による効果を妨げるものではな
い。Since the object of the present invention is to gradually cool the IC chip, the lead frame may be cooled with dry air or the like at the same time as the IC chip is gradually cooled to prevent thermal deformation of the lead frame. It does not prevent the effect of
【００２０】なお、本実施の形態ではリードフレーム上
のＩＣチップの徐冷について説明を行ったが、本発明の
主旨はＩＣチップの徐冷であるから、金属製のリードフ
レームに限らず、例えばポリイミド樹脂に配線パターン
を施したフィルム状のものや、基盤上にＩＣチップが搭
載されたようなものであっても同様の効果が得られる。In this embodiment, the slow cooling of the IC chip on the lead frame has been described. However, since the gist of the present invention is the slow cooling of the IC chip, the present invention is not limited to the metal lead frame. The same effect can be obtained even in the case of a film in which a wiring pattern is applied to a polyimide resin, or in a case where an IC chip is mounted on a base.
【００２１】実施例１ 以下、本発明の実施例を示して第１の実施の形態を更に
説明する。 Embodiment 1 Hereinafter, the first embodiment will be further described by showing embodiments of the present invention.
【００２２】室温２５℃の環境下においてワイヤーボン
ディング前のリードフレームが収納されているトレーよ
り搬送方向の長さ１５０ｍｍ、幅５０ｍｍ、厚さ１２５
μｍである銅合金製のリードフレームとリードフレーム
にＡｇペーストを用いて搭載されたＩＣチップ（５．０
０ｍｍ□、厚さ３００μｍ）を幅５０ｍｍ、搬送方向の
長さ５０ｍｍのステンレス製の予熱ブロック上に搬送す
る。予熱ブロック表面は内蔵されたセラミックヒーター
によりＴｐ：１００℃に温度調整されている。なお、リ
ードフレーム１枚当たりには３つのＩＣチップが等間隔
で搭載されており、予熱、ボンディング、徐冷はステッ
プ状にＩＣチップ毎に行われる。At a room temperature of 25 ° C., the length in the transport direction is 150 mm, the width is 50 mm, and the thickness is 125 from the tray containing the lead frame before wire bonding.
μm copper alloy lead frame and an IC chip (5.0 mm) mounted on the lead frame using Ag paste.
(0 mm □, thickness 300 μm) is conveyed onto a stainless preheating block 50 mm wide and 50 mm long in the conveying direction. The surface of the preheating block is temperature-controlled to Tp: 100 ° C. by a built-in ceramic heater. Note that three IC chips are mounted at equal intervals on one lead frame, and preheating, bonding, and slow cooling are performed in a stepwise manner for each IC chip.
【００２３】予熱後、リードフレームは内蔵のセラミッ
クヒーターにより表面がＴｂ：２００℃に調整され、ス
テンレス製で長さ４０ｍｍ、幅４０ｍｍであるヒーター
ブロック上に搬送され、線径３０μｍの金線を用いてＩ
Ｃチップ上の電極とリードを結合するワイヤーボンディ
ングが圧着ボール径：５５μｍで行われる。このとき１
つのＩＣチップ当たりのワイヤー数は３００であり、１
ＩＣチップのボンディングが終了するまでの時間は２分
である。After preheating, the surface of the lead frame is adjusted to Tb: 200 ° C. by a built-in ceramic heater, transported on a stainless steel heater block having a length of 40 mm and a width of 40 mm, and using a gold wire having a wire diameter of 30 μm. I
Wire bonding for connecting the electrode and the lead on the C chip is performed with a compressed ball diameter of 55 μm. At this time 1
The number of wires per IC chip is 300,
The time until the bonding of the IC chip is completed is 2 minutes.
【００２４】ボンディング終了後、２００℃に加熱され
たホットエアーをノズルよりＩＣチップ表面に噴射し、
ボンディング済みのＩＣチップ表面温度をボンディング
温度に保ったまま、３つのブロックから構成されるステ
ンレス製の徐冷ブロック上へとリードフレームの搬送が
１ＩＣチップ分行われる。３つの各徐冷ブロックは搬送
方向の長さ５０ｍｍ、幅２０ｍｍと形状は同一のもので
あり、ブロックの幅をリードフレームの幅より３０ｍｍ
狭めることでＩＣチップの徐冷のみを行い、リードフレ
ーム周辺部分の変形を防止するようになっている。After the bonding is completed, hot air heated to 200 ° C. is injected from the nozzle onto the surface of the IC chip.
While maintaining the surface temperature of the bonded IC chip at the bonding temperature, the lead frame is transported by one IC chip onto a stainless steel slow cooling block composed of three blocks. Each of the three slow cooling blocks has the same shape as the length of 50 mm and the width of 20 mm in the transport direction, and the width of the block is 30 mm from the width of the lead frame.
The narrowing allows only slow cooling of the IC chip to prevent deformation around the lead frame.
【００２５】まず、１９０℃にブロック表面が加熱され
た第１の徐冷ブロック上にボンディング済みのＩＣチッ
プが搬送されるが、０．３ｍｍの間隙がリードフレーム
底面と徐冷ブロックの間に設けられているために、ＩＣ
チップの温度は緩やかな温度勾配をたどりながら１７０
℃程度まで降下する。その後第２の徐冷ブロックへＩＣ
チップは移動するが、ここでのブロックの表面温度は１
２０℃に設定されており、実際のＩＣチップの温度は緩
やかに降下しながら１００℃程度となる。さらに第３の
徐冷ブロック上に搬送されるが、第３の徐冷ブロックの
表面温度は６０℃であり、ＩＣチップの温度は４０℃程
度となる。以上の３ブロック上で徐冷が行われた後、収
納トレーへ搬送されるが、収納中或いは収納後にＩＣチ
ップは雰囲気温度近くまで冷却される。First, the bonded IC chip is transported onto the first annealing block whose surface is heated to 190 ° C., and a gap of 0.3 mm is provided between the bottom surface of the lead frame and the annealing block. IC
The temperature of the chip was 170 while following a gentle temperature gradient.
Decrease to about ° C. Then IC to the second slow cooling block
The chip moves, but the surface temperature of the block here is 1
The temperature is set at 20 ° C., and the actual temperature of the IC chip becomes about 100 ° C. while gradually decreasing. Further, the wafer is transported onto the third slow cooling block. The surface temperature of the third slow cooling block is 60 ° C., and the temperature of the IC chip is about 40 ° C. After the gradual cooling is performed on the above three blocks, the IC chip is conveyed to the storage tray. During or after storage, the IC chip is cooled to near the ambient temperature.
【００２６】また、徐冷ブロック間のリードフレームの
搬送は、ボンディング時間に合わせステップ状に行わ
れ、１つの徐冷ブロックに一つのＩＣチップがある時間
はボンディング時間と同じ２分とする。つまり本実施例
では１ＩＣチップ当たり３徐冷ブロック合計で６分の徐
冷時間があることになり、このときのボンディング温度
から室温＋５℃までの平均温度勾配は−０．４５℃／秒
となる。The transfer of the lead frame between the slow cooling blocks is performed stepwise in accordance with the bonding time, and the time during which one IC chip is present in one slow cooling block is set to 2 minutes, which is the same as the bonding time. That is, in this embodiment, there is a slow cooling time of 6 minutes in total for three slow cooling blocks per IC chip, and the average temperature gradient from the bonding temperature to the room temperature + 5 ° C. is −0.45 ° C./sec. .
【００２７】［第２の実施形態］図３を示し、本発明の
第２の実施の形態について説明する。トレー１からリー
ドフレーム３の搬送（搬送方向４）が行われ、予熱ブロ
ック５でリードフレーム及びＩＣチップの予熱が行われ
た後、ヒーターブロック６上でワイヤーボンディングが
行われ、ホットエアー１０ａを用いてボンディング直後
の搬送時のＩＣチップの温度低下防止が行われるまでは
第１の実施の形態と同じである。[Second Embodiment] FIG. 3 shows a second embodiment of the present invention. After the lead frame 3 is transferred from the tray 1 (in the transfer direction 4) and the lead frame and the IC chip are preheated in the preheating block 5, wire bonding is performed on the heater block 6 and hot air 10a is used. The process is the same as that of the first embodiment until the temperature of the IC chip is prevented from lowering at the time of transfer immediately after bonding.
【００２８】その後、リードフレームはヒーターブロッ
クと収納トレー２の間に位置する保温ブロック１１上に
搬送され、収納トレーへリードフレームを収納するまで
ＩＣチップの保温が行われる。このときリードフレーム
と保温ブロックは接触させても非接触としても良い。な
お保温ブロックの温度については、ヒーター８ｃ，８
ｄ，８ｅにより調整が行われるが、ボンディングの行わ
れるヒーターブロックと同じ温度かＩＣチップの急激な
温度降下が起きない程度、例えば第１の実施の形態で示
した最初の徐冷ブロックと同じ温度に低下させておく。Thereafter, the lead frame is transported onto the heat retaining block 11 located between the heater block and the storage tray 2, and the IC chip is kept warm until the lead frame is stored in the storage tray. At this time, the lead frame and the heat retaining block may be in contact or non-contact. In addition, about the temperature of the heat retention block, the heaters 8c and 8
The adjustment is performed by d and 8e, but the same temperature as that of the heater block where the bonding is performed, or to the extent that a rapid temperature drop of the IC chip does not occur, for example, the same temperature as that of the first slow cooling block shown in the first embodiment. To lower.
【００２９】保温ブロックでの保温後、リードフレーム
は収納トレーに収納されるが、保温ブロックと収納トレ
ーとの間に隙間がある場合には、そこでのＩＣチップの
温度低下も予想されるのでノズル９ｂからホットエアー
１０ｂを噴射して温度低下を防止することが効果的であ
る。After keeping the heat in the heat retaining block, the lead frame is stored in the storage tray. If there is a gap between the heat retaining block and the storage tray, the temperature of the IC chip is expected to decrease there. It is effective to prevent the temperature from dropping by injecting hot air 10b from 9b.
【００３０】収納トレーへ収納後、ＩＣチップの徐冷が
行われることになるが、本実施形態では複数の温度に設
定されたホットエアーをトレー内部に噴射することによ
り、徐冷を行う場合を説明する。通常、収納トレーはリ
ードフレームが収納されるにつれて図３で示されるよう
に下方向へ移動し、次のリードフレーム収納に備える。
そこで、図３に示すようにＺ軸方向の各位置にノズル９
ｃ，９ｄ，９ｅを設置し、複数の温度に設定されたホッ
トエアー１０ｃ，１０ｄ，１０ｅをそれぞれ平行に収納
トレー内部に噴射する。このときホットエアーの温度は
下方向に進むに従いつまりＺ０，Ｚ１，Ｚ２となるに従
って低くなるように設定する。つまり、実際の収納トレ
ー内部の雰囲気温度は図３に示したようにＺ軸位置が下
ほど低くなる。すなわち収納トレーがリードフレームを
収納し、下方向に移動するに従ってリードフレームに搭
載されたＩＣチップは徐冷されることになる。After the IC chips are stored in the storage tray, the IC chips are gradually cooled. In this embodiment, the case where the cooling is performed by injecting hot air set at a plurality of temperatures into the trays is considered. explain. Normally, the storage tray moves downward as shown in FIG. 3 as the lead frame is stored to prepare for the next lead frame storage.
Therefore, as shown in FIG. 3, the nozzle 9 is located at each position in the Z-axis direction.
c, 9d, and 9e are installed, and hot air 10c, 10d, and 10e set to a plurality of temperatures are respectively injected in parallel into the storage tray. At this time, the temperature of the hot air is set so as to decrease as it goes downward, that is, as it becomes Z0, Z1, Z2. That is, the actual ambient temperature inside the storage tray is lower as the Z-axis position is lower as shown in FIG. That is, as the storage tray stores the lead frame and moves downward, the IC chip mounted on the lead frame is gradually cooled.
【００３１】ところで第２の実施の形態ではヒーターブ
ロックから収納トレーへの搬送中に保温ブロックを設
け、ＩＣチップの温度降下を防止するという形態を説明
したが、収納トレーに収納されるまでのＩＣチップの急
激な温度降下を防止することが目的であるので、保温ブ
ロックのかわりにヒーターブロックと収納トレーの間に
ノズルを設置し、リードフレーム搬送中にＩＣチップ表
面にホットエアーを噴射しても良いし、赤外線をＩＣチ
ップ表面に照射することでＩＣチップの急激な温度降下
を防止しても良い。By the way, in the second embodiment, a mode has been described in which a heat retaining block is provided during transportation from the heater block to the storage tray to prevent the temperature of the IC chip from dropping. Since the purpose is to prevent a sharp drop in the temperature of the chip, a nozzle is installed between the heater block and the storage tray instead of the heat insulation block, and even if hot air is sprayed on the IC chip surface during lead frame transport. Irradiating the surface of the IC chip with infrared rays may prevent a rapid temperature drop of the IC chip.
【００３２】一方、前述の第１の実施の形態との大きな
違いは、第１の実施の形態が収納トレーへの搬送中にＩ
Ｃチップの徐冷を行うのに対し、第２の実施の形態は収
納トレーの中で徐冷を行うことである。第１の実施の形
態が１つのＩＣチップ当たりのワイヤー数が多いためボ
ンディング時間が長く、後続のＩＣチップのボンディン
グ中に徐冷がボンディング装置の処理能力の低下なく十
分に行われる場合に適し、第２の実施の形態は１つのＩ
Ｃチップ当たりのワイヤー数が少ないためにボンディン
グ時間が短く、第１の実施の形態が示すようにリードフ
レームの搬送中に徐冷を行おうとするとボンディング装
置の処理能力が犠牲となる場合に適する。On the other hand, a major difference from the first embodiment described above is that the first embodiment has
In contrast to the slow cooling of the C chip, the second embodiment is to slowly cool the chip inside the storage tray. The first embodiment is suitable when the bonding time is long because the number of wires per IC chip is large and the slow cooling is sufficiently performed during the bonding of the subsequent IC chip without lowering the processing capability of the bonding apparatus. In the second embodiment, one I
Since the number of wires per C chip is small, the bonding time is short, and as shown in the first embodiment, it is suitable for the case where an attempt is made to perform slow cooling during the transfer of the lead frame, thereby sacrificing the processing capability of the bonding apparatus.
【００３３】また、更に別の実施の形態としてＩＣチッ
プの保温をトレー全体をヒーター等で加熱することでト
レー収納後も行い、収納トレーにボンディング予定の全
リードフレームを収納後、恒温層等の温度調節のできる
環境下にボンディング済みのＩＣチップが収納されたト
レーを置き、トレーごと徐冷を行うのも本発明の目的を
達成するために有効的な手段である。In still another embodiment, the IC chips are kept warm by heating the entire tray with a heater or the like after the tray is stored. After all the lead frames to be bonded are stored in the storage tray, the IC chip is kept at a constant temperature layer or the like. It is also an effective means for achieving the object of the present invention to place a tray containing bonded IC chips in an environment where the temperature can be adjusted and slowly cool the entire tray.
【００３４】実施例２ 以下、本発明の実施例を示して第２の実施の形態を更に
説明する。 Embodiment 2 Hereinafter, the second embodiment will be further described with reference to embodiments of the present invention.
【００３５】室温２５℃の環境下においてワイヤーボン
ディング前のリードフレームが収納されているトレーよ
り搬送方向の長さ２００ｍｍ、幅３０ｍｍ、厚さ１５０
μｍである４２合金製のリードフレームとリードフレー
ムにＡｇペーストを用いて搭載されたＩＣチップ（２．
００ｍｍ□、厚さ４００μｍ）を搬送方向の長さ３０ｍ
ｍ、幅３０ｍｍのステンレス製の予熱ブロック上に搬送
する。予熱ブロック表面は内蔵されたセラミックヒータ
ーによりＴｐ：１００℃に温度調整されている。なお、
リードフレーム１枚当たりには１０個のＩＣチップが等
間隔で搭載されており、予熱、ボンディングはステップ
状に１ＩＣチップ毎に行われる。At a room temperature of 25 ° C., the length in the transport direction is 200 mm, the width is 30 mm, and the thickness is 150 from the tray in which the lead frame before wire bonding is stored.
μm 42 alloy lead frame and an IC chip mounted on the lead frame using Ag paste (2.
00mm □, thickness 400μm) 30m in the transport direction
m, and conveyed on a stainless steel preheating block having a width of 30 mm. The surface of the preheating block is temperature-controlled to Tp: 100 ° C. by a built-in ceramic heater. In addition,
Ten IC chips are mounted at equal intervals on one lead frame, and preheating and bonding are performed step by step for each IC chip.
【００３６】予熱後、リードフレームは内蔵のセラミッ
クヒーターにより表面がＴｂ：２００℃に調整され、ス
テンレス製で搬送方向の長さ４０ｍｍ、幅２０ｍｍであ
るヒーターブロック上に搬送され、線径３０μｍの金線
を用いてＩＣチップ上の電極とリードを結合するワイヤ
ーボンディングが圧着ボール径：５５μｍで行われる。
このとき１つのＩＣチップ当たりのワイヤー数は２０で
あり、１ＩＣのボンディングが終了するまでの時間は１
０秒である。After preheating, the surface of the lead frame is adjusted to Tb: 200 ° C. by a built-in ceramic heater, transported onto a heater block made of stainless steel and having a length of 40 mm and a width of 20 mm in the transport direction, and having a wire diameter of 30 μm. Wire bonding for connecting the electrode and the lead on the IC chip using a wire is performed with a compressed ball diameter of 55 μm.
At this time, the number of wires per IC chip is 20, and the time until the bonding of one IC is completed is one.
0 seconds.
【００３７】ボンディング終了後、ＩＣチップ表面に２
００℃に加熱されたホットエアーが噴射され、保温ブロ
ックにボンディング済みのＩＣチップが搬送される。After the bonding is completed, 2
Hot air heated to 00 ° C. is injected, and the bonded IC chip is transported to the heat retaining block.
【００３８】保温ブロックは１ブロックからなり搬送方
向の長さ２００ｍｍ、幅３０ｍｍのステンレス製であ
る。保温ブロックは３本のセラミックヒーターにより２
２０℃に一様に加熱されているが、実施例１と同様リー
ドフレーム底面と保温ブロックとの間には０．３ｍｍ程
度のクリアランスがあるため実際のＩＣチップの温度は
２００℃となる。１枚のリードフレームに搭載された全
ＩＣチップ（１０個）のボンディングが終了し、保温ブ
ロック上に全ＩＣチップが搬送された後、収納トレーに
リードフレームは収納されるが、保温ブロックと収納ト
レーの間で温度低下を防止するために２００℃に加熱さ
れたホットエアーをＩＣチップ表面に噴射する。The heat retaining block is made of stainless steel and has a length of 200 mm and a width of 30 mm in the transport direction. Insulation block is 2 with 3 ceramic heaters
Although it is uniformly heated to 20 ° C., the actual temperature of the IC chip is 200 ° C. because there is a clearance of about 0.3 mm between the bottom surface of the lead frame and the heat retaining block as in the first embodiment. After bonding of all the IC chips (10 pieces) mounted on one lead frame is completed and all the IC chips are transported on the heat retaining block, the lead frame is stored in the storage tray, but is stored in the heat retaining block. Hot air heated to 200 ° C. is sprayed onto the surface of the IC chip to prevent a temperature drop between the trays.
【００３９】収納トレーへリードフレームを収納後ＩＣ
チップの徐冷が行われるが、収納トレー後方に設置され
た４つのノズルから温度の違うホットエアーを噴射する
ことによって行われる。図７に詳細を示すが、ノズルは
Ｚ方向に等間隔に設置されており、その間隔は収納され
ているリードフレーム２ピッチ分とし、それぞれの温度
は２００℃、１５０℃、１００℃、５０℃とし、１つの
ノズルから噴射されるホットエアー２５ａ〜２５ｄを２
枚のリードフレームの隙間に通す。２６は収納トレーノ
移動方向を示す。すなわち、１つのノズルで２枚のリー
ドフレームを同時に加熱し、各リードフレームはリード
フレームが収納トレーに収納される周期が１００秒（１
０秒×１０ＩＣチップ）となるため、同じ温度のホット
エアーに２００秒ずつさらされることになる。従って、
１枚のリードフレームならびにリードフレームに搭載さ
れたＩＣチップが４つのノズルから噴射されるホットエ
アーにさらされる合計時間は８００秒となり、ボンディ
ング温度から室温＋５℃以下になるまでの平均温度勾配
は−０．２℃／秒程度になる。IC after storing lead frame in storage tray
Slow cooling of the chips is performed by injecting hot air having different temperatures from four nozzles installed behind the storage tray. As shown in detail in FIG. 7, the nozzles are installed at equal intervals in the Z direction, and the interval is set to two pitches of the accommodated lead frame. And the hot air 25a to 25d injected from one nozzle is 2
Through the gap between the lead frames. Reference numeral 26 indicates the direction in which the storage tray moves. That is, two lead frames are simultaneously heated by one nozzle, and each lead frame has a cycle in which the lead frames are stored in the storage tray for 100 seconds (1 second).
0 seconds × 10 IC chips), so that they are exposed to hot air at the same temperature for 200 seconds. Therefore,
The total exposure time of one lead frame and the IC chip mounted on the lead frame to the hot air jetted from the four nozzles is 800 seconds, and the average temperature gradient from the bonding temperature to room temperature + 5 ° C. or less is −. It is about 0.2 ° C./sec.
【００４０】[0040]
【発明の効果】以上の様な本発明によれば、半導体素子
のの徐冷を行い、電極接合部においての熱応力を緩和す
ることで、層間膜の剥離やシリコンでのクラックなどの
電極のダメージを防止することができ、それにより層間
膜の剥離やシリコンでのクラックを防止することが可能
となり、電極を構成する層間の高い接着信頼性を得るこ
とができる。According to the present invention as described above, the semiconductor element is gradually cooled to relieve the thermal stress at the electrode joint, thereby removing the interlayer film and cracking the silicon. Damage can be prevented, whereby peeling of an interlayer film and cracking in silicon can be prevented, and high adhesion reliability between layers constituting electrodes can be obtained.
【００４１】また、本発明によれば、電極にダメージを
与えないボンディングが可能となるため、電極アルミニ
ウム膜厚の薄いＩＣチップへのボンディングが可能とな
る。Further, according to the present invention, since bonding without damaging the electrodes can be performed, bonding to an IC chip having a thin electrode aluminum film can be performed.
【図１】本発明の第１の実施の形態を示す説明図であ
る。FIG. 1 is an explanatory diagram showing a first embodiment of the present invention.
【図２】従来のボンディング工程を示す説明図である。FIG. 2 is an explanatory view showing a conventional bonding step.
【図３】本発明の第２の実施の形態を示す説明図であ
る。FIG. 3 is an explanatory diagram showing a second embodiment of the present invention.
【図４】ＩＣチップの温度履歴を示す説明図である。FIG. 4 is an explanatory diagram showing a temperature history of an IC chip.
【図５】リードフレームへのＩＣチップの搭載方法を示
す説明図である。FIG. 5 is an explanatory diagram showing a method of mounting an IC chip on a lead frame.
【図６】圧着ボールの電極への接合状態を示す断面図で
ある。FIG. 6 is a cross-sectional view showing a bonding state of a pressure-bonded ball to an electrode.
【図７】実施例２において収納トレーに収納されている
リードフレームとホットエアーの位置関係を示す説明図
である。FIG. 7 is an explanatory diagram illustrating a positional relationship between a lead frame stored in a storage tray and hot air according to the second embodiment.
１ トレー ２ 収納トレー ３ リードフレーム ４ リードフレーム搬送方向 ５ 予熱ブロック ６ ヒーターブロック ７ 徐冷ブロック ８ａ〜８ｅ ヒーター ９ａ〜９ｅ ノズル １０ａ〜１０ｅ ホットエアー １１ 保温ブロック １２ 自然冷却によるＩＣチップの温度履歴 １３ 徐冷を行うことによるＩＣチップの温度履歴 １４ ＩＣチップ １５ リードフレーム １６ ワイヤー １７ 圧着ボール １８ａ，１８ｂ アルミニウム膜 １９ バリア層 ２０ 層間膜 ２１ａ〜２１ｂ 圧着ボールとアルミニウム膜間の熱
応力 ２２ａ〜２２ｂ アルミニウム膜とバリア層間での熱
応力 ２３ａ〜２３ｂ バリア層と層間膜間での熱応力 ２４ リードフレーム ２５ａ〜２５ｄ ホットエアー ２６ 収納トレー移動方向DESCRIPTION OF SYMBOLS 1 Tray 2 Storage tray 3 Lead frame 4 Lead frame conveyance direction 5 Preheating block 6 Heater block 7 Slow cooling block 8a-8e Heater 9a-9e Nozzle 10a-10e Hot air 11 Heat insulation block 12 Temperature history of IC chip by natural cooling 13 Slow Temperature history of IC chip due to cooling 14 IC chip 15 Lead frame 16 Wire 17 Crimping ball 18a, 18b Aluminum film 19 Barrier layer 20 Interlayer film 21a-21b Thermal stress between crimping ball and aluminum film 22a-22b Aluminum film Thermal stress between barrier layers 23a-23b Thermal stress between barrier layer and interlayer film 24 Lead frame 25a-25d Hot air 26 Storage tray moving direction
Claims (8)
電気的接続のために用いられる部材を含む半導体装置を
製造する方法において、前記半導体素子の電極と前記外
部との電気的接続のために用いられる部材とを加熱下で
ボンディングする工程と、該ボンディング工程後に前記
半導体素子を徐冷する工程とを有することを特徴とする
半導体装置の製造方法。In a method of manufacturing a semiconductor device including a semiconductor element and a member used for electrical connection between the semiconductor element and the outside, a method for manufacturing an electrical connection between an electrode of the semiconductor element and the outside is provided. A method for manufacturing a semiconductor device, comprising: a step of bonding a member to be used under heating; and a step of gradually cooling the semiconductor element after the bonding step.
から室温＋５℃までの平均温度勾配を−２．０℃／秒ま
たはそれより緩やかにすることを特徴とする、請求項１
記載の半導体装置の製造方法。2. The method according to claim 1, wherein an average temperature gradient from the bonding temperature to room temperature + 5 ° C. in the annealing step is set to −2.0 ° C./sec or less.
The manufacturing method of the semiconductor device described in the above.
工程を行うことを特徴とする、請求項１〜２のいずれか
記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein said slow cooling step is performed subsequent to said bonding step.
て行うことを特徴とする、請求項３記載の半導体装置の
製造方法。4. The method for manufacturing a semiconductor device according to claim 3, wherein said slow cooling step is performed using a heater plate.
を行い、該保温工程に続いて前記徐冷工程を行うことを
特徴とする、請求項１〜２のいずれか記載の半導体装置
の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein a heat retaining step is performed after the bonding step, and the slow cooling step is performed after the heat retaining step.
て行うことを特徴とする、請求項４記載の半導体装置の
製造方法。6. The method for manufacturing a semiconductor device according to claim 4, wherein the heat retaining step is performed using a heater plate.
特徴とする、請求項６記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein said slow cooling step is performed in a storage means.
て行うことを特徴とする、請求項７記載の半導体装置の
製造方法。8. The method for manufacturing a semiconductor device according to claim 7, wherein said slow cooling step is performed by using hot air injection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33217297A JP3055511B2 (en) | 1997-12-02 | 1997-12-02 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33217297A JP3055511B2 (en) | 1997-12-02 | 1997-12-02 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11163025A true JPH11163025A (en) | 1999-06-18 |
| JP3055511B2 JP3055511B2 (en) | 2000-06-26 |
Family
ID=18251973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33217297A Expired - Fee Related JP3055511B2 (en) | 1997-12-02 | 1997-12-02 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3055511B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7017636B2 (en) | 2002-03-22 | 2006-03-28 | Seiko Epson Corporation | Apparatus for manufacturing an electronic device, method of manufacturing an electronic device, and program for manufacturing an electronic device |
| JP2013008758A (en) * | 2011-06-23 | 2013-01-10 | Fuji Electric Co Ltd | Method of manufacturing semiconductor device |
| JP2013089763A (en) * | 2011-10-18 | 2013-05-13 | Fuji Electric Co Ltd | Power semiconductor device and method of manufacturing the same |
| JP2022023496A (en) * | 2020-07-27 | 2022-02-08 | キヤノンマシナリー株式会社 | Conveying device, conveying method, die bonder, and bonding method |
-
1997
- 1997-12-02 JP JP33217297A patent/JP3055511B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7017636B2 (en) | 2002-03-22 | 2006-03-28 | Seiko Epson Corporation | Apparatus for manufacturing an electronic device, method of manufacturing an electronic device, and program for manufacturing an electronic device |
| US7410826B2 (en) | 2002-03-22 | 2008-08-12 | Seiko Epson Corporation | Apparatus for manufacturing an electronic device, method of manufacturing an electronic device, and program for manufacturing an electronic device |
| JP2013008758A (en) * | 2011-06-23 | 2013-01-10 | Fuji Electric Co Ltd | Method of manufacturing semiconductor device |
| JP2013089763A (en) * | 2011-10-18 | 2013-05-13 | Fuji Electric Co Ltd | Power semiconductor device and method of manufacturing the same |
| JP2022023496A (en) * | 2020-07-27 | 2022-02-08 | キヤノンマシナリー株式会社 | Conveying device, conveying method, die bonder, and bonding method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3055511B2 (en) | 2000-06-26 |
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