JPH0621312A - Manufacture of package - Google Patents
Manufacture of packageInfo
- Publication number
- JPH0621312A JPH0621312A JP4177286A JP17728692A JPH0621312A JP H0621312 A JPH0621312 A JP H0621312A JP 4177286 A JP4177286 A JP 4177286A JP 17728692 A JP17728692 A JP 17728692A JP H0621312 A JPH0621312 A JP H0621312A
- Authority
- JP
- Japan
- Prior art keywords
- pins
- package
- brazing material
- pin
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，ＰＧＡ（Ｐｉｎ Ｇｒ
ｉｄ Ａｌｌａｙ）タイプのセラミックパッケージ等の
製造方法に関する。The present invention relates to a PGA (Pin Gr)
The present invention relates to a method for manufacturing a ceramic package or the like of an id Array type.
【０００２】近年，半導体デバイスの高集積化にともな
い，ピン数の多いＰＧＡタイプのパッケージが多く使用
され，信頼性の高い開発技術が必要とされている。In recent years, with the high integration of semiconductor devices, PGA type packages with a large number of pins are often used, and a highly reliable development technique is required.
【０００３】[0003]
【従来の技術】図４，図５は従来例の説明図である。図
において，１はパッケージ，２はセラミック基板，３は
Ｎｉピン，12はプリント基板である。2. Description of the Related Art FIGS. 4 and 5 are explanatory views of a conventional example. In the figure, 1 is a package, 2 is a ceramic substrate, 3 is a Ni pin, and 12 is a printed circuit board.
【０００４】従来，ＰＧＡタイプのセラミックパッケー
ジにおいて，図４に示すように，パッケージ１をプリン
ト基板12に半田付けして，パッケージ内のＬＳＩチップ
とプリント基板の配線接続を行なうピンの材質には，Ｋ
ＯＶＡＲ（コバール）が多く用いられてきた。Conventionally, in a PGA type ceramic package, as shown in FIG. 4, when the package 1 is soldered to the printed board 12, the material of the pins for connecting the wiring between the LSI chip in the package and the printed board is as follows. K
OVAR (Kovar) has been widely used.
【０００５】しかし，表面実装されるプリント基板12と
パッケージ１との熱伝導率（ＮｉはＫＯＶＥＲの５倍程
度）の差が問題となる多ピン，微細ピッチの最近のパッ
ケージでは，しばしばニッケル（Ｎｉ）ピン３が使用さ
れる。However, in a recent multi-pin, fine-pitch package in which the difference in thermal conductivity between the surface-mounted printed circuit board 12 and the package 1 (Ni is about 5 times KOVER) is a problem, nickel (Ni) is often used. ) Pin 3 is used.
【０００６】[0006]
【発明が解決しようとする課題】しかし，Ｎｉピン３を
使用した場合には，次のような問題が発生する。図５
（ａ）に示すように，Ｎｉピン３のロー付けは，一般に
800〜900 ℃で行なわれるが, その際，図５（ｂ）に示
すようにＮｉピン３の頭部から軸方向にロー材５が這い
上がり, そのため, セラミック基板２とＮｉピン３の接
合部のロー材５が不足する。However, when the Ni pin 3 is used, the following problems occur. Figure 5
As shown in (a), brazing of the Ni pin 3 is generally performed.
It is carried out at 800 to 900 ° C. At that time, the brazing material 5 crawls from the head of the Ni pin 3 in the axial direction as shown in Fig. 5 (b). Lack of brazing material 5.
【０００７】その対策として, 図５（ｃ）に示すよう
に，ロー材５の量を多くすると, ロー付けするロー材５
のセラミック基板２との境界部分で, セラミック基板２
にクラックが発生してしまう。As a countermeasure, as shown in FIG. 5 (c), when the amount of the brazing material 5 is increased, the brazing material 5 to be brazed is increased.
At the boundary with the ceramic substrate 2 of
Will crack.
【０００８】本発明は, Ｎｉピン３等のセラミック基板
２への半田付けにおいて，Ｎｉピン３へのロー材の這い
上がり防止し，高品質のセラミック基板２を得ることを
目的とする。It is an object of the present invention to obtain a high quality ceramic substrate 2 by preventing the brazing material from creeping up onto the Ni pin 3 when soldering the Ni pin 3 or the like to the ceramic substrate 2.
【０００９】[0009]
【課題を解決するための手段】図１は本発明の原理説明
図であり，パッケージへ装填するＮｉピン, 或いは，Ｎ
ｉめっきＭｏスタッドの製造フローである。図２は本発
明実施前後のＮｉ材表面の顕微鏡で観察した状態のスケ
ッチ図である。FIG. 1 is a diagram for explaining the principle of the present invention, in which a Ni pin or N loaded in a package is used.
It is a manufacturing flow of i plating Mo stud. FIG. 2 is a sketch diagram of the state of the Ni material surface observed before and after the present invention with a microscope.
【００１０】図において，１はパッケージ，２はセラミ
ック基板，３はＮｉピン，４はスタッド，５はロー材，
６は底板，７は放熱フィン，８はキャップ，９はチッ
プ，10はワイヤ, 11はリードである。In the figure, 1 is a package, 2 is a ceramic substrate, 3 is a Ni pin, 4 is a stud, 5 is a brazing material,
6 is a bottom plate, 7 is a radiation fin, 8 is a cap, 9 is a chip, 10 is a wire, and 11 is a lead.
【００１１】Ｎｉピン３へのロー材５の這い上がり防止
方法として，ネールヘッドピン，ストレートピン等をＮ
ｉ材よりＮｉピン３に成形後，水素雰囲気中で 900〜95
0 ℃の熱処理を行なってから, Ｎｉピン３にロウ材５を
付け，セラミック基板２にロウ付けをして，ＰＧＡタイ
プのセラミックパッケージが完成する。As a method of preventing the brazing material 5 from creeping up onto the Ni pin 3, nail head pins, straight pins, etc.
900 ~ 95 in hydrogen atmosphere after molding from i material to Ni pin 3
After heat treatment at 0 ° C., the brazing material 5 is attached to the Ni pins 3 and the ceramic substrate 2 is brazed to complete a PGA type ceramic package.
【００１２】すなわち，本発明の目的は，パッケージ１
のセラミック基板２に装填するＮｉピン３の製造に際
し, 図１（ａ）の製造フローに示すように，該Ｎｉピン
３を成形する工程と,成形された該Ｎｉピン３を熱処理
する工程と，熱処理された該Ｎｉピン３を, 該セラミッ
ク基板２にロー材５を用いてロー付けする工程とを含む
ことにより，或いは, パッケージ１のセラミック基板２
に装填するスタッド４の製造に際し, 図１（ｂ）の製造
フローに示すように，該スタッド４であるＭｏ素材を成
形する工程と,成形された該スタッド４をＮｉめっきす
る工程と，Ｎｉめっきされた該スタッド４を熱処理する
工程と，熱処理された該スタッド４を, 該セラミック基
板２にロー材５を用いてロー付けする工程とを含むこと
により，そして，前記熱処理は, Ｎｉピン３，スタッド
４，両方とも，還元雰囲気中，900 〜 950℃で行なわれ
ることにより達成される。That is, the object of the present invention is to provide a package 1
When manufacturing the Ni pin 3 to be loaded on the ceramic substrate 2 of FIG. 1, as shown in the manufacturing flow of FIG. 1A, a step of molding the Ni pin 3, a step of heat-treating the molded Ni pin 3, A step of brazing the heat-treated Ni pin 3 to the ceramic substrate 2 by using a brazing material 5, or the ceramic substrate 2 of the package 1.
As shown in the manufacturing flow of FIG. 1 (b), when manufacturing the stud 4 to be loaded into the stud 4, a step of forming the Mo material that is the stud 4, a step of Ni-plating the formed stud 4, and a Ni-plating step. The heat treatment of the heat treated stud 4 and the step of brazing the heat treated stud 4 to the ceramic substrate 2 using a brazing material 5, and the heat treatment includes the Ni pin 3, This can be achieved by performing both studs 4 and 900 in a reducing atmosphere at 900 to 950 ° C.
【００１３】[0013]
【作用】本発明においては，Ｎｉピン３やＮｉめっきＭ
ｏスタッド４等のＮｉ材を成形後に，水素を含む還元雰
囲気中において熱処理する事により，図２に示すよう
に，Ｎｉ材の表面が非常に滑らかとなり，凹凸がなくな
り，また，熱処理によりＮｉ材がロー材５との反応を阻
害し，ロー材５の這い上がりが生じにくくなる。In the present invention, the Ni pin 3 and the Ni plating M are used.
By heat treating the Ni material such as o stud 4 in a reducing atmosphere containing hydrogen as shown in FIG. 2, the surface of the Ni material becomes very smooth and has no irregularities. Inhibits the reaction with the brazing material 5 and makes it difficult for the brazing material 5 to creep up.
【００１４】[0014]
【実施例】図３は本発明の第２の実施例の説明図であ
る。図において，１はパッケージ，２はセラミック基
板，４はスタッド，５はロー材，６は底板，７は放熱フ
ィン，８はキャップ，９はチップ，10はワイヤ, 11はリ
ードである。FIG. 3 is an explanatory view of the second embodiment of the present invention. In the figure, 1 is a package, 2 is a ceramic substrate, 4 is a stud, 5 is a brazing material, 6 is a bottom plate, 7 is a radiation fin, 8 is a cap, 9 is a chip, 10 is a wire, and 11 is a lead.
【００１５】本発明の第１の実施例として，パッケージ
へロー付けするピンの製造について説明する。Ｎｉ材を
図４に示したようなネールヘッド型のＮｉピン３，或い
はストレートピンに成形加工する。その時ピン軸の表面
は図２（ａ）に示すように，数μｍ程度の皺状の凹凸面
となっている。As a first embodiment of the present invention, the manufacture of pins to be brazed to a package will be described. The Ni material is formed into a nail head type Ni pin 3 or a straight pin as shown in FIG. At that time, the surface of the pin shaft is a wrinkled uneven surface of about several μm, as shown in FIG.
【００１６】このＮｉピン３をコンベア式の炉にいれ，
水素１に対して窒素１〜３の還元雰囲気中において，90
0 〜950 ℃で熱処理する。単体のＮｉピンの熱処理時間
は凡そ１時間である。Put the Ni pin 3 in a conveyor type furnace,
90% in a reducing atmosphere of 1 to 3 nitrogen and 1 to 3 nitrogen
Heat treatment is performed at 0 to 950 ° C. The heat treatment time for a single Ni pin is about 1 hour.
【００１７】熱処理すると，Ｎｉピン３の表面は，図２
（ｂ）に示すように，１μｍ以下の梨地面となり，熱処
理前に比べて非常に滑らかな面となっている。銅（Ｃ
ｕ）２８％，銀（Ａｇ）７２％からなるＢＡｇ−８ロー
材５を塗布し，ＰＧＡパッケージ用のセラミック基板２
に格子状に数百本のピンを 800〜900 ℃でロー付けし
て, ＰＧＡパッケージを製作する。After the heat treatment, the surface of the Ni pin 3 is shown in FIG.
As shown in (b), the textured surface is 1 μm or less, which is a very smooth surface compared to before the heat treatment. Copper (C
u) A BAg-8 brazing material 5 composed of 28% and silver (Ag) 72% is applied, and a ceramic substrate 2 for a PGA package 2
A few hundred pins are brazed in a grid at 800-900 ° C to make a PGA package.
【００１８】本発明の第２の実施例として，パッケージ
へフィンをロー付けするためのＮｉめっきＭｏスタッド
４の製造について説明する。高出力半導体素子では，放
熱のため，図３（ａ）に示すような多層の放熱フィン７
をパッケージ１のセラミック基板２に，底板６を介して
装着する。装着のため，底板６のスタッド４にロー材５
を付け，放熱フィン７をロー付けする際，図３（ｂ）に
示すように，ロー材の這い上がりが生じて，放熱フィン
７の固定が不完全なものとなり，放熱効果が低減する。
そのため，スタッド４を成形後，第一の実施例のＮｉピ
ン３と同様な条件で，コンベア炉内で熱処理してから使
用する。これにより，ロー材５の這い上がりが防止さ
れ。放熱フィン７の放熱効果も所望の値に達することが
できた。As a second embodiment of the present invention, the production of the Ni-plated Mo stud 4 for brazing the fin to the package will be described. In a high-power semiconductor device, for heat dissipation, a multilayer heat dissipation fin 7 as shown in FIG.
Is mounted on the ceramic substrate 2 of the package 1 via the bottom plate 6. For mounting, brazing material 5 on stud 4 of bottom plate 6
When the heat radiation fins 7 are brazed to each other, as shown in FIG. 3B, the brazing material creeps up, and the heat radiation fins 7 are imperfectly fixed, and the heat radiation effect is reduced.
Therefore, after forming the stud 4, the stud 4 is used after being heat-treated in the conveyor furnace under the same conditions as the Ni pin 3 of the first embodiment. This prevents the brazing material 5 from climbing up. The heat radiation effect of the heat radiation fin 7 could reach a desired value.
【００１９】[0019]
【発明の効果】以上説明したように，セラミックパッケ
ージに装填するＮｉ材のピン或いはフィン止め具を成形
後本発明の如く熱処理すれば，Ｎｉ材の表面が非常に滑
らかとなり，ロウ材の這い上がりが防止される。As described above, when the Ni material pins or fin stoppers to be loaded into the ceramic package are molded and then heat treated as in the present invention, the surface of the Ni material becomes very smooth and the brazing material climbs. Is prevented.
【００２０】その結果，ロー材の多いところに発生する
Ｎｉめっきや拡散工程での膨れ防止でき，またピンのロ
ー材を半分以下に低減でき，パッケージの歩留り上昇，
品質向上に寄与するところが大きい。As a result, it is possible to prevent Ni plating that occurs in a lot of brazing material and swelling in the diffusion process, reduce the brazing material of the pin to less than half, and increase the package yield,
It greatly contributes to quality improvement.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明実施前後のＮｉ材表面状態FIG. 2 Surface condition of Ni material before and after the present invention
【図３】 本発明の第２の実施例の説明図FIG. 3 is an explanatory diagram of a second embodiment of the present invention.
【図４】 従来例の説明図（その１）FIG. 4 is an explanatory diagram of a conventional example (No. 1)
【図５】 従来例の説明図（その２）FIG. 5 is an explanatory diagram of a conventional example (No. 2)
１はパッケージ ２はセラミック基板 ３はＮｉピン ４はスタッド ５はロー材 ６は底板 ７は放熱フィン ８はキャップ ９はチップ 10はワイヤ 11はリード 1 is a package 2 is a ceramic substrate 3 is a Ni pin 4 is a stud 5 is a brazing material 6 is a bottom plate 7 is a radiation fin 8 is a cap 9 is a chip 10 is a wire 11 is a lead
Claims (3)
装填するニッケル（Ｎｉ）ピン(3) の製造に際し, 該Ｎｉピン(3) を成形する工程と, 成形された該Ｎｉピン(3) を熱処理する工程と， 熱処理された該Ｎｉピン(3) を, 該セラミック基板
(2) にロー材(5) を用いてロー付けする工程とを含むこ
とを特徴とするパッケージの製造方法。1. A step of molding the nickel (Ni) pin (3) to be loaded on the ceramic substrate (2) of the package (1), and a step of molding the nickel pin (3). ) Is heat-treated, and the heat-treated Ni pin (3) is attached to the ceramic substrate.
A method of manufacturing a package, comprising the step (2) of brazing with the brazing material (5).
装填するスタッド(4) の製造に際し, 該スタッド(4) であるモリブデン（Ｍｏ）素材を成形す
る工程と, 成形された該スタッド(4) をＮｉめっきする工程と， Ｎｉめっきされた該スタッド(4) を熱処理する工程と， 熱処理された該スタッド(4) を, 該セラミック基板
(2) にロー材(5) を用いてロー付けする工程とを含むこ
とを特徴とするパッケージの製造方法。2. A step of forming a molybdenum (Mo) material, which is the stud (4), in the production of the stud (4) to be loaded on the ceramic substrate (2) of the package (1), and the formed stud ( 4) is Ni-plated, the Ni-plated stud (4) is heat treated, and the heat-treated stud (4) is
A method of manufacturing a package, comprising the step (2) of brazing with the brazing material (5).
(4) の熱処理は, 還元雰囲気中，900 〜 950℃で行なわ
れることを特徴とする請求項１或いは２記載のパッケー
ジの製造方法。3. The Ni pin (3) or stud
The package manufacturing method according to claim 1 or 2, wherein the heat treatment (4) is performed at 900 to 950 ° C in a reducing atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4177286A JP3049948B2 (en) | 1992-07-06 | 1992-07-06 | Package manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4177286A JP3049948B2 (en) | 1992-07-06 | 1992-07-06 | Package manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0621312A true JPH0621312A (en) | 1994-01-28 |
| JP3049948B2 JP3049948B2 (en) | 2000-06-05 |
Family
ID=16028376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4177286A Expired - Fee Related JP3049948B2 (en) | 1992-07-06 | 1992-07-06 | Package manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3049948B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217341A (en) * | 2000-02-03 | 2001-08-10 | Ngk Spark Plug Co Ltd | Wiring board with lead pin |
| US6555757B2 (en) | 2000-04-10 | 2003-04-29 | Ngk Spark Plug Co., Ltd. | Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions |
| US6648211B2 (en) | 2000-10-13 | 2003-11-18 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6660946B2 (en) | 2000-04-10 | 2003-12-09 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6960729B2 (en) | 2001-07-27 | 2005-11-01 | Ngk Spark Plug Co., Ltd. | Upright-pin-joined resin substrate, method of producing the substrate, pins, and method of producing the pins |
-
1992
- 1992-07-06 JP JP4177286A patent/JP3049948B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217341A (en) * | 2000-02-03 | 2001-08-10 | Ngk Spark Plug Co Ltd | Wiring board with lead pin |
| US6555757B2 (en) | 2000-04-10 | 2003-04-29 | Ngk Spark Plug Co., Ltd. | Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions |
| US6660946B2 (en) | 2000-04-10 | 2003-12-09 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6648211B2 (en) | 2000-10-13 | 2003-11-18 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6960729B2 (en) | 2001-07-27 | 2005-11-01 | Ngk Spark Plug Co., Ltd. | Upright-pin-joined resin substrate, method of producing the substrate, pins, and method of producing the pins |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3049948B2 (en) | 2000-06-05 |
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