JPS59198726A - Manufacture of mic(microwave) device - Google Patents

Manufacture of mic(microwave) device

Info

Publication number
JPS59198726A
JPS59198726A JP58073206A JP7320683A JPS59198726A JP S59198726 A JPS59198726 A JP S59198726A JP 58073206 A JP58073206 A JP 58073206A JP 7320683 A JP7320683 A JP 7320683A JP S59198726 A JPS59198726 A JP S59198726A
Authority
JP
Japan
Prior art keywords
metal carrier
mic
circuit
alloy
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58073206A
Other languages
Japanese (ja)
Inventor
Norio Yabe
谷辺　範夫
Toshio Takahara
高原　寿夫
Hiromi Kikuchi
菊地　広美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58073206A priority Critical patent/JPS59198726A/en
Publication of JPS59198726A publication Critical patent/JPS59198726A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PURPOSE:To reduce thermal stress, and to reduce the warps of an MIC circuit and a metal carrier after the junction-cooling process is completed by a method wherein the metal carrier is cooled, while a heated high temperature block is put on the MIC circuit to hold the circuit at a high temperature. CONSTITUTION:A metal carrier 5 is heated at a temperature higher than the fusing point (280 deg.C) of an Au-Sn alloy 6 to be used as a brazing material. Such heating of the metal carrier 5 is performed on a heating pedestal 8 using a heater 7, and moreover the heating-junction process is performed in a nitrogen atmosphere to prevent the Au-Sn alloy 6 from oxidation. After then, at the point in time when the Au-Sn alloy 6 is molten, an MIC circuit 1 is put thereon, junction is performed, and at the cooling process thereof, the metal carrier 5 is put on a heat dissipating pedestal 9 to be cooled, the MIC circuit 1 having a small thermal expansion coefficient is heated using a heated block 10, and when the Au-Sn alloy 6 is to be hardened, the temperature of the MIC circuit 1 (a dielectric substrate 2) is made as to be held high, and the temperature of the metal carrier 5 is made so as to be held low.

Description

【発明の詳細な説明】 （］）発明の技術分野 本発明は、ＭＩＣ装置の製造方法に係シ、特にＭＩＣ回
路とこれを搭載するメタルキャリアとのロー付け、若し
くはハンダ付けによる接合の冷却工程に関する。[Detailed Description of the Invention] (]) Technical Field of the Invention The present invention relates to a method for manufacturing an MIC device, and in particular to a cooling process for joining a MIC circuit and a metal carrier on which it is mounted by brazing or soldering. Regarding.

（２）技術の背景 Ｍ　Ｉ　Ｃ回路は、誘電体基板の一表面にマイクロスト
リップ・ライン及び必要な高周波回路を配し、一方裏面
には接地導体を形成した、マイクロ波、ミリ波等の高周
波回路である。また、斯かるＭＩｃ回路をメタルキャリ
アに搭載してＭＩＣ装置を梼成し、所定の筐体に設置し
ている。(2) Background of the technology MIC circuits are high-frequency, microwave, millimeter-wave, etc. It is a circuit. Moreover, such an MIc circuit is mounted on a metal carrier to form an MIC device, and the MIC device is installed in a predetermined housing.

上記ｉｓ’ｉ　Ｉ　Ｃ回路は、セラミック等の硬質の基
板を用いるもので、ここに応力が加ることは、基板の機
械強度からみて好ましくない。また上述の如＜ＭＩＣ回
路のメタルキャリアとの接合面には、接地導体が形成さ
れておシ、装置の特性上両者の接合が均一で且つ密に行
なわれる必要がある。従って、特性に優れ、信頼性の高
いＭＩＣ装置を製造するためには、十分に注意を支払い
、ＭＩＣ回路とメタルキャリアとの接合を行う必要があ
る。The above-mentioned is'i IC circuit uses a hard substrate made of ceramic or the like, and it is not preferable from the viewpoint of the mechanical strength of the substrate that stress is applied thereto. Further, as mentioned above, a ground conductor is formed on the surface of the MIC circuit to be bonded to the metal carrier, and due to the characteristics of the device, it is necessary that the bonding between the two be uniform and dense. Therefore, in order to manufacture a highly reliable MIC device with excellent characteristics, it is necessary to pay sufficient attention to bonding the MIC circuit and the metal carrier.

（３）従来技術と問題点 通常、上記ＭＩＣ回路で用いられる誘電体基板は、アル
ミナセラミック、サファイア、フェライト等から成り、
またメタルキャリアとしては、放熱特性に優れた銅、銅
合金、及びアルミニューム等の材料が用いられる。両者
を接合するロー材としては（Ａｕ−８ｎ　）　、　（Ａ
ｕ　−Ｇｅ　）　ｔ　（Ａｕ−３ｉ）合金、またノ・ン
ダ材としては（Ｓｎ　−Ｐｂ　）　＝　（Ｉ　ｎ　−Ａ
ｇ　−Ｐｂ　）合金が使用される。(3) Prior art and problems Usually, the dielectric substrate used in the above MIC circuit is made of alumina ceramic, sapphire, ferrite, etc.
Further, as the metal carrier, materials such as copper, copper alloy, and aluminum, which have excellent heat dissipation properties, are used. As brazing materials for joining both, (Au-8n) and (A
u -Ge ) t (Au-3i) alloy, and as a non-onda material (Sn -Pb) = (I n -A
g-Pb) alloy is used.

とこで、上記誘電体基板の熱膨率が、上記メタル・キャ
リアの約１／３〜１／４程度であるため、上記接合材の
硬化時（冷却工程時）に、周知のペイメタル現象でＭＩ
Ｃ回路及びメタルキャリアに反りを生ずることとなる。By the way, since the coefficient of thermal expansion of the dielectric substrate is about 1/3 to 1/4 of that of the metal carrier, when the bonding material is cured (during the cooling process), MI due to the well-known pay metal phenomenon occurs.
This will cause warping of the C circuit and metal carrier.

斯かるメタルキャリアの反りによシ両者間に間隙を生じ
た場合、回路の動作時に意図しない共振現象等を起こす
ことになる。また、上記ＭＩＣ回路の反りにより、引張
曲げ応力が基板表面に加わった場合、パターン調整時等
にＭ、ＩＣ回路につけられたキズに該応力が集中し、基
板を破壊することになる。If a gap is created between the two metal carriers due to the warping of the metal carrier, an unintended resonance phenomenon will occur during circuit operation. Furthermore, if tensile bending stress is applied to the substrate surface due to the warping of the MIC circuit, the stress will be concentrated on scratches made on the M and IC circuits during pattern adjustment, etc., and the substrate will be destroyed.

尚、ＭＩＣ回路基板と、熱膨張率差の小さい材料、例え
ばコバール、アンバー、ニッケル合金を用いてメタルキ
ャリアを構成した場合、これらの材料はいずれも熱伝導
率の低いものであるため、メタルキャリアの放熱機能を
十分に発（ホさせることができない。In addition, when the metal carrier is constructed using the MIC circuit board and a material with a small difference in coefficient of thermal expansion, such as Kovar, amber, or a nickel alloy, since all of these materials have low thermal conductivity, the metal carrier The heat dissipation function of the device cannot be sufficiently emitted.

（４）発明の目的 本発明は、上記従来技術の問題点に鑑み為されだもので
あって、ＭＩＣ回路及びメタルキャリアの反りを小さく
することを目的としている。。(4) Purpose of the Invention The present invention was created in view of the problems of the prior art described above, and its purpose is to reduce the warpage of MIC circuits and metal carriers. .

（５）発明の構成 まだ、上記発明の目的を達成するために、本発明に係る
ＭＩＣ装置の製造方法では、ＭＩＣ回路とメタルキャリ
アとのロー付け、若しくはノ・ンダ付けによる接合の冷
却工程に於いて、該メタルキャリアを放熱台上に置き冷
却するとともに、該ＭＩＣ回路上に加熱した高熱ブロッ
クを載せ、高温に保つようにしたことを特徴としている
。(5) Structure of the Invention In order to achieve the above object of the invention, the method for manufacturing an MIC device according to the present invention includes a cooling process for joining the MIC circuit and the metal carrier by brazing or soldering. The metal carrier is placed on a heat sink to cool it, and a heated high-temperature block is placed on top of the MIC circuit to keep it at a high temperature.

（６）発明の実施例 以下、図面を参照して本発明の一笑雄側について説明を
する。(6) Embodiments of the Invention Hereinafter, the Issho side of the present invention will be explained with reference to the drawings.

第１図はＭＩＣ回路１とメタルキャリア５との接合工程
を示す図で、Ｍ■Ｃ回路１は、表面にマイクロストリッ
プライン４、共面に接地導体３が夫々形成された誘電体
基板２より成る。FIG. 1 is a diagram showing the bonding process between the MIC circuit 1 and the metal carrier 5. The MC circuit 1 is made of a dielectric substrate 2 on which a microstrip line 4 is formed on the surface and a ground conductor 3 is formed on the same surface. Become.

このＭＩＣ回路１をメタルキャリア５上に接合するに際
し、ロー材として使用される（Ａｕ−８ｎ）合金０の溶
融点（２８０℃）よりも高い温度にメタルキャリア５を
加熱する。斯かるメタルキャリア５の加熱は、ビータ７
を用いた加熱台８て行なわれ、また（Ａｕ−８ｎ）合金
６の酸化を防止するため、上記の加熱−接合工程は皇素
雰囲気中で行なわれる。その後、（Ａｕ　−８ｎ　）合
金６が溶融した時点で、ＭＩＣ回路１を載せ、接合を行
なう。When joining this MIC circuit 1 onto the metal carrier 5, the metal carrier 5 is heated to a temperature higher than the melting point (280° C.) of the (Au-8n) alloy 0 used as the brazing material. The metal carrier 5 is heated by the beater 7.
In order to prevent oxidation of the (Au-8n) alloy 6, the above heating-bonding process is performed in a copper atmosphere. Thereafter, when the (Au-8n) alloy 6 is melted, the MIC circuit 1 is mounted and bonded.

第２図は、上記接合工程後に行なわれる冷却工程を示す
図で、図中９は冷却のだめの放熱台、１０はＭＩＣ回路
１を加熱する加熱ブロックである。。FIG. 2 is a diagram showing a cooling step performed after the above-mentioned bonding step. In the figure, 9 is a heat sink for cooling, and 10 is a heating block for heating the MIC circuit 1. FIG. .

（Ａｕ　−Ｓｎ　）合金６′の溶融点は、前述の如く、
約２８０℃であるが、ＭＩＣ回路１とメタルキャリア５
の接合を拘束するのは、約２０゛０℃程度のロー材の硬
化時である。従って、斯かる硬化時にＭＩＣ回路１とメ
タルキャリア５が同一の温度であった場合、その後室温
にまで冷却した際に、両者の熱膨張の差が熱応力として
発生する。As mentioned above, the melting point of the (Au-Sn) alloy 6' is
The temperature is about 280℃, but the MIC circuit 1 and metal carrier 5
It is during the hardening of the brazing material at about 20°C that the bonding is restricted. Therefore, if the MIC circuit 1 and the metal carrier 5 are at the same temperature during such curing, the difference in thermal expansion between them will occur as thermal stress when they are subsequently cooled to room temperature.

そこで、本発明では熱膨張率の小さいＭｉＣ回路１を、
加熱ブロック１０を用いて加熱し、（Ａ、ｕ　−８ｎ）
合金６が硬化する際に、Ｍ工Ｃ回路１（誘電体基板２）
の温度を褐＜、メタルキャリア５の温度を低く保つよう
にしている。Therefore, in the present invention, the MiC circuit 1 with a small coefficient of thermal expansion is
Heating using the heating block 10, (A, u -8n)
When alloy 6 hardens, M engineering C circuit 1 (dielectric substrate 2)
The temperature of the metal carrier 5 is kept low, and the temperature of the metal carrier 5 is kept low.

（７）発明の詳細 な説明したように、本発明にしれば、Ｍ■Ｃ回路とメタ
ルキャリアの熱膨張率の差に基く熱応力を小さくシ、接
合−冷却工程終了後のＭＩＣ回路とメタルキャリアの反
りを小さくすることができる。よって、熱伝導率の優れ
たメタルギヤリアを採用し、且つ反りの小ないＭＩＣ装
置が製造される。(7) As described in detail, the present invention can reduce thermal stress based on the difference in thermal expansion coefficient between the MC circuit and the metal carrier, and Warpage of the carrier can be reduced. Therefore, a MIC device that uses a metal gear with excellent thermal conductivity and is less warped can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、Ｍ■−Ｃ回路と、メタルキャリアの接合工程
を、第２図は、その後の冷却工程を示す。 図中、１はＩｖＩＩＣ回路、２はお電体基板、３は接地
導体、４はマイクロストリップライン、５（ｄメタルキ
ャリア、６はロー材、１３ニヒータ、８は加熱台、９は
冷却台、ＩＩ］ｌ叶訓熱ブロックである。 代理人　弁理士　　松　岡　　宏四部 第１図　　　。 第２図FIG. 1 shows the joining process of the M■-C circuit and the metal carrier, and FIG. 2 shows the subsequent cooling process. In the figure, 1 is an IvIIC circuit, 2 is an electrical board, 3 is a ground conductor, 4 is a microstrip line, 5 (d metal carrier, 6 is a brazing material, 13 is a heater, 8 is a heating table, 9 is a cooling table, II ] This is Kano Kunnetsu Block. Agent Patent Attorney Hiroshi Matsuoka Department Figure 1. Figure 2

Claims (1)

【特許請求の範囲】[Claims] ＭＩＣ回路とメタルキャリアとのロー付け、遇しくけハ
ンダ付けによる接合の冷却工程に於いて、該メタルキャ
リアを放熱台上に置き冷却するとともに、該ＭＩＣ回路
上に加熱した高熱ブロックを載せ、高温に保つようにし
たことを特徴とするＭＩＣ装置の製造方法。In the cooling process of joining the MIC circuit and metal carrier by brazing or random soldering, the metal carrier is placed on a heat sink to cool it, and a heated high-temperature block is placed on top of the MIC circuit to cool it down. 1. A method for manufacturing an MIC device, characterized in that the MIC device is maintained at a constant temperature.
JP58073206A 1983-04-26 1983-04-26 Manufacture of mic(microwave) device Pending JPS59198726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58073206A JPS59198726A (en) 1983-04-26 1983-04-26 Manufacture of mic(microwave) device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58073206A JPS59198726A (en) 1983-04-26 1983-04-26 Manufacture of mic(microwave) device

Publications (1)

Publication Number Publication Date
JPS59198726A true JPS59198726A (en) 1984-11-10

Family

ID=13511440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58073206A Pending JPS59198726A (en) 1983-04-26 1983-04-26 Manufacture of mic(microwave) device

Country Status (1)

Country Link
JP (1) JPS59198726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0357425A2 (en) 1988-09-02 1990-03-07 Canon Kabushiki Kaisha An exposure apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0357425A2 (en) 1988-09-02 1990-03-07 Canon Kabushiki Kaisha An exposure apparatus

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