JPH11163021A - Manufacture of electronic component with bump - Google Patents

Manufacture of electronic component with bump

Info

Publication number
JPH11163021A
JPH11163021A JP9327779A JP32777997A JPH11163021A JP H11163021 A JPH11163021 A JP H11163021A JP 9327779 A JP9327779 A JP 9327779A JP 32777997 A JP32777997 A JP 32777997A JP H11163021 A JPH11163021 A JP H11163021A
Authority
JP
Japan
Prior art keywords
electronic component
substrate
resin
chip
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9327779A
Other languages
Japanese (ja)
Other versions
JP3351324B2 (en
Inventor
Masahide Koyama
賢秀 小山
Kenji Matsuo
健二 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP32777997A priority Critical patent/JP3351324B2/en
Publication of JPH11163021A publication Critical patent/JPH11163021A/en
Application granted granted Critical
Publication of JP3351324B2 publication Critical patent/JP3351324B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an electronic component with a bump which can be easily and inexpensively manufactured with satisfactory yield. SOLUTION: A recessed part is formed in a substrate by stamping, and a UV resin is applied to the surface of the substrate except for the recessed part, and hardened to form a resist film. Then, electrodes 11 and 12 are formed on the surface of the recessed part by a plating method. A chip 14 is loaded on the electrode 11, and the pad of the chip 14 is connected through a wire 15 with the electrode 12. The chip 14 and the wire 15 are sealed by the resin so that a mold body 16 can be formed, and a substrate 1 is removed, and the electrodes 11 and 12 are exposed so that a bump can be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、バンプ付電子部品
の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bumped electronic component.

【０００２】[0002]

【従来の技術】バンプ付電子部品は、基板の小型化、高
集積化に有利なことから、近年、様々な電子機器に多用
されるようになってきている。バンプ付電子部品の製造
方法としては、半田ボールなどの導電性ボールを用いる
方法や、スクリーン印刷によりパッドにクリーム半田を
塗布した後、クリーム半田を溶融固化させる方法などの
様々な方法が提案されている。2. Description of the Related Art In recent years, electronic components with bumps have been widely used in various electronic devices because they are advantageous for miniaturization and high integration of substrates. Various methods for manufacturing electronic components with bumps have been proposed, such as a method using conductive balls such as solder balls, a method of applying cream solder to a pad by screen printing, and then melting and solidifying the cream solder. I have.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら従来方法
は、いずれも製造コストが高く、また歩留りも必ずしも
高くないなどの問題点があった。However, all of the conventional methods have problems that the manufacturing cost is high and the yield is not always high.

【０００４】したがって本発明は、簡単かつ低コストで
歩留りよく製造できるバンプ付電子部品の製造方法を提
供することを目的とする。Accordingly, an object of the present invention is to provide a method of manufacturing an electronic component with bumps which can be manufactured easily and at a low cost with a high yield.

【０００５】[0005]

【課題を解決するための手段】本発明のバンプ付電子部
品の製造方法は、基材の表面に凹部を形成する工程と、
凹部を除く基材の表面にレジスト膜を形成する工程と、
メッキ手段により凹部の表面に導電材をメッキして電極
を形成する工程と、基材の表面のレジスト膜を除去する
工程と、複数個の電極のうちの何れかの電極上にチップ
を搭載する工程と、このチップと他の電極をワイヤで接
続する工程と、チップとワイヤを樹脂で封止する工程
と、樹脂と電極とを一体的に基材から分離し、電極の下
面を露呈させて電極をバンプとする工程と、を含む。A method of manufacturing an electronic component with bumps according to the present invention comprises the steps of: forming a concave portion on the surface of a substrate;
A step of forming a resist film on the surface of the substrate excluding the concave portions,
A step of forming an electrode by plating a conductive material on the surface of the concave portion by plating means, a step of removing the resist film on the surface of the substrate, and mounting a chip on any one of the plurality of electrodes A step of connecting the chip and another electrode with a wire, a step of sealing the chip and the wire with a resin, and a step of integrally separating the resin and the electrode from the base material and exposing the lower surface of the electrode. Using the electrodes as bumps.

【０００６】上記構成の発明によれば、基材に凹部加
工、レジスト膜加工、メッキ加工などを施しながら、バ
ンプ付電子部品を簡単に製造することができる。According to the invention having the above-described structure, it is possible to easily manufacture an electronic component with bumps while performing concave processing, resist film processing, plating processing, and the like on a base material.

【０００７】[0007]

【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。図１は、本発明の一実施の形態の
バンプ付電子部品の製造工程図、図２は同凹部が形成さ
れた基材の斜視図、図３は同バンプ付電子部品の断面
図、図４は同バンプ付電子部品の実装構造図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a manufacturing process diagram of an electronic component with bumps according to an embodiment of the present invention, FIG. 2 is a perspective view of a substrate having the concave portion formed thereon, FIG. FIG. 2 is a mounting structure diagram of the electronic component with bumps.

【０００８】まず、図１を参照してバンプ付電子部品の
製造方法を説明する。図１（ａ）〜（ｋ）は製造工程順
に示している。図１（ａ）においては、１はテープ状の
基材である。この基材１は銅などの導電材から成ってい
る。図１（ｂ）に示すように、基材１の表面に大形の凹
部２と小形の凹部３を形成する。本形態では、スタンピ
ング手段により凹部２を形成する。すなわち４はスタン
ピング用の金型であって、突起５ａ，５ｂが形成されて
おり、突起５ａ，５ｂを基材１の表面に押し付けること
により、複数個の凹部２，３を形成する。この場合、テ
ープ状の基材１を矢印方向に送行しながら、金型４を基
材１に対して上下動させて基材１に押し付けることによ
り、凹部２，３を高速度で形成することができる。First, a method of manufacturing a bumped electronic component will be described with reference to FIG. 1A to 1K are shown in the order of the manufacturing process. In FIG. 1A, reference numeral 1 denotes a tape-shaped base material. The substrate 1 is made of a conductive material such as copper. As shown in FIG. 1B, a large concave portion 2 and a small concave portion 3 are formed on the surface of a substrate 1. In this embodiment, the recess 2 is formed by a stamping means. That is, reference numeral 4 denotes a stamping die on which projections 5a and 5b are formed, and a plurality of recesses 2 and 3 are formed by pressing the projections 5a and 5b against the surface of the substrate 1. In this case, the concave portions 2 and 3 are formed at a high speed by moving the mold 4 up and down with respect to the base material 1 while pressing the base material 1 while feeding the tape-shaped base material 1 in the arrow direction. Can be.

【０００９】次に図１（ｃ）に示すように、基材１の表
面にレジスト材としてのＵＶ樹脂６を塗布する。ＵＶ樹
脂６の塗布手段は、基材１の表面に接地する第１ローラ
７と、第１ローラ７に当接する第２ローラ８と、第２ロ
ーラ８上にレジスト膜の素材であるＵＶ樹脂６を貯溜す
る容器９から成っている。基材１を第１ローラ７に対し
て矢印方向に相対的に送行させながら、容器９の底部か
ら第２ローラ８上にＵＶ樹脂６を微量づつ流出させる。
するとＵＶ樹脂６は第２ローラ８、第１ローラ７の周面
を流下し、基材１の表面に薄く塗布される。この場合、
第１ローラ７は凹部２，３の表面には当接しないので、
ＵＶ樹脂６は凹部２，３を除く基材１の表面に塗布され
る。Next, as shown in FIG. 1C, a UV resin 6 as a resist material is applied to the surface of the substrate 1. The means for applying the UV resin 6 includes a first roller 7 that contacts the surface of the substrate 1, a second roller 8 that contacts the first roller 7, and a UV resin 6 that is a resist film material on the second roller 8. Is stored in the container 9. While feeding the base material 1 relatively to the first roller 7 in the direction of the arrow, a small amount of the UV resin 6 flows out from the bottom of the container 9 onto the second roller 8.
Then, the UV resin 6 flows down the peripheral surfaces of the second roller 8 and the first roller 7 and is applied thinly on the surface of the substrate 1. in this case,
Since the first roller 7 does not contact the surfaces of the concave portions 2 and 3,
The UV resin 6 is applied to the surface of the substrate 1 excluding the concave portions 2 and 3.

【００１０】次に図１（ｄ）に示すように、放射線Ｌを
照射してＵＶ樹脂６を硬化させ、これによりレジスト膜
６’を生成する。次に図１（ｅ）に示すように、基材１
の裏面に絶縁性のマスキング材１０を薄くコーティング
する。図２は、以上のようにして形成された基材１を示
している。Next, as shown in FIG. 1D, radiation L is applied to cure the UV resin 6, thereby forming a resist film 6 '. Next, as shown in FIG.
Is coated thinly with an insulating masking material 10. FIG. 2 shows the substrate 1 formed as described above.

【００１１】次に基材１をメッキ槽に浸漬するなどし
て、基材１の表面に露呈する凹部２，３の表面にメッキ
を施し、電極１１，１２を形成する（図１（ｆ））。次
に図１（ｇ）に示すようにレジスト膜６’とマスキング
材１０を剥離して除去する。以上により基材１の加工は
終了する。以上のように本方法によれば、テープ状の基
材１を送行させながら作業性よく連続的に加工できる。Next, the surfaces of the concave portions 2 and 3 exposed on the surface of the substrate 1 are plated by immersing the substrate 1 in a plating tank or the like to form electrodes 11 and 12 (FIG. 1 (f)). ). Next, as shown in FIG. 1G, the resist film 6 'and the masking material 10 are peeled and removed. Thus, the processing of the base material 1 is completed. As described above, according to the present method, the tape-shaped substrate 1 can be continuously processed with good workability while being fed.

【００１２】次に一方の電極１１上にボンド１３を塗布
し、チップ１４を搭載する（図１（ｈ））。次にチップ
１４の上面のパッドと電極１２をワイヤ１５で接続する
（図１（ｉ））。次にチップ１４とワイヤ１５を樹脂で
封止してモールド体１６を形成する（図１（ｊ））。本
例のチップ１４はＬＥＤであり、その上面に光を透過さ
せる必要があるので、樹脂としては透明な透光性のもの
を用い、またチップ１４の上方は集光性のために半球状
の球面部１７とする。勿論、ＬＥＤ以外の他のチップの
場合は透光性は必要ではないので黒色などの有色の樹脂
でよく、また球面部１７も不要である。次に基材１を除
去して電極１１，１２の下面を露呈させれば電極１１，
１２はバンプとなり、バンプ付電子部品１９は完成する
（図１（ｈ））。Next, a bond 13 is applied on one electrode 11 and a chip 14 is mounted (FIG. 1 (h)). Next, the pads on the upper surface of the chip 14 and the electrodes 12 are connected by wires 15 (FIG. 1 (i)). Next, the chip 14 and the wires 15 are sealed with a resin to form a molded body 16 (FIG. 1 (j)). The chip 14 of this example is an LED, and it is necessary to transmit light to the upper surface thereof. Therefore, a transparent light-transmitting resin is used as the resin. The spherical portion 17 is used. Of course, in the case of a chip other than the LED, a light-transmitting property is not required, so a colored resin such as black may be used, and the spherical portion 17 is not required. Next, if the base material 1 is removed and the lower surfaces of the electrodes 11 and 12 are exposed,
Reference numeral 12 denotes a bump, and the electronic component 19 with a bump is completed (FIG. 1H).

【００１３】図３は以上のようにして完成したバンプ付
電子部品１９の断面図である。本例のバンプ付電子部品
１９は多数個取りであって、上記樹脂により形成された
モールド体１６はモールド体１６と同時に形成された樹
脂製の薄肉部１８（図１（ｋ）も参照）で互いに連結さ
れている。そこで薄肉部１８を切断してモールド体１６
同士を分離すれば、図３に示す単品のバンプ付電子部品
１９が得られる。FIG. 3 is a sectional view of the electronic component 19 with bumps completed as described above. The electronic component 19 with bumps in this example is a multi-piece, and the molded body 16 made of the resin is a thin portion 18 made of resin (see also FIG. 1 (k)) formed simultaneously with the molded body 16. Linked to each other. Then, the thin portion 18 is cut and the mold body 16 is cut.
When separated from each other, a single electronic component 19 with bumps shown in FIG. 3 is obtained.

【００１４】図４は以上のようにして製造されたバンプ
付電子部品１９を基板２０に実装した状態を示してい
る。バンプ付電子部品１９の電極１１，１２を基板２０
の電極２１，２２上に搭載し、半田などの接着剤２３に
より接着する。FIG. 4 shows a state in which the electronic component 19 with bumps manufactured as described above is mounted on a substrate 20. The electrodes 11 and 12 of the electronic component 19 with bumps are
Are mounted on the electrodes 21 and 22 and bonded by an adhesive 23 such as solder.

【００１５】図５は、本発明の他の実施の形態のバンプ
付電子部品の断面図である。電極１１’の側方には複数
個の電極１２’が形成されている。チップ１４’はボン
ド１３’により電極１１’上に搭載され、またチップ１
４’の上面のパッドと電極１２’はワイヤ１５’で接続
され、全体は樹脂で形成されたモールド体１６’で封止
されている。このバンプ付電子部品１９’も、図１に示
す方法と同じ方法により製造される。FIG. 5 is a sectional view of an electronic component with bumps according to another embodiment of the present invention. A plurality of electrodes 12 'are formed beside the electrodes 11'. Chip 14 'is mounted on electrode 11' by a bond 13 '
The pad on the upper surface of 4 'and the electrode 12' are connected by a wire 15 ', and the whole is sealed with a molded body 16' made of resin. This electronic component with bump 19 'is also manufactured by the same method as that shown in FIG.

【００１６】図４および図５に示すように、バンプ付電
子部品は、品種によってチップサイズや電極の寸法配列
が異るが、上記方法によれば、バンプ付電子部品の品種
が変る場合には、図１（ｂ）に示すスタンピング手段の
金型の形状を変更して基材に形成する凹部の寸法や配列
を変更すればよく、図１（ｃ）〜（ｇ）に示す各工程は
バンプ付電子部品の品種が変っても同一とすることが可
能であるので、バンプ付電子部品の品種変更にきわめて
対応しやすいという利点がある。As shown in FIGS. 4 and 5, the electronic components with bumps have different chip sizes and electrode dimensional arrangements depending on the types. However, according to the above-mentioned method, when the type of electronic components with bumps changes, By changing the shape of the mold of the stamping means shown in FIG. 1B to change the dimensions and arrangement of the recesses formed in the base material, each step shown in FIGS. Since it is possible to make the same even if the type of the electronic component with a change changes, there is an advantage that it is very easy to cope with the change in the type of the electronic component with a bump.

【００１７】[0017]

【発明の効果】本発明によれば、バンプ付電子部品を低
コストで簡単に製造でき、また製造の歩留りも高い。According to the present invention, electronic parts with bumps can be easily manufactured at low cost, and the production yield is high.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態のバンプ付電子部品の製
造工程図FIG. 1 is a manufacturing process diagram of an electronic component with bumps according to an embodiment of the present invention.

【図２】本発明の一実施の形態の凹部が形成された基材
の斜視図FIG. 2 is a perspective view of a substrate having a concave portion according to an embodiment of the present invention.

【図３】本発明の一実施の形態のバンプ付電子部品の断
面図FIG. 3 is a sectional view of an electronic component with bumps according to an embodiment of the present invention.

【図４】本発明の一実施の形態のバンプ付電子部品の実
装構造図FIG. 4 is a mounting structure diagram of an electronic component with bumps according to an embodiment of the present invention.

【図５】本発明の他の実施の形態のバンプ付電子部品の
断面図FIG. 5 is a sectional view of an electronic component with bumps according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 基材 ２，３ 凹部 ４ 金型 ６ ＵＶ樹脂 ６’ レジスト膜 １１，１１’，１２，１２’ 電極 １３，１３’ ボンド １４，１４’ チップ １５，１５’ ワイヤ １６，１６’ モールド体 １９，１９’ バンプ付電子部品 DESCRIPTION OF REFERENCE NUMERALS 1 base material 2, 3 concave portion 4 mold 6 UV resin 6 'resist film 11, 11', 12, 12 'electrode 13, 13' bond 14, 14 'chip 15, 15' wire 16, 16 'molded body 19, 19 'Electronic component with bump

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】基材の表面に凹部を形成する工程と、凹部
を除く基材の表面にレジスト膜を形成する工程と、メッ
キ手段により凹部の表面に導電材をメッキして電極を形
成する工程と、基材の表面のレジスト膜を除去する工程
と、複数個の電極のうちの何れかの電極上にチップを搭
載する工程と、このチップと他の電極をワイヤで接続す
る工程と、チップとワイヤを樹脂で封止する工程と、前
記樹脂と前記電極とを一体的に前記基材から分離して前
記電極の下面を露呈させて前記電極をバンプとする工程
と、を含むことを特徴とするバンプ付電子部品の製造方
法。A step of forming a concave portion on the surface of the substrate, a step of forming a resist film on the surface of the substrate except for the concave portion, and forming an electrode by plating a conductive material on the surface of the concave portion by plating means. Step, a step of removing the resist film on the surface of the base material, a step of mounting a chip on any one of the plurality of electrodes, and a step of connecting this chip and other electrodes by wires, A step of sealing the chip and the wire with a resin, and a step of separating the resin and the electrode from the substrate integrally and exposing a lower surface of the electrode to make the electrode a bump. A method for manufacturing a bumped electronic component.
JP32777997A 1997-11-28 1997-11-28 Manufacturing method of electronic component with bump Expired - Fee Related JP3351324B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32777997A JP3351324B2 (en) 1997-11-28 1997-11-28 Manufacturing method of electronic component with bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32777997A JP3351324B2 (en) 1997-11-28 1997-11-28 Manufacturing method of electronic component with bump

Publications (2)

Publication Number Publication Date
JPH11163021A true JPH11163021A (en) 1999-06-18
JP3351324B2 JP3351324B2 (en) 2002-11-25

Family

ID=18202894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32777997A Expired - Fee Related JP3351324B2 (en) 1997-11-28 1997-11-28 Manufacturing method of electronic component with bump

Country Status (1)

Country Link
JP (1) JP3351324B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111052584A (en) * 2017-08-30 2020-04-21 日立汽车系统株式会社 Power semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111052584A (en) * 2017-08-30 2020-04-21 日立汽车系统株式会社 Power semiconductor device and method for manufacturing the same
CN111052584B (en) * 2017-08-30 2023-07-11 日立安斯泰莫株式会社 Power semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
JP3351324B2 (en) 2002-11-25

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