JPH11162327A - Field emission device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-density field emission device by which a plane display with high precision or multi-gradation or the like can be realized, by adopting such a formation that insulating characteristics between cathode lines are excellent, and also provide a manufacturing method thereof. SOLUTION: In the field emission device which is composed of plural cathode lines 1c formed linearly showing conductivity on the surface of a substrate 1, field emission cathodes 4 arranged on the cathode lines 1c, and a gate electrode 3 which is arranged on the peripheries of the field emission cathodes 4 and formed linearly in the vertical direction relative to the cathode lines 1c, such a formation is adopted that intervals of plural cathode lines 1c are insulated by thermally oxidized silicon 1d.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission device capable of emitting electrons at a low voltage from the tip of a field emission cathode by addressing with a cathode line and a gate electrode, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, field emission devices used as electron emission sources have been applied to flat-panel image display devices, ultrahigh-speed microwave devices, sensors, and the like.
Then, a fine field emission cathode (also referred to as an emitter, hereinafter referred to as an emitter) can be formed, and a large number of emitters can be arranged on a substrate.

[0003] Such a field emission device is composed of an emitter array formed from a plurality of emitter cones on a cathode electrode, and a gate electrode formed around each of the emitters. Electrons are emitted from the emitter array by an electric field induced by a potential difference from the gate electrode.

[0004] As a field emission device capable of matrix addressing, there is known a field emission device as shown in a sectional view of a main part of FIG. This field emission device has a stripe-shaped cathode electrode (cathode line) on a substrate 101.
105 is formed, a plurality of cone-shaped emitters 104 are arranged thereon in an array, and a gate electrode 103 is arranged around the emitter array.
In the field emission device having such a structure, the cathode line 1
Electrons are emitted from the array of emitters 4 by the electric field induced by the potential difference between the gate electrode 103 and the gate electrode 103.

Japanese Patent Application Laid-Open No. 9-139177 discloses a field emission device as shown in a sectional view of a main part of FIG. This is because stripe-shaped cathode lines 115 such as ITO are formed on a substrate 111 such as glass,
A cone-shaped emitter 114 is disposed thereon, and a gate electrode 113 is further disposed around the emitter 114. By miniaturizing the opening of the gate electrode 113 to about submicron, a low voltage It is intended to realize a drivable field emission device.

On the other hand, JP-A-5-67426 discloses that
It is disclosed that a high-resistance semiconductor substrate such as non-doped silicon is doped with an impurity such as phosphorus to form an impurity diffusion layer, which is used as a low-resistance cathode line.

[0007]

However, a high-density field emission device, for example, which constitutes a high-definition or multi-tone flat display, cannot be achieved by the above-mentioned conventional device.

That is, in the conventional field emission device as shown in FIG.
And the pitch of the cathode lines 105 have limitations in their reduction.

In the field emission device described in Japanese Patent Application Laid-Open No. 9-139177, the pitch of the cathode lines 115 is limited in terms of insulation resistance and parasitic capacitance. The realization of a high density field emission device could not be expected.

Therefore, it is conceivable to use an impurity diffusion layer as described in Japanese Patent Application Laid-Open No. 5-67426 as a cathode line. However, if the pitch of the cathode lines is reduced, the insulation between the cathode lines becomes insufficient. Again, high density field emission devices could not be expected.

The present invention provides a high-density field emission device capable of realizing a high-definition or multi-tone flat-panel display and the like and a method of manufacturing the same by adopting a configuration having good insulation characteristics between cathode lines. The purpose is to do.

[0012]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, a plurality of cathode lines formed in a line shape showing conductivity on a substrate surface, and a plurality of cathode lines are formed on the cathode lines. In a field emission device composed of an arranged field emission cathode and a gate electrode arranged around the field emission cathode and formed in a vertical line with the cathode line, heat is applied between the plurality of cathode lines. Insulated by silicon oxide.

According to the first aspect of the present invention, since the cathode lines are insulated by silicon oxide having excellent insulation characteristics, the cathode line pitch can be reduced.

Further, according to the second aspect of the present invention, in the field emission device according to the first aspect, the cathode line is formed of an impurity diffusion layer into which impurities are introduced.

According to the second aspect of the present invention, since the cathode lines are formed of the impurity diffusion layers into which the impurities are introduced, the cathode lines can be easily formed with high density.

According to a third aspect of the present invention, in the field emission device according to the first or second aspect, the substrate is made of S
It is configured using an OI substrate.

SOI is an abbreviation of silicon on insulator and has a structure in which a silicon layer is disposed on an insulator.
This facilitates isolation between elements in the depth direction. According to the third aspect of the present invention, since such an SOI substrate is used as the substrate, a field emission device having a high-density cathode line pitch can be easily realized.

According to a fourth aspect of the present invention, in the field emission device according to the first, second, or third aspect, the gate electrode is curved toward the front end of the field emission cathode. It has to be a shape.

Conventionally, in a field emission device,
It has been proposed to coat a tip of a field emission cathode (emitter) with a low work function material to reduce the threshold voltage of field emission and drive the field emission device at a low voltage. However, in the configuration of the conventional field emission device, when the tip of the emitter is coated with a low work function material, short circuit occurs between the gate electrode and the emitter due to the wraparound of the low work function material, and the reliability of the device becomes a problem. In addition, if the opening of the gate is increased to prevent such a short circuit, the electric field strength at the tip of the emitter decreases, and the driving voltage increases. That is, there is a problem that there is a trade-off between high reliability and low voltage driving of the device.

On the other hand, according to the fourth aspect of the invention, by forming the gate electrode into the above-mentioned arcuate shape, the spatial margin between the gate electrode and the field emission cathode can be enlarged, and It is possible to reduce the short-circuit between the field emission cathode and the distance between the gate electrode and the tip of the field emission cathode as compared with the prior art, thereby realizing a highly reliable field emission device that can be driven at a low voltage. .

According to the fifth aspect of the present invention, a plurality of cathode lines formed in a line shape exhibiting conductivity on the substrate surface, a field emission cathode disposed on the cathode lines, and the field emission cathode In a method for manufacturing a field emission device comprising a cathode line and a gate electrode formed in a vertical line shape arranged around the substrate, heat is applied to an upper portion of a substrate in which a silicon layer is arranged on an insulating layer. A mask formation step of forming a mask for oxidation in a portion where a cathode line is formed, and a thermal oxidation step of thermally oxidizing a silicon layer of a substrate on which the mask is formed to form silicon oxide in a portion where a mask is not formed; Remove the mask,
An impurity diffusion step of forming an impurity diffusion layer serving as a cathode line by introducing impurities into a portion of the substrate where the mask of the silicon layer has been removed, and an interlayer forming an interlayer insulating film on the substrate on which the impurity diffusion layer is formed An insulating film forming step, a gate electrode forming step of forming a gate electrode layer on the interlayer insulating film, and a field emission cathode forming step of forming a contact hole in the interlayer insulating film to form a field emission cathode. I have.

According to the fifth aspect of the present invention, the first aspect is provided.
, A highly reliable field emission device which can be driven at a low voltage and can be easily manufactured.

Further, in the invention according to claim 6, in the method for manufacturing a field emission device according to claim 5, an SOI substrate is used as a substrate.

According to the invention described in claim 6, the above-mentioned field emission device can be manufactured more easily.

According to a seventh aspect of the present invention, in the method of manufacturing a field emission device according to the fifth aspect, the mask formed in the mask forming step is made of silicon nitride.

According to the seventh aspect of the present invention, since the silicon nitride whose technology in the formation and etching process is mature is used as a mask for the thermal oxidation, the formation is easy and the thermal oxidation process in the subsequent thermal oxidation step is performed. Silicon oxide can be easily formed.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a partial sectional perspective view showing a main part of an arrayed field emission device of the present embodiment, and FIG. 2 is an enlarged sectional side view of a single field emission device.

As shown in FIGS. 1 and 2, in this field emission device, a cone-shaped field emission cathode (hereinafter, referred to as an emitter) 4 is arranged on a substrate 1, and an interlayer insulating film 2 is interposed therebetween. And a gate electrode 3 having a stripe shape. On the surface of the substrate 1, a plurality of cathode lines 1c are formed by an impurity diffusion layer via a thermally oxidized silicon layer 1d, and a matrix structure is formed by the cathode lines 1c and the striped gate electrodes 3. I have. Further, the gate electrode 3 has an arcuate shape that is curved toward the tip of the emitter 4. The substrate 1 shown in FIGS. 1 and 2 has a structure in which a cathode line 1c and a thermally oxidized silicon layer 1d are formed on a lower silicon layer 1a via an insulating layer 1b.

According to the field emission device having the structure shown in FIGS. 1 and 2, the cathode line 1c is insulated by the thermally oxidized silicon layer 1d having an excellent insulating property. It can be smaller than before,
A high-density field emission device can be realized. Further, since the cathode lines 1c are formed by the impurity diffusion layers into which impurities are introduced, the pitch of the cathode lines 1c can be further reduced to facilitate the formation.

According to the field emission device having the structure shown in FIGS. 1 and 2, the gate electrode 3 / emitter 4
The spatial margin between them can be increased, the short circuit between the gate electrode 3 and the emitter 4 can be suppressed, the distance between the tip of the gate electrode 3 and the tip of the emitter 4 can be reduced, and the electric field that can be driven at a low voltage can be reduced. An emission device can be realized.

Here, the field emission device of the present embodiment will be described in more detail. The substrate 1 has an insulating layer 1a
And a cathode line 1c formed by an impurity diffusion layer, which is separated by a thermal silicon oxide layer 1d, and a single emitter 4 is formed on the cathode line 1c so as to be electrically connected to the cathode line 1c. ing. In the present embodiment, the emitter 4 is formed by evaporating a high melting point material such as Mo or W, and has a tip diameter of 20 nm.
It was as follows. The gate electrode 3 is arranged around the tip of the emitter 4. In this embodiment, the distance between the tip of the emitter 4 and the edge of the gate electrode 3 around the tip is 0.15 to 1 μm.
Was adjusted.

In the vicinity of the emitter 4 of the gate electrode 4, the gate electrode 4 has a convex arcuate shape which is close to the tip of the emitter 4 and is curved. The distance between the gate electrodes 3 is adjusted to 2.15 to 3 μm, and the emitter 4 and the gate electrodes 3 are insulated by the interlayer insulating film 2.

With regard to the interlayer insulating film of the present embodiment, the contact diameter of the interlayer insulating film 2 in the portion where the emitter 4 is formed is set to 0.3 to 2 μm, and the thickness of the interlayer insulating film 2 is set to 0.1 to 1 μm.
μm.

Further, although not shown, in the present embodiment, the tip portion of the emitter 4 is coated with a thin film of a low work function material to drive at a lower voltage.

As described above, according to the field emission device of the present embodiment, the cathode line 1c is insulated by the thermally oxidized silicon layer 1d having excellent insulation characteristics as described above.
The pitch of the cathode lines 1c can be reduced as compared with the conventional case, and a high-density field emission device can be realized. Further, since the cathode line 1c is formed by the impurity diffusion layer into which the impurity is introduced, the cathode line 1c
Can be easily formed with a reduced pitch.

According to the field emission device of this embodiment, the spatial margin between the gate electrode 3 and the emitter 4 can be increased by adopting the above-mentioned arcuate gate electrode structure. A short circuit between the gate electrode 3 and the emitter 4 can be suppressed, and the distance between the gate electrode 3 and the tip of the emitter 4 can be reduced as compared with the related art, so that a low-voltage drive and a highly reliable field emission device can be realized. . Further, since a short circuit between the gate electrode 3 and the emitter 4 can be suppressed and the tip portion of the emitter 4 can be coated with a low work function material, the driving voltage can be further reduced.

Next, a method of manufacturing the field emission device of this embodiment will be described with reference to FIGS.

As the substrate 1, as shown in FIG.
An SOI substrate having a structure in which a lower silicon layer 1a, an insulating layer 1b, and an upper silicon layer 1e are sequentially stacked can be used. As a SOI substrate fabrication technology, SIMOX
(Separation by Implanted Oxygen), Combined SOI, Z
MR (Zone Melting Recrystallization), solid phase epitaxy, lateral vapor phase epitaxy, FIPOS (Full Isolation b
y Porous Oxided Silico), but in this embodiment, SIMOX is used. In this method, high-concentration oxygen is ion-implanted into a silicon substrate, and a high-temperature heat treatment is performed to form a buried oxide film serving as an insulating layer 1b, thereby performing vertical element isolation.

The SOI substrate used in this embodiment is a P type (100), and the upper silicon layer 1e has a thickness of 190.
0 °, the thickness of the insulating layer 1b (buried oxide film) is 3700
Å.

First, on the substrate 1 as described above, FIG.
As shown in (a), a mask 5 is formed. In this embodiment, after a thermal oxide silicon film of 100 ° is formed as a pad oxide film (not shown) on the upper silicon layer 1e of the SOI substrate 1, a silicon nitride film serving as a mask for a subsequent thermal oxidation process is formed thereon. 2000 mm deposited. And
As shown in FIG. 3A, a mask 5 was formed by patterning the silicon nitride film by dry etching so as to form a shape of a cathode line. At this time, in order to miniaturize the mask 5, it is preferable to use a silicon nitride sidewall recess recess method as disclosed in JP-A-4-127433. Miniaturization is possible.

Next, as shown in FIG.
Is used to thermally oxidize the upper silicon layer 1e to form a thermally oxidized silicon layer 1d. In the present embodiment, the thermal oxidation of the upper silicon layer 1e is performed using the mask 5 formed by patterning the silicon nitride film to form the thermally oxidized silicon layer 1d. This thermal oxidation step is performed using a general L
OCOS oxidation can be performed under conditions. In the present embodiment, wet oxidation at 1100 ° C. has an oxidation time of about 14 minutes. At this time, in this embodiment, SO
Since the I substrate is used, the thermal silicon oxide layer 1d can be easily formed without strictly controlling the thermal oxidation conditions.

Next, after removing the mask 5, a cathode line 1c is formed in a portion of the upper silicon layer 1e where the thermally oxidized silicon layer 1d is not formed. In this embodiment,
An impurity is introduced into the cathode line 1c to form a cathode line composed of an impurity diffusion layer.

The removal of the mask 5 and the formation of the cathode line 1c according to the present embodiment will be described in more detail. First, the mask 5 made of a silicon nitride film was removed by immersion in phosphoric acid at 150 ° C. for 120 minutes. Then, after removing a pad oxide film (not shown) with hydrofluoric acid, a protective film 200 (not shown) is formed as a protective film for later ion implantation.
The thermal oxidation protective film of Å was formed. Then, in the portion of the upper silicon layer 1e where the thermal silicon oxide layer 1d is not formed,
Ion implantation was performed to introduce impurities. Ion implantation conditions at this time, injection volume 5 × 10 ¹³ to 5 phosphorus
It is preferable to perform the implantation under the conditions of × 10 ¹⁵ / cm ² and an implantation energy of 30 to 50 keV, and in this embodiment, 5 × 1
Phosphorus was implanted at 0 ¹³ / cm ² and 50 keV.

After the ion implantation, annealing is performed at 850 ° C. for 30 minutes to change the region to be an impurity diffusion layer from the p ⁻ layer to n ⁺
As a layer, a cathode line 1c as an impurity diffusion layer was formed.

Next, as shown in FIG. 3C, an interlayer insulating film 2 is formed. In this embodiment, as will be described later, since silicon nitride is used for the first and third dummy layers to be formed later, silicon oxide is used as a material having a different etching rate, and phosphoric acid is used as an etchant. Thus, the difference in etching rate (etching selectivity) was increased. In the present embodiment, the silicon oxide film as the interlayer insulating film 2 is formed by a CVD method using
It was deposited with a film thickness of μm.

The thickness of the silicon oxide film as the interlayer insulating film 2 is optimized according to the diameter of a contact hole to be formed later.
A film thickness of 1 to 0.1 μm is preferable to 3 to 2 μm.

Next, a first dummy layer 6 and a second dummy layer 7 are sequentially formed on the interlayer insulating film 2. In this embodiment, silicon nitride is used as the insulating film as the first dummy layer 6, and a silicon nitride film of 1000 ° is deposited by the CVD method. The second dummy layer 7 needs to have an etching rate different from that of the first dummy layer due to an etching step described later. Therefore, in this embodiment, silicon oxide is used as the insulating film as the second dummy layer 7, and a silicon oxide film of 500 ° is deposited by the CVD method.

In the present embodiment, in order to improve the patterning accuracy of the dummy layers 6 and 7 described later, the silicon oxide film as the second dummy layer 7 is formed at a high temperature (80 ° C.).
0 ° C.) and deposited at 900 ° C.
For about 20 minutes. The condition of this annealing is set in consideration of the activation annealing at the time of forming the cathode line 1c as the impurity diffusion layer.

Next, as shown in FIG. 3C, the first dummy layer 6 and the second dummy layer 7 are patterned so that the first dummy layer 6 and the second dummy layer As shown in FIG. 7, the shape is such that each dummy layer remains only in a portion where a contact hole described later is formed and an emitter is formed later. This patterning
It determines the distance between the emitter / gate electrode at the tip of the emitter and the diameter of the contact hole in which the emitter is formed.

In this embodiment, since a contact hole having a diameter of 1 μm is formed, as will be described later, the first dummy layer 6 and the second dummy layer 7 having a circular diameter of 1 μm are formed.
Patterning was performed by a dry etching method. Note that the first dummy layer 5 and the second
The diameter of the dummy layer 6 can be sufficiently reduced to about 0.3 μm by utilizing a semiconductor miniaturization process.

Next, as shown in FIG. 3D, a third dummy layer is deposited from above the patterned first dummy layer 6 and the second dummy layer 7, and then this third dummy layer 6 is deposited. Is etched back to form a sidewall 8 having a curved convex side surface so as to cover the side surfaces of the first dummy layer 6 and the second dummy layer 7.

The third dummy layer is preferably made of the same material as that of the first dummy layer 6 in consideration of the etching selectivity in the etching step described later, since the process is simplified. Therefore, in the present embodiment, the first dummy layer is used as the third dummy layer.
Of the same material as the dummy layer 6 was used.

The sidewall 8 determines the bow shape of the gate electrode 3. The thickness of the side wall 8 depends on the first dummy layer 6 and the second dummy layer 7.
Is controlled by the film thickness of the stacked layers and the film thickness of the third dummy layer. For example, in order to obtain a sidewall thickness of 1000 °, the thickness in which the first dummy layer 6 and the second dummy layer 7 are stacked needs to be 1000 ° or more, and the thickness of the third dummy layer needs to be about 1000 °. .

In the present embodiment, as described above, the first dummy layer (silicon nitride film) is formed by 1000 ° and the second dummy layer (silicon oxide film) is 500 °. A silicon nitride film was deposited as a third dummy layer at a thickness of 1000 ° by LPCVD. Then, the silicon nitride film, which is the third dummy layer, was etched back to obtain the sidewall 8 having a thickness of 1000 °.

The thickness of the sidewall is an important parameter for suppressing a short circuit between the gate electrode and the emitter, and the first dummy layer 6 and the second dummy layer 7 correspond to the device design. What is necessary is just to control with the film thickness of the laminated | stacked and the film thickness of the 3rd dummy layer.

Next, only the second dummy layer 7 is removed.
In the present embodiment, the first dummy layer 6 and the sidewall 8 formed from the third dummy layer are made of silicon nitride, and the second dummy layer 7 is made of silicon oxide. Was selectively etched. At this time, the silicon oxide film serving as the interlayer insulating film 2 is also etched at the same time. However, as described above, the thickness of the silicon oxide film serving as the second dummy layer 7 is 500 °, and the thickness of the silicon oxide film of the interlayer insulating film 2 is reduced. Since the film is 0.8 μm, there is no problem even if the silicon oxide film of the interlayer insulating film 2 is etched by about 500 °. In this embodiment, wet etching with hydrofluoric acid was used for the selective etching removal.

It is preferable that the side wall 8 is formed at a position where the edge of the side wall 8 overlaps with the end of the cathode line 1c formed of the impurity diffusion layer.

Next, as shown in FIG. 4A, a gate electrode layer 3 is formed. As a material of the gate electrode layer 3a,
Refractory metal materials such as W, Mo, and Nb are preferred. In the present embodiment, Mo is deposited by rotating the substrate at an incident angle of 15 ° by oblique rotation deposition, and the film thickness is 2 in the direction perpendicular to the substrate.
A gate electrode layer 3 was formed by depositing a Mo film of 2,000 °. At this time, an arcuate shape of the gate electrode layer 3 is formed around the sidewall 8 according to the shape.

Next, as shown in FIG. 4B, the first dummy layer 6 and the side wall 8 formed from the third dummy layer are removed. In the present embodiment, since these are made of silicon nitride, the interlayer insulating film 2 (silicon oxide film) and the gate electrode layer 3 (Mo film) are selectively etched by phosphoric acid (immersion at 150 ° C. for 120 minutes). Removed.
Since the gate electrode 3 thus formed is not formed by rotary oblique deposition using the cap on the emitter as a shielding mask, unlike the field emission device described in the above-mentioned Japanese Patent Application Laid-Open No. 9-139177, the vicinity of the emitter 4 Has a high mechanical strength without forming an extremely thin gate electrode.

Next, as shown in FIG. 4C, a contact hole 9 is formed in the interlayer insulating film 2. In this embodiment, the contact hole 9 is formed by dry-etching the silicon oxide film as the interlayer insulating film 2 by RIE using the gate electrode layer (Mo film) 3 as an etching mask.

Since the formation of the contact hole 9 is performed before the patterning of the gate electrode layer 3 to be described later, it is necessary to suppress the contamination due to the etching residue and the like inside the contact hole when the gate electrode layer 3 is patterned. In the present embodiment, the organic peeling cleaning is sufficiently performed to prevent the contamination of the organic matter by the etching residue or the like in the contact hole.

Next, the gate electrode layer 3 is patterned. In the present embodiment, the gate electrode layer is patterned in a stripe shape in a direction orthogonal to the cathode lines 1c by a normal photolithography technique. By this patterning, each gate electrode layer 3 has a structure insulated by a silicon oxide film (interlayer insulating film 2) having excellent insulating properties.
In addition, before this step, as described above, it is preferable to sufficiently wash.

Next, an emitter is formed. In this embodiment, a known formation method that has been reported by Spindt et al. Is used. That is, first, Al is rotated by a substrate at an incident angle of 15 ° by oblique rotation evaporation, and evaporation is performed.
Was formed (FIG. 4D). Next, Mo as an emitter material was vapor-deposited in a direction perpendicular to the substrate, thereby forming the emitter 4 inside the contact hole 9 (FIG. 5). In the present embodiment, the Mo film has a thickness of 1.2 μm
Vapor deposition was performed so as to have a film thickness of. Thereafter, lift-off was performed with phosphoric acid at 90 ° C., and the lift-off layer 10 and the Mo film 4a formed thereon were removed, whereby a field emission device as shown in FIG. 2 could be obtained.

Further, although not shown, a tip end of the emitter 4 is coated with a low work function material thereafter. In the present embodiment, LaB is formed by sputtering (or vapor deposition).
₆ was coated on the tip of the emitter 4 by 10 nm.
At this time, since the shape of the gate electrode 3 has an arcuate shape which is curved toward the tip of the emitter 4 as described above, the short work between the emitter and the gate electrode can be easily achieved without a short work function. The coating of the material could be performed. It should be noted that, as the low work function material, in addition to the LaB _6,
Cesium, rubidium, tantalum nitride, barium, chromium silicide, titanium carbide, hafnium carbide, zircon carbide, or the like can be used.

Using the field emission device manufactured as described above, an anode coated with a phosphor is disposed on the device,
By maintaining this in a vacuum state, applying a negative bias to the cathode line 1c and applying a positive bias to the gate electrode layer 3, electrons are emitted from a single addressed emitter and collide with the phosphor. Luminescence was observed. Further, in the field emission device of the present embodiment, no short circuit between the gate electrode layer 3 and the emitter 4 is observed at all,
An emission current (anode current) of 100 μA / tip (current value in a single field emission device (emitter)) or more was obtained at a lower driving voltage than that without coating with LaB ₆ .

As described above, according to the field emission device of the present embodiment, since the cathode line 1c is insulated by the thermally oxidized silicon layer 1d having excellent insulation characteristics, the pitch of the cathode line 1c is reduced as compared with the conventional case. And a high-density field emission device can be realized. Further, since the cathode lines 1c are formed by the impurity diffusion layers into which impurities are introduced, the pitch of the cathode lines 1c can be further reduced to facilitate the formation.

According to the field emission device of the present embodiment, the spatial margin between the gate electrode 3 and the emitter 4 can be increased by employing the above-described arcuate gate electrode structure. A short circuit between the gate electrode 3 and the emitter 4 can be suppressed, and the distance between the gate electrode 3 and the tip of the emitter 4 can be reduced as compared with the related art, so that a low-voltage drive and a highly reliable field emission device can be realized. . Further, since a short circuit between the gate electrode 3 and the emitter 4 can be suppressed and the tip portion of the emitter 4 can be coated with a low work function material, the driving voltage can be further reduced.

As described above, if the device is constructed using the field emission device according to the present invention, it can be applied as a flat-panel image display device. It can be applied to various devices such as sensors.

In the above description, a single field emission cathode (emitter) 4 is arranged in one matrix (intersection between the cathode line 1c and the linear (striped) gate electrode 3). However, a plurality of emitters 4 may be arranged in one matrix.

[0070]

As described above, according to the first aspect of the present invention, since the cathode lines are insulated by silicon oxide having excellent insulation properties, the insulation resistance and the parasitic capacitance are improved. The matrix addressable cathode line pitch can be reduced. Therefore,
ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to implement | achieve a high-density field emission device which can implement | achieve a flat display of high definition or multi-gradation.

Further, according to the second aspect of the present invention,
Since the cathode lines are constituted by the impurity diffusion layers into which impurities are introduced, the cathode lines can be easily formed with high density.

According to the third aspect of the present invention, since the SOI substrate is used as the substrate, a field emission device having a high-density cathode line pitch can be easily realized.

According to the fourth aspect of the present invention, the space between the gate electrode and the field emission cathode is formed by forming the gate electrode into an arcuate shape which is curved toward the front end of the field emission cathode. Margin can be expanded,
A short-circuit between the gate electrode and the field emission cathode is suppressed, and the distance between the gate electrode and the tip of the field emission cathode can be reduced to about 0.15 μm as compared with the related art. Devices can be realized. Furthermore, coating of the low-work-function material on the tip of the field emission cathode can be easily performed while suppressing a short circuit between the gate electrode and the field emission cathode.

According to the fifth aspect of the present invention, a highly reliable field emission device which can be driven at a low voltage and has a high reliability can be easily manufactured. Furthermore, in this manufacturing method, a thermal silicon oxide film for insulating the cathode line is formed by thermal oxidation of silicon, and the cathode line is formed by introducing impurities. The manufacture of a field emission device is possible.

Further, according to the invention described in claim 6,
The above-mentioned field emission device can be manufactured more easily.

According to the seventh aspect of the present invention, as a mask for thermal oxidation, silicon nitride whose technology in formation and etching process is mature is used, so that the formation is easy and thermal oxidation is performed later. Silicon oxide can be easily formed in the process.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional perspective view showing a main part of an arrayed field emission device according to an embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional side view of a single field emission device of the array of FIG.

FIG. 3 is a fragmentary cross-sectional view of a single field emission device for describing a method of manufacturing the field emission device of the present embodiment.

FIG. 4 is a cross-sectional view of a main part of a single field emission device for describing a method of manufacturing the field emission device of the embodiment.

FIG. 5 is a cross-sectional view of a main part of a single field emission device for describing a method of manufacturing the field emission device of the embodiment.

FIG. 6 is a sectional view of a main part showing a structure of a conventional field emission device.

FIG. 7 is a sectional view of a main part showing a structure of a conventional field emission device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 1c Cathode line 1d Thermal oxide layer 2 Interlayer insulating film 3 Gate electrode 4 Field emission cathode (emitter) 6 First dummy layer 7 Second dummy layer 8 Side wall 9 Contact hole

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Morino Yano 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka

Claims (7)

[Claims] 1. A plurality of cathode lines formed in a line shape showing conductivity on the surface of a substrate, a field emission cathode arranged on the cathode line, and the cathode line arranged around the field emission cathode. And a gate electrode formed in a vertical line shape, wherein the plurality of cathode lines are insulated by thermal silicon oxide. 2. The field emission device according to claim 1, wherein said cathode line is formed of an impurity diffusion layer into which impurities are introduced. 3. The field emission device according to claim 1, wherein the substrate is an SOI substrate. 4. The field emission device according to claim 1, wherein the gate electrode has an arcuate shape that is curved toward the front end of the field emission cathode. 5. A plurality of cathode lines formed in a line shape showing conductivity on a substrate surface, a field emission cathode arranged on the cathode line, and the cathode line arranged around the field emission cathode. And a gate electrode formed in the shape of a vertical line, comprising: a substrate having a silicon layer disposed on an insulating layer;
A mask forming step of forming a mask for thermal oxidation in a portion where the cathode line is formed; a thermal oxidation step of thermally oxidizing a silicon layer of the substrate on which the mask is formed to form silicon oxide in a portion where the mask is not formed; Removing the mask, introducing an impurity into a portion of the silicon layer of the substrate where the mask has been removed to form an impurity diffusion layer serving as a cathode line, and forming an impurity diffusion layer on the substrate on which the impurity diffusion layer is formed. Forming an interlayer insulating film on the interlayer insulating film, forming a gate electrode layer on the interlayer insulating film, forming a contact hole in the interlayer insulating film to form a field emission cathode. A method for manufacturing a field emission device, comprising: forming an emission cathode. 6. The method according to claim 5, wherein an SOI substrate is used as the substrate. 7. A mask formed in the mask forming step is made of silicon nitride.
3. The method for manufacturing a field emission device according to claim 1.