JPH10199400A - Manufacture of field emission element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the sizes of the hole diameters of the first and the second gate electrode layers individually. SOLUTION: After a hole 10a is formed to a second gate electrode 7 and a second insulation layer 6 by an etching, a resist layer is peeled off, and a metal layer 11 is formed by a rotary oblique vaporization (a), a hole 10b is framed to the bottom of the hole 10a, a first gate electrode layer 5, and a first insulation layer 4 by the etching (b), and after the metal layer 11 is peeled off, a cone form emitter 15 is formed in the hole 10b (c, d, and e). And a metal layer is formed on the second gate electrode layer, on the wall of the first hole, and to the first gate electrode to be the bottom of the first hole, by the rotary oblique vaporization and then, the second hole is formed to the first gate electrode layer and the first insulation layer by the etching, and after an emitter material layer is deposited up to form a cone form emitter in the second hole, the above metal layer and the above emitter layer are lifted off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission cathode known as a cold cathode, and more particularly to a method of manufacturing a field emission cathode having a focusing electrode having a novel structure.

[0002]

2. Description of the Related Art An electric field applied to a metal or semiconductor surface is 10
^At about ⁹ [V / m], electrons pass through the barrier and emit electrons in a vacuum even at room temperature due to the tunnel effect.
This is called field emission, and a cathode that emits electrons based on such a principle is called a field emission cathode (Fi
eld Emission Cathode). In recent years, it has become possible to create surface emission type field emission cathodes composed of micron-sized field emission cathodes by making full use of semiconductor processing technology.
It is going to be used for CRTs, electron microscopes and electron beam devices.

FIGS. 4A, 4B, 4C, 4D, and 4E
A conventional example of a method for manufacturing a triode type field emission cathode (hereinafter, referred to as FEC) having a first gate line and a second gate line will be described with reference to FIG.

First, as shown in FIG. 4A, a thin film conductor layer 42 serving as a cathode electrode is formed on a substrate 41 made of glass or the like, for example, by vapor deposition, and Si doped with impurities is formed thereon. A first resistance layer 43 is formed by film formation, and an insulating layer 44 is further formed thereon by, for example, SiO2. Then, Nb to be the first gate electrode layer 45 is deposited thereon. On the first gate electrode layer 45, a second insulating layer 46 is formed of, for example, SiO ₂ similarly to the above-mentioned first insulating layer 44, and a second gate electrode layer 47 is formed of the same Nb as the first gate electrode layer 45. It is formed of a material.

[0005] The laminated substrate is patterned by providing a positive photoresist layer (hereinafter simply referred to as a resist layer) 48 on its surface to form an opening pattern 49 as shown in FIG. Thereafter, anisotropic etching is performed on the opening pattern 49 by using, for example, SF ₆ gas and CHF ₃ gas in combination, and as shown in FIG. Hole 50 in the layer 46, the first gate electrode layer 45, and the first insulating layer 44.
To form Since it is difficult to stop the anisotropic etching immediately before forming the hole 50 immediately before the resistance layer 43, the anisotropic etching usually ends when the first insulating layer 44 remains about 0.1 μm on the resistance layer 43. doing.

Next, as shown in FIG. 4D, the first insulating layer 44 and the second insulating layer 46 on the side surfaces of the hole 50 are wet-etched using hydrofluoric acid. Then, the resistance layer 43 is exposed, and the first gate electrode layer 45 and the second gate electrode layer 47 are set to be in a slightly protruding state. Further, as shown in FIG. 4E, a release layer 5 made of, for example, Al is formed on the second gate electrode layer 47.
1 and a buffer material layer 52 of Cr or the like is formed.
Here, the buffer layer 52 a is formed at the bottom of the hole 50 by depositing the buffer material layer 52. Then, when an emitter material layer 53 such as Mo is deposited on the buffer material layer 52, the emitter material is deposited on the buffer layer 52a, and a cone-shaped emitter 54 is formed on the resistance layer 43. Although a detailed description of the buffer material layer 52 and the buffer layer 52a is omitted,
For example, as a prior art by the present applicant, Japanese Patent Application No. 7-346.
As shown in No. 273, by arranging the buffer layer 52a between the emitter 54 and the resistance layer 43 in the hole 50, for example, the adhesion strength of the emitter 54 is improved. Thereafter, when the peeling layer 51, the buffer material layer 52, and the emitter material layer 53 on the second gate electrode layer 47 are removed together by using a technique such as anodic oxidation, a two-layer structure as shown in FIG. FEC is obtained.

[0007]

However, for example, FIG.
As shown in FIG. 3C, R
When performing the IE, the resist layer 48 and the insulating layers 44, 46
The selectivity of (SiO ₂ ) cannot be obtained, that is, the resist layer 48 is also etched when the insulating layer 44 is etched. As a result, the shape of the hole 50 becomes tapered. Accordingly, the hole diameter G6 of the second gate electrode layer 47 and the hole diameter G5 of the first gate electrode layer 45 are enlarged by side etching, and the respective hole diameters G5,
It is difficult to control G6 independently. FIG.
It is impossible to make the hole diameter G6 smaller than the hole diameter G5 in the method described in the above, and the lift-off of the emitter material layer 53 becomes more difficult as the difference between the hole diameter G5 and the hole diameter G6 becomes larger.

When the hole diameter G6 is larger than the hole diameter G5, for example, as shown in FIG. 5A, when the emitter material layer 53 is deposited to form the emitter 54, the Mo of the Mo forming the emitter 54 is formed. Part of the second gate electrode layer 4
7 and may be left as a deposition portion 55 on the first gate electrode layer 45 in some cases. In this case, it is difficult to remove the deposited portion 55 adhering to the first gate electrode layer 45 by lift-off, and remains after lift-off as shown in FIG. 5B. In addition, the deposition section 55
If the etching is performed to remove this, there is a problem that the protruding portion of the first gate electrode layer 45 is removed. Therefore, if the thickness of the release layer 51 is increased in order to prevent residual Mo, the size of the emitter 54 is reduced, and the required emission characteristics cannot be obtained.

Further, it is difficult to individually control the hole diameter G5 of the first gate electrode layer 45 formed for drawing and the hole diameter G6 of the second gate electrode layer 47 formed for focusing. It is not easy to configure the FEC so as to achieve both a function of focusing emitted electrons and a distribution ratio.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and a cathode electrode, a first insulating layer, a first gate electrode layer, a second insulating layer,
A second gate electrode layer is sequentially stacked, and patterned with a resist layer formed on the second gate electrode layer, and a first hole is formed at a predetermined position on the second gate electrode layer and the second insulating layer. After being formed by dry etching and then peeling off the resist layer, at least the second gate electrode layer is deposited with a metal layer by rotary oblique deposition, and the bottom surface of the first hole and the first gate electrode layer and A second hole following the first hole is formed by dry-etching the first insulating layer, and after removing the metal layer, a cone-shaped bottom is formed on the bottom surface of the second hole by a lift-off process. Form the emitter.

In addition, a cathode electrode, a first insulating layer, a first gate electrode layer, a second insulating layer, and a second gate electrode layer are sequentially laminated on a substrate, and a resist formed on the second gate electrode layer is formed. By patterning with a layer, a first hole is formed at a predetermined position of the second gate electrode layer and the second insulating layer by dry etching, and then a metal layer is formed on the resist layer by rotary oblique deposition Then, a second hole following the first hole is formed in the bottom surface of the first hole, the first gate electrode layer, and the first insulating layer by dry etching, and then the resist layer and the metal layer are formed. After peeling, a cone-shaped emitter is formed in the second hole by a lift-off process.

Further, a cathode electrode, a first insulating layer, a first gate electrode layer, a second insulating layer, and a second gate electrode layer are sequentially laminated on a substrate, and a resist formed on the second gate electrode layer is formed. Patterning with a layer, a first hole is formed in the second gate electrode layer and the second insulating layer by dry etching, the resist layer is peeled off, and then a bottom surface of the first hole and a first hole are formed. The first gate electrode layer is exposed by etching the periphery of the hole, and then the first gate electrode layer and the first hole to be the wall of the first hole and the bottom surface of the first hole are formed by rotary oblique deposition. Forming a metal layer on a part of the gate electrode portion, then forming a second hole in the first gate electrode layer and the first insulating layer by etching, and then depositing an emitter material layer, In the second hall Forms a over down-like emitter, is lifted off the metal layer and the emitter material layer.

According to the present invention, the hole diameter of the first gate electrode layer is etched in a state where the metal layer is formed on the second gate electrode layer. Therefore, the second gate electrode layer is protected by the metal layer and is not etched. The size of the hole diameter of the gate electrode layer can be controlled independently.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a field emission device according to the present invention will be described below. FIG. 1 (a) (b)
(C), (d), and FIGS. 2 (a), (b), (c), and (d)
(E) is a process diagram illustrating a method for manufacturing the field emission device of the present embodiment. The substrate 1, the thin-film conductor layer 2, the resistance layer 3, the first insulating layer 4, and the like shown in these process diagrams are illustrated. The first gate electrode layer 5, the second insulating layer 6, the second gate electrode layer 7, and the resist layer 8 correspond to the substrate 41 and the thin-film conductor layer 4 described above with reference to FIG.
2, resistance layer 43, first insulating layer 44, first gate electrode layer 4
5, the second insulating layer 46, the second gate electrode layer 47, and the resist layer 48.

That is, as shown in FIG. 1A, a thin film conductor layer 2 serving as a cathode electrode is formed on a substrate 1 made of glass or the like by vapor deposition, and Si doped with impurities is formed thereon. The resistance layer 3 is formed by film formation,
The insulating layer 4 is formed by O ₂ . Then, Nb to be the first gate electrode layer 5 is deposited thereon. Then, the first insulating layer 4 described above is formed on the first gate electrode layer 5.
Similarly, the second insulating layer 6 is formed of SiO ₂ , and the second gate electrode layer 7 is formed of the same Nb material as the first gate electrode layer 5. Although a resist layer 8 for forming a hole is provided on the second gate electrode layer 7, in this embodiment, the resist layer 8 can be formed thinner than the conventional example previously shown in FIG. . Thereby, the resolution when performing the hole patterning can be improved.

First, the resist layer 8 is patterned to form an opening pattern 9 as shown in FIG. After that, two continuous RIEs using, for example, SF ₆ gas and CHF ₃ gas together are performed on the opening pattern 9.
(Reactive ion etching) to perform anisotropic etching to form the second gate electrode layer 7 and the second insulating layer 6
Then, as shown in FIG. 1C, a hole 10a serving as a first opening is formed. Then, the resist layer 8 is peeled off from the second gate electrode layer 7 as shown in FIG.

Next, the subsequent steps will be described with reference to FIG. After the resist layer 8 is peeled off, as shown in FIG.
A metal layer 11 for dry etching resistance such as
While protecting the second gate electrode layer 7, the second insulating layer 6, the first gate electrode layer 5, and the first insulating layer 4 are dry-etched as shown in FIG. A hole 10b is formed as two openings. At this time, since the second gate electrode layer 7 is protected by the metal layer 11, etching can be performed without increasing the hole diameter G2. The hole diameter G1 of the first gate electrode layer 5 can be approximately G by determining the thickness of the metal layer 11 to be deposited.
1 ≒ G2 or G1 <G2,
G1> G2 is also possible by increasing the amount of side etching under the conditions for etching the first gate electrode layer 5. Also, the extent of the side portion of the second insulating layer 6 can be controlled by the etching amount.

As described above, according to the present invention, when the metal layer 11 is formed by rotary oblique deposition, the thickness and the amount of side etching of the first gate electrode layer 5 are controlled so that the hole diameter of the first gate electrode layer 5 is reduced. The magnitude of G1 can be controlled. Note that the etching in FIG. 2B is stopped immediately before the resistance layer 3 so that the first insulating layer 4 is left with a predetermined thickness.

Next, as shown in FIG.
Perform wet processing. That is, the metal layer 11 is removed with, for example, phosphoric acid, and further, for example, using hydrofluoric acid, the second insulating layer 6 forming the wall of the hole 10a and the first forming the wall of the hole 10b are formed. The insulating layer 4 is wet-etched. Then, the resistance layer 3 is exposed, and the first gate electrode layer 5 and the second gate electrode layer 7 are set to be in a state of being slightly protruded.

Thereafter, as shown in FIG. 2D, a metal layer 12 of, for example, Al and a buffer material layer 13 of, for example, Cr are deposited on the second gate electrode layer 7. At this time, the buffer layer 13a is formed on the bottom surface (the resistance layer 3) of the hole 10b. Further, an emitter material layer 14 of, for example, Mo is deposited on the buffer material layer 13 to form an emitter 15 on the buffer layer 13a. The metal layer 12 is formed as a lift-off layer, and is formed to remove the buffer material layer 13 and the emitter material layer 14 after the emitter 15 is formed. Then, as shown in FIG. 2D, the emitter 15 is placed in the hole 10b.
Is formed, for example, lift-off is performed using phosphoric acid or the like, and as shown in FIG. 2E, the emitter material layer 14 is removed to form a two-layer FEC laminated substrate.

As described above, in the present embodiment, for example, when the metal layer 11 shown in FIG. 2A is formed by rotary oblique deposition, the thickness is controlled to control the second gate electrode layer 7.
The size of the hole diameter G1 of the first gate electrode layer 5 can be controlled by how much it protrudes into the inside of the hole diameter G2 formed in FIG. Further, as shown in FIG. 2B, when the first gate electrode layer 5 is etched, since the second gate electrode layer 7 is protected by the metal layer 11, the hole diameter G2 is increased by the side etching. Can be prevented. Further, since the hole diameter G1 and the hole diameter G2 can be controlled independently, it is possible to increase the hole diameter G1 and the hole diameter G2.

In the present embodiment, as shown in FIG. 1C, the resist layer 8 is peeled off after forming the hole 10a by dry etching.
For example, in the state shown in FIG. 1 (c), a metal layer 11 is vapor-deposited on the resist
At the time of lift-off (FIG. 2 (e)) after the formation of 5, it may be removed using, for example, phosphoric acid and a resist stripper. In this case, since the metal layer 11 is formed on the resist layer 8, it can be removed cleanly together with the resist layer 8, and the metal layer peeling step can be omitted.

Next, another embodiment of the present invention will be described with reference to FIG. In this embodiment, FIG.
The steps described in (a) to (d) are the same, and FIG.
(A) shows a step following FIG. 1 (d). Further, the substrate 21, the thin-film conductor layer 22, the resistance layer 23, the first insulating layer 24, the first gate electrode layer 25, the second insulating layer 26, the second gate electrode layer 27, the hole 28a shown in FIG.
Reference numeral 28b denotes the substrate 1, the thin-film conductor layer 2, the resistance layer 3, the first insulating layer 4, the first gate electrode layer 5, the second insulating layer 6, the second gate electrode layer 7, the hole 10a, 10b.

In this embodiment, similarly to the example described with reference to FIG. 1D, a wet process is performed after etching the second gate electrode layer 27 and the insulating layer 26, and further, for example, as shown in FIG. As described above, the wall of the hole 28a which is the first opening is etched to form the second gate electrode layer 2.
7 is slightly overhanging. At this time, the first gate electrode layer 25 is exposed as the bottom of the hole 28a. In this embodiment, a metal such as Al or Cr is vapor-deposited on the second gate electrode layer 27 at an angle θ, for example, by rotation oblique vapor deposition, and as shown in FIG. 29 are formed. Note that the angle θ is an angle that is also deposited near the end of the first gate electrode layer 25 exposed as the bottom surface of the hole 28a when the rotation oblique deposition is performed.

Next, as shown in FIG.
The first gate electrode layer 25 and the first insulating layer 24 are etched to form a hole 28b serving as a second opening. At this time, the hole diameter G of the first gate electrode layer 25 is changed.
3 is the size of the first gate electrode layer 25 shown in FIG.
Corresponds to the exposed area. In other words, the size of the hole diameter G3 can be set by changing the angle θ at which the rotation oblique deposition is performed in FIG. 3B. After the first gate electrode layer 25 and the first insulating layer 24 are etched, as shown in FIG. 3D, the wall of the first insulating layer 24 in the hole 28b is etched by wet processing, The end of the first gate electrode layer 25 is set to be in a slightly protruding state.

Then, a buffer material layer 30 and an emitter material layer 31 are deposited on the metal layer 29 to obtain a structure shown in FIG.
The buffer layer 30 is formed on the resistance layer 23 as shown in FIG.
a, the emitter 32 is formed, and then the metal layer 29 is lifted off together with the emitter material layer 31 by, for example, phosphoric acid or the like. This makes it possible to configure a two-layer FEC as shown in FIG. As described above, in another embodiment, as shown in FIG. 3B, by forming the metal layer 29 for protecting the second gate electrode layer 27, the metal layer 29 is lifted off and the emitter material is removed. Since the layer 31 can be removed, there is no need to form the metal layer 12 for lifting off the emitter material layer 14, as shown in FIG. 2D, thereby simplifying the manufacturing process. become able to. When lift-off is performed, the emitter material layer 3 such as Mo deposited near the first gate electrode 25 may be used.
1 can be removed at the same time.

[0027]

As described above, according to the present invention, in the step of etching a hole in which an emitter cone is formed,
By adding the step of etching the metal layer as a resist film, the second gate electrode layer is not etched when etching the hole diameter of the first gate electrode layer,
The hole diameters of the first and second gate electrode layers can be independently controlled. Further, since the selectivity between Al for forming a metal layer and SiO ₂ for forming an insulating layer is high, the etching rate can be increased by using O ₂ or the like. Furthermore, the number of steps can be reduced by using the metal layer also as the lift-off layer. Further, there is an advantage that the metal layer can be removed quickly and reliably together with the resist layer by removing the resist layer by obliquely depositing the metal layer directly on the resist layer.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating steps of a method for manufacturing a field emission device according to an embodiment of the present invention.

FIG. 2 is a view for explaining steps of a method of manufacturing the field emission device according to the embodiment following FIG. 1;

FIG. 3 is a diagram illustrating a process of a method for manufacturing a field emission device according to another embodiment of the present invention.

FIG. 4 is a view for explaining steps of a conventional method for manufacturing a field emission device.

FIG. 5 is a diagram illustrating a conventional emitter material deposited on a first gate electrode layer.

[Explanation of symbols]

 1, 21 Substrate 2, 22 Thin film conductor layer 3, 23 Resistive layer 4, 6, 24, 26 Insulating layer 5, 25 First gate electrode layer 7, 27 Second gate electrode layer 8 Resist layer 10a, 10b Hole 11, 12 , 29 Metal layer 13, 30 Buffer material layer 14, 31 Emitter material layer 15, 32 Emitter

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yuji Ohara 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Corporation

Claims (3)

[Claims] 1. A cathode electrode, a first insulating layer,
A first gate electrode layer, a second insulating layer, and a second gate electrode layer are sequentially stacked and patterned with a resist layer formed on the second gate electrode layer to form the second gate electrode layer and the second insulating layer. A first hole is formed at a predetermined position of the layer by dry etching, and after the resist layer is peeled off, at least the second gate electrode layer is deposited with a metal layer by rotary oblique deposition, and the first hole is formed. Forming a second hole following the first hole by dry etching the bottom surface of the hole and the first gate electrode layer and the first insulating layer, after peeling the metal layer,
A method for manufacturing a field emission device, wherein a cone-shaped emitter is deposited on a bottom surface of the second hole by a lift-off process. 2. A cathode electrode, a first insulating layer,
A first gate electrode layer, a second insulating layer, and a second gate electrode layer are sequentially laminated, and patterned with a resist layer formed on the second gate electrode layer, to form the second gate electrode layer and the second insulating layer. A first hole is formed at a predetermined position of the layer by dry etching, and then a metal layer is formed on the resist layer by rotary oblique deposition, and a bottom surface of the first hole and the first gate electrode layer and A second hole following the first hole is formed in the first insulating layer by dry etching, and then, after the resist layer and the metal layer are peeled off, a cone-like shape is formed in the second hole by a lift-off process. A method for manufacturing a field emission device, comprising depositing an emitter. 3. A cathode electrode, a first insulating layer,
A first gate electrode layer, a second insulating layer, and a second gate electrode layer are sequentially laminated, and patterned with a resist layer formed on the second gate electrode layer, to form the second gate electrode layer and the second insulating layer. Forming a first hole in the layer by dry etching to peel off the resist layer, and then etching the bottom surface of the first hole and the periphery of the first hole to expose the first gate electrode layer, Next, a metal layer is formed on the second gate electrode layer by rotary oblique deposition and on a part of the first gate electrode portion serving as a wall portion of the first hole and a bottom surface of the first hole. Forming a second hole in one gate electrode layer and the first insulating layer by etching, and then depositing an emitter material layer to form a cone-shaped emitter in the second hole; And emitter material Method of manufacturing a field emission device characterized by lifting off the layer.