JP3146471B2 - Field emission type electron-emitting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type electron-emitting device which emits electrons by a strong electric field. More specifically, an array of FEAs constituting a flat panel display
The present invention relates to an electron-emitting device that can be preferably applied to (FieldEmitter Array).

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices which are smaller in size than CRTs, light in weight, and easy to flatten have become widely used as displays for computers and the like.

However, the liquid crystal display element has a narrow viewing angle,
In addition, there is a disadvantage that the power consumption of the backlight is large. Therefore, in recent years, a flat type self-luminous display having high-speed response and high resolution has been strongly demanded.
A promising display structure for this purpose is one in which fine electron-emitting devices having cold electrodes that emit cold electrons instead of thermoelectrons are arranged in an array in a high-vacuum flat plate cell.

[0004] As such a minute electron-emitting device,
A device utilizing a so-called field emission phenomenon is known (Journal of Applied Physi).
cs. 39 (7), p3504 (1968);
1-222183). That is, in the field emission type electron-emitting device, when the intensity of the electric field applied to the substance is increased, the width of the energy barrier on the surface of the substance is gradually narrowed according to the intensity, and the electric field intensity is increased to 10 ⁷ V / cm or more. When it comes
This utilizes the phenomenon that electrons in a substance can break through the energy barrier due to a tunnel effect, and thus electrons are emitted from the substance. For this reason, the field emission type electron-emitting device can realize a high current density, can reduce power consumption, and
It has the advantage that it can be manufactured by LSI fine manufacturing technology.

A conventional field emission type electron-emitting device is shown in FIG.
As shown in (cross-sectional view) and FIG. 7 (schematic perspective view), this is an element having a cone-shaped emitter electrode, an insulating substrate 61 such as a glass substrate, low-resistivity silicon (Si) or chromium (Cr). An emitter wiring pattern 62 made of
An insulating layer 63 such as SiO ₂ and Cr or molybdenum (M
o), etc. are sequentially laminated, and the emitter electrode pattern 6 is formed between the gate electrode 64 and the insulating layer 63.
2 is opened by an etching method or the like, and the emitter wiring pattern 62 in the opening a is
An emitter electrode 65 made of a metal having a high melting point and a low work function, such as Mo or tungsten (W), whose tip is processed into a needle shape having a radius of curvature of submicron or less so as not to contact the insulating layer 63 and the gate electrode 64. Is provided. In this case, the gate electrode 64 is a common electrode in one pixel formed by a plurality of electron-emitting devices.

The conventional electron-emitting device shown in FIG.
It is manufactured as shown in FIG.

First, an Si film doped with a high concentration of phosphorus is formed on an insulating substrate 61 such as glass, and is patterned by a photolithographic method or the like to form an emitter wiring pattern for applying a voltage to the emitter. 62 are formed (FIG. 8A).

Next, an insulating layer 63 is formed on the emitter wiring pattern 62 by a thermal oxidation method, a sputtering method, a vacuum evaporation method, or the like.
And the gate electrode 64 are sequentially laminated (FIG. 8B).

Next, a resist layer is coated and patterned on the gate electrode 64, and the gate electrode 6 is formed by anisotropic etching such as reactive ion etching using the patterned resist layer as an etching mask.
A hole a having a diameter of about 1 to 2 μm reaching the emitter wiring pattern 62 is formed in the insulating layer 4 and the insulating layer 63, and the resist layer used as an etching mask is removed by a conventional method (FIG. 8C). ).

Next, copper (Cu), aluminum (Al), or the like is formed on the gate electrode 64 by the oblique rotation evaporation method.
The lift-off layer 66 is formed by vapor deposition so as to reduce the diameter (FIG. 8D).

Then, a metal for the emitter electrode 65 is deposited from the vertical direction of the insulating substrate 61 by using an anisotropic deposition method, for example, a reactive electron beam (REB) deposition method. Thus, an emitter electrode 65 having a sharp tip is formed inside the hole a, and a thin metal layer 67 is also formed on the lift-off layer 66 so as to cover the hole a (FIG. 8).
(E)).

Next, the lift-off layer 66 is removed by a selective etching method or the like, whereby the thin metal layer 67 is lifted off. Thus, an electron-emitting device having a cone-shaped emitter electrode 65 as shown in FIG. 6 is obtained (FIG. 8).
(F)).

In addition to an electron-emitting device having a cone-type emitter electrode, an electron-emitting device having a disk-type emitter electrode as shown in FIG. 9 has been proposed in order to ensure uniform workability over a wide area. (Japanese Unexamined Patent Publication No.
No. 137327). The structure of the electron-emitting device includes an insulating substrate 61, an emitter wiring pattern 62, an insulating layer 63.
The gate electrode 64 and the insulating layer 63 are provided with an opening a reaching the emitter wiring pattern 62, and the emitter base layer 68 is formed on the emitter wiring pattern 62 in the opening a. And the emitter electrode 69 are stacked so as not to contact the insulating layer 63 and the gate electrode 64.

[0014]

However, when manufacturing an electron-emitting device having a cone-type emitter electrode as shown in FIGS. 6 and 7, the lift-off layer 66 is obliquely rotated as shown in FIG. The emitter electrode 65 is formed by an anisotropic evaporation method and the emitter electrode 65 is formed by an anisotropic evaporation method. However, it is difficult to form the emitter electrode 65 having a uniform and uniform pointed tip over a wide range by these methods. There was a problem.

For this reason, the emitter electrode 65 may be formed to be inclined due to uneven deposition, and when a voltage is applied to such an emitter electrode 65, the emitter electrode 65 and the gate electrode 64 are short-circuited. There was a problem of doing.

In order to solve such a problem, as described above, a disk-type emitter electrode 69 as shown in FIG. Electron-emitting devices have been proposed. However, also in this electron-emitting device, since the distance between the emitter electrode 69 and the gate electrode 64 is very small, there is a problem that conductive dust adheres to them and causes a short circuit.

The emitter electrode 65 of any shape,
Even when the gate electrode 64 is used, if a short circuit occurs between the emitter electrodes 65 and 69 and the gate electrode 64, the gate electrode 6
Since 4 is a common electrode in one pixel, the whole one pixel is affected, causing a problem that the pixel becomes unusable.

An object of the present invention is to solve the above-mentioned problems of the prior art. When a plurality of electron-emitting devices are arranged in an array to constitute one pixel, one electron-emitting device is provided. It is an object of the present invention to minimize adverse effects on other electron-emitting devices even if an emitter electrode and a gate electrode of the device are short-circuited, and to prevent a pixel from becoming defective.

[0019]

Means for Solving the Problems The present inventors did not use the entire gate electrode of the electron-emitting device in one pixel as a common electrode, but instead formed one gate wiring pattern for applying a voltage to the gate electrode. The present inventors have found that the above object can be achieved by making the gate wiring pattern and the gate electrode electrically common in a pixel by a capacitive coupling method, and have completed the present invention.

That is, the present invention provides an emitter wiring pattern,
An emitter electrode provided thereon, a first insulating layer provided on the conductive layer so as to surround the emitter electrode, and a first insulating layer provided so as to surround the emitter electrode on the first insulating layer. In a field emission type electron-emitting device comprising a gate electrode, a gate wiring pattern for applying a voltage to the gate electrode is formed on the gate electrode so as to be electrically connected to the gate electrode by a capacitive coupling method. Provided is a field emission type electron-emitting device, which is provided via a second insulating layer.

Hereinafter, the electron-emitting device of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of a preferred embodiment of the electron-emitting device of the present invention having a cone-shaped emitter electrode.
This electron-emitting device includes an insulating substrate 1, an emitter wiring pattern 2 formed thereon, an emitter electrode 3 provided on the emitter wiring pattern 2, and an emitter electrode 3 provided on the emitter wiring pattern 2 so as to surround the emitter electrode 3. A first insulating layer 4 provided, and an emitter electrode 3 on the first insulating layer 4.
Having a gate electrode 5 disposed so as to surround
The gate electrode 5 and a gate wiring pattern 6 for applying a voltage to the gate electrode 5 have a structure in which they are electrically connected to each other via a second insulating layer 7 by a capacitive coupling method.

When each electron-emitting device has such a structure, when one pixel is constituted by a plurality of electron-emitting devices, the gate wiring pattern 6 is shared with the gate wiring patterns of other electron-emitting devices. This eliminates the need for the gate electrode 5 to be a common electrode. Therefore, even if the emitter electrode 3 and the gate electrode 5 of one electron-emitting device are short-circuited, the influence on other electron-emitting devices can be prevented as much as possible, and the performance of one pixel as a whole is substantially maintained. be able to.

In the electron-emitting device of the present invention, the insulating substrate 1 functions as a support for the electron-emitting device, and a glass substrate having a thickness of about 0.3 to 5 mm can be used.

The emitter wiring pattern 2 is a wiring for applying a voltage to the emitter electrode 3. Materials for the emitter wiring pattern 2 include Cr, Ta, Al, Cu, S
Preferred examples include i. The thickness of the emitter wiring pattern 2 is preferably about 0.1 to 0.5 μm.

The emitter wiring pattern 2 includes
Although a substrate provided on an insulating substrate such as glass may be used, a conductive substrate such as a silicon substrate may be used so that the emitter wiring pattern itself can function as a support. In this case, the insulating substrate can be omitted.

The emitter electrode 3 functions as a member for directly emitting electrons from its tip. As a material of such an emitter electrode 3, a material having a small work function, good electron emission characteristics, high voltage resistance, and a high melting point is used. Such materials include Cr, W, M
Preferred examples include o, Ta, and Nb.

The first insulating layer 4 is made of SiO ₂ , Si
It is preferable to use an inorganic insulating compound such as N or Ta ₂ O ₅ . The layer thickness varies depending on the size of the emitter electrode 3 and the like, but is preferably about 0.5 to 2 μm.

The gate electrode 5 is an electrode for concentrating a strong electric field on the emitter electrode 3. As the material of the gate electrode, a material that is not easily sputtered is preferable, but a material can be appropriately selected in consideration of process compatibility. Preferred examples of such a material include Cr, W, Mo, Ta, and Nb. The thickness of the gate electrode 5 varies depending on process resistance, processability, etc.
It is preferable to set it to 0.6 μm.

The gate wiring pattern 6 applies a voltage to the gate electrode 5 through the second insulating layer 7 by a capacitive coupling method. The thickness of the gate wiring pattern 6, the surface area facing the gate electrode 5, and the like can be appropriately selected.

The second insulating layer 7 functions as a separator for electrically coupling the gate wiring pattern 6 and the gate electrode 5 by a capacitive coupling method. As a material of such a second insulating layer 7, it is preferable to use an inorganic insulating compound such as SiO ₂ or Ta ₂ O ₅ . The layer thickness varies depending on the size of the emitter electrode 3 and the like, but is preferably about 0.1 to 1 μm.

FIG. 2A is a plan view of the gate electrode of the electron-emitting device of FIG. In this case, the gate electrode 5 includes a donut portion 5a surrounding the conical emitter electrode 3 and a capacitive coupling portion 5b for capacitive coupling with the linear gate wiring pattern 6.

The shape of the gate electrode 5 of the electron-emitting device is not limited to this example, and may be any shape as long as it surrounds the emitter electrode 3 and is electrically insulated from the adjacent gate electrode. . For example, a shape as shown in FIG. In addition, in the examples of FIGS. 2A and 2B, an example in which an independent gate electrode 5 is provided for one emitter electrode 3 is shown. However, as shown in FIG. , Unless they affect
For example, the gate electrode 5 for the two emitter electrodes 3 may be configured as a common electrode.

2 (a) to 2 (c), the gate wiring pattern 6 is shown as an example of a line shape. For example, as shown in FIG. 2D, a film shape having an opening b at a portion corresponding to the emitter electrode 3 may be used.

FIG. 3 is a plan view of one pixel formed by arranging the electron-emitting devices of FIG. 2A in an array.

Next, an example of a method for manufacturing the electron-emitting device of the present invention in which the emitter wiring pattern also functions as a support substrate is shown in FIGS. 4 (cross-sectional views (a) to (j)) and FIG. a) to (e) and plan views (f) to (j)).

First, a conductive substrate (1) functioning as the emitter wiring pattern 2 is prepared (FIGS. 4A and 5).
(A)).

Next, an insulating layer 4x to be a first insulating layer is formed on the emitter wiring pattern 2 by a thermal oxidation method, a sputtering method,
A conductive layer 5x to be a gate electrode is formed by a vacuum deposition method or the like (FIG. 4B and FIG. 5).
(B)).

The gate electrode 5 is formed by patterning the conductive layer 5x by a photolithographic method (FIGS. 4C and 5C). In this case, the gate electrode 5 is patterned so as to include a donut portion 5a surrounding the emitter electrode 3 and a capacitive coupling portion 5b for capacitive coupling with the gate wiring pattern.

Next, an insulating material layer 7a to be a second insulating layer is formed on the gate electrode 5 by a sputtering method or the like, and a conductive material layer 6a to be a gate wiring pattern is formed (FIG. 4D). And FIG. 5 (d)).

The conductive material layer 6x is patterned by photolithography or the like to form a line-shaped gate wiring pattern 6 (FIGS. 4E and 5E).

Next, the second insulating layer 7 is formed by photolithography or the like by patterning so that an opening for providing an emitter electrode is formed in the insulating material layer 7x (FIG. 4F). And FIG. 5 (f)).

Next, an insulating material layer 4x serving as a first insulating layer
The first insulating layer 4 is formed by forming an opening a reaching the emitter wiring pattern 2 by etching by photolithography or the like (FIG. 4G and FIG. 5).
(G)). At this time, it is preferable to perform side etching on the inner wall of the opening a in order to improve the function of the gate electrode 5 for concentrating the electric field on the emitter electrode.

Next, a lift-off layer 8 is formed on the entire surface of the second insulating layer 7 (FIGS. 4 (h) and 5 (h)). It is preferable to reduce the opening diameter of the portion a, and for this purpose, it is preferable to form the lift-off layer 8 on the rotating conductive substrate (1) by oblique deposition.
An Al layer having a thickness of about 0.3 to 1 μm can be formed as the lift-off layer 8.

Next, the emitter electrode 3 having a sharp tip is formed in the opening a by vapor-depositing a material for the emitter electrode from the vertical direction of the conductive substrate 1 (see FIGS. 4 (j) and 5 ( j)) At this time, the emitter electrode material layer 9 is also formed on the lift-off layer 8.

Finally, the lift-off layer 8 is removed by selective etching or the like, and the emitter electrode material layer 9 is lifted off. Thereby, FIG. 4 (k) and FIG.
An electron-emitting device of the present invention as shown in (k) is obtained.

Although FIGS. 1 to 5 show an example in which the emitter electrode is of a cone type, the present invention is not limited to this.
The present invention can be applied to an electron-emitting device having a disk-type emitter electrode as described in Japanese Patent No. 37327.

[0048]

In the electron-emitting device of the present invention, the gate electrode and the gate wiring pattern are electrically connected by a capacitive coupling method. Therefore, when forming a pixel from a plurality of electron-emitting devices, the gate wiring pattern can be shared in the pixel, and the gate electrode can be made electrically independent of the gate electrodes of other electron-emitting devices. Therefore, even if the gate electrode and the emitter electrode of one electron-emitting device are short-circuited, other electron-emitting devices can be prevented from being adversely affected, so that the pixel does not become defective as a whole.

[0049]

FIG. 4 shows an example of manufacturing an electron-emitting device according to the present invention.
The process will be described with reference to FIG.

First, a phosphorus-doped 0.36 m thick
m of silicon substrate (1) was prepared. This surface functions as a solid emitter wiring pattern 2 (FIGS. 4A and 5A).

Next, a 1.2 μm thick SiO ₂ layer 4x serving as a first insulating layer is formed on the emitter wiring pattern 2 by a thermal oxidation method.
A 3 μm Mo layer 5x was formed by a sputtering method (FIG. 4).
(B) and FIG. 5 (b)).

The gate electrode 5 was formed by patterning the Mo layer 5x by photolithography (FIGS. 4C and 5C). In this case, the gate electrode 5 was patterned so as to include a donut portion 5a having an inner diameter of 1 μm and an outer diameter of 6 μm, and a rectangular capacitive coupling portion 5b of 3 × 3 μm for capacitive coupling with a gate wiring pattern.

Next, a 0.3 μm thick SiO ₂ layer 7x serving as a second insulating layer is formed on the gate electrode 5 by sputtering, and a 0.2 μm thick C ₂ O ₂ layer serving as a gate wiring pattern is formed.
An r layer 6x was formed (FIGS. 4D and 5D).

The Cr layer 6x was patterned by photolithography to form a line-shaped gate wiring pattern 6 having a width of 3 μm (FIGS. 4 (e) and 5 (e)).

Next, an opening a having a diameter of 3 μm for providing an emitter electrode is formed on the emitter wiring pattern 2 by photolithography, thereby forming the second insulating layer 7.
(FIG. 4 (f) and FIG. 5 (f)).

Next, the first insulating layer 4 was formed by etching the SiO ₂ layer 4x serving as the first insulating layer by photolithography to provide an opening a reaching the emitter wiring pattern 2 (FIG. 4 ( g) and FIG. 5 (g)). At that time, the inner wall of the opening a was side-etched by 0.2 μm.

Next, an Al layer 8 having a thickness of 0.5 μm serving as a lift-off layer was formed from the direction of about 15 ° with respect to the silicon substrate (1) by a rotary evaporation method. At this time, the opening diameter of the opening a is reduced (see FIG. 4H and FIG. 5).
(H)).

Next, by evaporating Mo from the vertical direction of the silicon substrate (1), the emitter electrode 3 having a sharp tip was formed in the opening a (FIG. 4 (i) and FIG. 5).
(I)). At this time, the Mo layer 9 was also formed on the Al layer 8.

Finally, the Al layer 8 is selectively etched and removed by the lift-off method, and at the same time, the Mo layer 9 thereon is removed.
Was removed. Thus, an electron-emitting device of the present invention as shown in FIGS. 4 (j) and 5 (j) was obtained.

[0060]

According to the present invention, when one pixel is constituted by a plurality of electron-emitting devices, even if the gate electrode and the emitter electrode of one electron-emitting device are short-circuited, another electron-emitting device is used. An adverse effect on the electron-emitting device can be prevented. Therefore, the pixel does not become defective as a whole. Therefore, when the electron-emitting device of the present invention is used, FEA
Can be improved, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of an electron-emitting device of the present invention.

FIG. 2 is a plan view of a gate electrode of the electron-emitting device of the present invention.

FIG. 3 is a plan view of the electron-emitting devices of the present invention arranged in an array.

FIG. 4 is a manufacturing process diagram of the electron-emitting device of the present invention.

FIG. 5 is a manufacturing process diagram of the electron-emitting device of the present invention.

FIG. 6 is a cross-sectional view of a conventional electron-emitting device.

FIG. 7 is a schematic perspective view of a conventional electron-emitting device.

FIG. 8 is a manufacturing process diagram of a conventional electron-emitting device.

FIG. 9 is a cross-sectional view of a conventional electron-emitting device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Emitter wiring pattern 3 Emitter electrode 4 First insulating layer 5 Gate electrode 6 Gate wiring pattern 7 Second insulating layer

Claims (5)

(57) [Claims] An emitter wiring pattern, an emitter electrode provided thereon, a first insulating layer provided on the emitter wiring pattern so as to surround the emitter electrode, and an emitter electrode provided on the first insulating layer. In a field emission type electron-emitting device including a gate electrode provided so as to surround an emitter electrode, a gate wiring pattern for applying a voltage to the gate electrode is electrically connected to the gate electrode by a capacitive coupling method. A field emission type electron-emitting device, which is disposed on the gate electrode via a second insulating layer. 2. The field emission electron-emitting device according to claim 1, wherein the emitter wiring pattern is formed on an insulating substrate. 3. The field emission type electron-emitting device according to claim 1, wherein the emitter wiring pattern itself functions as a support substrate. 4. The field emission type electron-emitting device according to claim 3, wherein the emitter wiring pattern is made of a silicon substrate. 5. The field emission electron-emitting device according to claim 1, wherein the emitter electrode is a cone-shaped electrode having a sharp tip or a disk-shaped electrode having a flat surface.