JPH0748346B2 - Field emission cold cathode device - Google Patents

Field emission cold cathode device

Info

Publication number
JPH0748346B2
JPH0748346B2 JP31050892A JP31050892A JPH0748346B2 JP H0748346 B2 JPH0748346 B2 JP H0748346B2 JP 31050892 A JP31050892 A JP 31050892A JP 31050892 A JP31050892 A JP 31050892A JP H0748346 B2 JPH0748346 B2 JP H0748346B2
Authority
JP
Japan
Prior art keywords
insulating layer
emitter
substrate
electrode
cold cathode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP31050892A
Other languages
Japanese (ja)
Other versions
JPH06162919A (en
Inventor
秀男 巻島
裕則 井村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31050892A priority Critical patent/JPH0748346B2/en
Publication of JPH06162919A publication Critical patent/JPH06162919A/en
Publication of JPH0748346B2 publication Critical patent/JPH0748346B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子放出源となる冷陰
極、特に鋭利な先端から電子を放出する電界放出冷陰極
素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cold cathode which serves as an electron emission source, and more particularly to a field emission cold cathode device which emits electrons from a sharp tip.

【0002】[0002]

【従来の技術】微小な円錐状のエミッタと、エミッタの
すぐ近くに形成され、電流引き出しならびに電流制御機
能を持つゲート電極で構成された微小冷陰極をアレイ状
に並べた冷陰極(Journal of Applie
d Physics,Vol.47,No.12,p
p.5248,1976)が提案されている。このスピ
ント型冷陰極は、熱陰極と比較して高い電流密度が得ら
れ、放出電子の速度分散が小さい等の利点を持つ。ま
た、単一の電界放出エミッタと比較して電流雑音が小さ
く、数10〜200Vの低い電圧で動作し、比較的悪い
真空度の環境中でも動作するとされている。
2. Description of the Related Art Cold cathodes (Journal of Applies) in which microscopic cold cathodes composed of a minute conical emitter and a gate electrode formed in the immediate vicinity of the emitter and having a current extraction and current control function are arranged in an array form
d Physics, Vol. 47, No. 12, p
p. 5248, 1976) has been proposed. This Spindt-type cold cathode has advantages that a higher current density can be obtained and the velocity dispersion of emitted electrons is smaller than that of a hot cathode. Further, it is said that the current noise is smaller than that of a single field emission emitter, it operates at a low voltage of several tens to 200 V, and it operates even in an environment of relatively poor vacuum degree.

【0003】図7には、従来技術であるスピント型冷陰
極の1個の微小冷陰極の構造を示している。101は導
電性の基板で、この上に微小な円錐状のエミッタ102
が膜堆積法によって形成され、エミッタ102の周囲に
は、絶縁層103とゲート電極104が形成されてい
る。基板101とエミッタ102とは、電気的に接続さ
れており、基板101(およびエミッタ102)とゲー
ト電極104の間には、約100Vの電圧が印加され
る。基板101とゲート電極104の間は、約1μmと
狭く、エミッタ102の先端は、きわめて鋭利に作られ
ているので、エミッタ102の先端には、強い電界が加
わる。この電界が2〜5×107 V/cm以上になる
と、エミッタ102の先端から電子が放出される。
FIG. 7 shows the structure of one minute cold cathode of the Spindt-type cold cathode of the prior art. Reference numeral 101 denotes a conductive substrate on which a minute conical emitter 102 is formed.
Is formed by a film deposition method, and an insulating layer 103 and a gate electrode 104 are formed around the emitter 102. The substrate 101 and the emitter 102 are electrically connected, and a voltage of about 100 V is applied between the substrate 101 (and the emitter 102) and the gate electrode 104. The distance between the substrate 101 and the gate electrode 104 is as narrow as about 1 μm, and the tip of the emitter 102 is made extremely sharp, so that a strong electric field is applied to the tip of the emitter 102. When the electric field becomes 2 to 5 × 10 7 V / cm or more, electrons are emitted from the tip of the emitter 102.

【0004】このような構造の微小冷陰極を基板101
上にアレイ状に並べることにより、大きな電流を放出す
る面状の陰極が構成される。
The micro cold cathode having such a structure is used as the substrate 101.
By arranging them in an array on top, a planar cathode that emits a large current is formed.

【0005】なお、図7において、1点鎖線および2点
鎖線は、それぞれ絶縁層の下から10%および50%の
位置から形成される等電位線を示し、数字は、この等電
位線の電位の基板とエミッタ間の電圧V0 に対する割合
を示す。絶縁層103は、均一であるから、絶縁層の下
から10%および50%の位置から形成される等電位線
の電位は、それぞれ0.1V0 、0.5V0 となる。
In FIG. 7, the alternate long and short dash line and the alternate long and two short dashes line indicate the equipotential lines formed from the positions of 10% and 50% from the bottom of the insulating layer, respectively, and the numerals indicate the potentials of these equipotential lines. The ratio of V to the voltage V 0 between the substrate and the emitter is shown. Insulating layer 103, since a uniform potential of equipotential lines formed between 10% and 50% of the positions from the bottom of the insulating layer are respectively 0.1 V 0, becomes 0.5V 0.

【0006】図8は、グレイ型と呼ばれる電界放出冷陰
極の従来技術(特開平4−94033号公報)の製法と
構造を示している。図8において、110は絶縁膜マス
クパターン、111はシリコン基板、112はシリコン
熱酸化膜、113は絶縁膜、114はゲート電極、11
5はエミッタである。基本的な動作は、図7に示すスピ
ント型と同様であるが、エミッタ115がシリコン基板
111と同一材料で一体化されているところが異なる。
この冷陰極を製作するには、ゲート電極114の開口と
ほぼ同じ大きさの絶縁膜マスクパターン110を通して
シリコン基板111の等方的エッチングを行い、円錐状
のエミッタ115を形成する(図8(c))。
FIG. 8 shows a manufacturing method and structure of a conventional technique (Japanese Patent Laid-Open No. 4-94033) of a field emission cold cathode called a gray type. In FIG. 8, 110 is an insulating film mask pattern, 111 is a silicon substrate, 112 is a silicon thermal oxide film, 113 is an insulating film, 114 is a gate electrode, 11
5 is an emitter. The basic operation is similar to that of the Spindt type shown in FIG. 7, except that the emitter 115 is integrated with the silicon substrate 111 by the same material.
In order to manufacture this cold cathode, the silicon substrate 111 is isotropically etched through the insulating film mask pattern 110 having substantially the same size as the opening of the gate electrode 114 to form the conical emitter 115 (FIG. 8C). )).

【0007】次に、エミッタ115を含むシリコン基板
111の表面を熱酸化し、熱酸化膜112を形成する
(図8(d))。その後、絶縁膜113とゲート電極1
14を堆積し(図8(e))、エミッタ115部分の熱
酸化膜および絶縁膜マスクパターン110の除去(図8
(f))、ゲート電極114のパターニングによって図
8(g)に示す構造を得る。
Next, the surface of the silicon substrate 111 including the emitter 115 is thermally oxidized to form a thermal oxide film 112 (FIG. 8 (d)). Then, the insulating film 113 and the gate electrode 1
14 is deposited (FIG. 8E), and the thermal oxide film and the insulating film mask pattern 110 in the emitter 115 portion are removed (FIG. 8E).
(F)) By patterning the gate electrode 114, the structure shown in FIG.

【0008】熱酸化膜112をエミッタ115の部分に
形成し、これを除去することによって、等方性エッチン
グでは実現できない鋭い先端のエミッタを、高い精度で
形成することができる。絶縁膜113は、ゲート電極1
14のエミッタ先端に対する位置を適正に設定する厚さ
に選ばれる。図8に示す従来例では、尖った先端のエミ
ッタを高精度で、再現性良く製作する製法としたため
に、2層構造の絶縁層となったもので、本発明のように
絶縁層を誘電率の異なった多層化する目的で熱酸化膜1
12と絶縁膜119を形成したものではない。
By forming the thermal oxide film 112 on the emitter 115 and removing it, an emitter having a sharp tip, which cannot be realized by isotropic etching, can be formed with high accuracy. The insulating film 113 is the gate electrode 1
The thickness is selected so as to properly set the position of 14 with respect to the tip of the emitter. In the conventional example shown in FIG. 8, since the emitter having a sharp tip is manufactured with high accuracy and good reproducibility, the insulating layer has a two-layer structure. Thermal oxide film 1 for the purpose of making different layers
12 and the insulating film 119 are not formed.

【0009】図9は、スピント型陰極を変形した横型の
電界放出冷陰極の公知例(Technical Dig
est of IVMC 91,pp.46,199
1)の構造である。図9において、石英の絶縁基板11
6上の第1の面に平面状のエミッタ117が形成され、
絶縁基板116の第1の面から僅かに低い第2の面上に
平面状のゲート電極119が形成されている。図には示
さないが、エミッタ117は、櫛歯状に加工され、多く
の角あるいは稜が形成されている。エミッタ117の先
端とゲート電極119の先端は、極めて接近して形成さ
れているので、エミッタ117に対しゲート電極119
に正の電圧が印加すると、エミッタ117の先端付近か
ら電子が放出される。
FIG. 9 is a known example of a lateral field emission cold cathode obtained by modifying a Spindt-type cathode (Technical Dig).
est of IVMC 91, pp. 46,199
It is the structure of 1). In FIG. 9, an insulating substrate 11 made of quartz is used.
6, a planar emitter 117 is formed on the first surface on 6,
A planar gate electrode 119 is formed on a second surface slightly lower than the first surface of the insulating substrate 116. Although not shown in the figure, the emitter 117 is processed into a comb shape and has many corners or edges. Since the tip end of the emitter 117 and the tip end of the gate electrode 119 are formed extremely close to each other, the gate electrode 119 and
When a positive voltage is applied to, electrons are emitted from the vicinity of the tip of the emitter 117.

【0010】[0010]

【発明が解決しようとする課題】エミッタ102とゲー
ト電極104の間の電圧(以下、ゲート電圧と呼ぶ)
は、エミッタ102とゲート電極104の間の絶縁性に
影響を及ぼし、長時間の陰極の安定性に影響するため、
ゲート電圧は、可能な限り低いことが望ましい。また、
陰極放出電流は、ゲート電圧によって制御されるので、
半導体集積回路等の出力でゲート電極104を制御する
ためには、同様にゲート電圧を低くすることが望まし
い。
A voltage between the emitter 102 and the gate electrode 104 (hereinafter referred to as a gate voltage).
Influences the insulating property between the emitter 102 and the gate electrode 104 and affects the stability of the cathode for a long time.
It is desirable that the gate voltage be as low as possible. Also,
The cathode emission current is controlled by the gate voltage, so
In order to control the gate electrode 104 with the output of a semiconductor integrated circuit or the like, it is desirable to similarly lower the gate voltage.

【0011】さらに、このような構造のエミッタ102
の先端の電子放出部を衝撃する正イオンは、エミッタ1
02の極近傍(数μm以内)で発生したものであるた
め、正イオンの衝撃エネルギーは、主にゲート電圧で決
定される。また、正イオンの衝撃によって生じるエミッ
タ102先端の機械的変形は、加速電圧が100V以下
になると、ゲート電圧の低下とともに大幅に低下するの
で、エミッタ102の長寿命化と、真空度に関する耐環
境性の改善にも、ゲート電圧の低減は重要である。
Further, the emitter 102 having such a structure.
The positive ions that impact the electron emission part at the tip of the
Since it is generated in the vicinity of 02 (within several μm), the impact energy of positive ions is mainly determined by the gate voltage. Further, the mechanical deformation of the tip of the emitter 102, which is caused by the impact of positive ions, is drastically reduced as the gate voltage is lowered when the accelerating voltage is 100 V or less. Therefore, the life of the emitter 102 is extended and the environment resistance related to the degree of vacuum is improved. The reduction of the gate voltage is also important for improving.

【0012】ゲート電圧を低減する方法には、エミッ
タの先端を先鋭にし、円錐の頂角を小さくする方法(T
hird International Vacuum
Microelectronics Confere
nce, KeynoteAddress,1990、
特開平4−94033号公報)、スケーリング則に基
づき微小冷陰極全体の構造を小さくする方法(Thir
d International Vacuum Mi
croelectronics Conferenc
e, Keynote Address,1990)、
エミッタ本体あるいは先端あるいはエミッタ表面を仕
事関数の小さい材料とする方法(特開平3−18711
9号公報、特開昭51−21471号公報、特開昭51
−54358号公報)等が提案されている。
To reduce the gate voltage, the tip of the emitter is sharpened and the apex angle of the cone is reduced (T
hird International Vacuum
Microelectronics Confere
nce, Keynote Address, 1990,
Japanese Patent Laid-Open No. 4-94033), a method for reducing the structure of the entire micro cold cathode based on the scaling rule (Thir).
d International Vacuum Mi
croelectronics Conference
e, Keynote Address, 1990),
A method of using a material having a small work function for the emitter body, tip, or emitter surface (Japanese Patent Laid-Open No. 3-18711).
No. 9, JP-A-51-21471, JP-A-51
No. 54,358) has been proposed.

【0013】エミッタの先端を先鋭にすると、正イオン
衝撃による特性変化を伴い易くなり、円錐の頂角を小さ
くすると、エミッタ102先端で発生した熱の放散が低
下して先端の温度上昇が大きくなり、エミッタ当りの最
大放出電流が制限される。全体の構造を小さくするに
は、素子を製作するのに高精度の微細加工システムが必
要になり、均一性、歩留まり等の問題の発生する可能性
がある。また、採用できるエミッタ材料は、素子の製作
プロセス、使用環境等の要因で制限される。
If the tip of the emitter is sharpened, the characteristics are likely to change due to positive ion bombardment, and if the apex angle of the cone is made smaller, the heat dissipation at the tip of the emitter 102 is reduced and the temperature rise of the tip is increased. , The maximum emission current per emitter is limited. In order to reduce the size of the entire structure, a highly accurate microfabrication system is required to manufacture the device, which may cause problems such as uniformity and yield. Further, the emitter material that can be used is limited by factors such as the element manufacturing process and the operating environment.

【0014】本発明の目的は、エミッタ先端付近の電界
強度を上げ、同一電流を放出するゲート電圧を低下さ
せ、正イオン衝撃によるエミッタ先端の機械的変形を低
減した電界放出冷陰極素子を提供することにある。
An object of the present invention is to provide a field emission cold cathode device in which the electric field strength near the emitter tip is increased, the gate voltage for emitting the same current is lowered, and the mechanical deformation of the emitter tip due to positive ion bombardment is reduced. Especially.

【0015】[0015]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る電界放出冷陰極素子は、基板と、電子
放出電極と、絶縁層と、制御電極とを有する電界放出冷
陰極素子であって、基板は、導電性をもつ基板、或いは
絶縁性材料上に導電層を積層した基板であり、電子放出
電極は、前記基板上に錐状に立上って形成され、かつ基
板に電気的に接続されたものであり、絶縁層は、電子放
出電極の周囲を取囲み、誘電率の異なる多層に形成さ
れ、前記基板に近い絶縁層の誘電率は、他の絶縁層のも
のより小さいものであり、制御電極は、絶縁層上に積層
形成され、前記電子放出電極を取囲む開口を有するもの
である。
In order to achieve the above object, a field emission cold cathode device according to the present invention is a field emission cold cathode device having a substrate, an electron emission electrode, an insulating layer, and a control electrode. The substrate is a substrate having conductivity or a substrate in which a conductive layer is laminated on an insulating material, and the electron emission electrode is formed in a pyramidal shape on the substrate and is electrically connected to the substrate. The insulating layer surrounds the periphery of the electron emission electrode and is formed in multiple layers having different dielectric constants, and the dielectric constant of the insulating layer close to the substrate is smaller than that of other insulating layers. The control electrode is laminated on the insulating layer and has an opening surrounding the electron emission electrode.

【0016】また、前記積層層のうち、基板に近く誘電
率が他の絶縁層より小さい絶縁層は、他の絶縁層よりも
薄い膜厚を有するものである。
Of the laminated layers, the insulating layer close to the substrate and having a dielectric constant smaller than that of the other insulating layers has a smaller film thickness than the other insulating layers.

【0017】また、本発明に係る電界放出冷陰極素子
は、薄膜型電子放出電極と、制御電極と、絶縁体とを有
する電界放出冷陰極素子であって、薄膜型電子放出電極
は、電子を放出するものであり、制御電極は、電子放出
電極に電子を引き出す電圧を印加するものであり、絶縁
体は、少なくとも2以上の絶縁体からなり、電子放出電
極と制御電極とを分離するものであり、電子放出電極に
近い絶縁体の誘電率は、他の絶縁体より小さいものであ
る。
The field emission cold cathode device according to the present invention is a field emission cold cathode device having a thin film type electron emission electrode, a control electrode and an insulator, and the thin film type electron emission electrode emits electrons. The control electrode applies a voltage for extracting electrons to the electron emission electrode, and the insulator is composed of at least two insulators and separates the electron emission electrode from the control electrode. The dielectric constant of the insulator close to the electron emission electrode is smaller than that of other insulators.

【0018】[0018]

【作用】本発明においては、基板とゲート電極の間の絶
縁層を誘電率の異なる少なくとも2層構造とし、基板あ
るいはエミッタ側に誘電率の小さい絶縁材料を、ゲート
電極側に誘電率の大きい絶縁材料を使用する。
In the present invention, the insulating layer between the substrate and the gate electrode has at least a two-layer structure with different permittivities, an insulating material with a low permittivity is provided on the substrate or emitter side, and an insulator with a high permittivity is provided on the gate electrode side. Use material.

【0019】この結果、エミッタの先端付近の電界強度
が均一絶縁層の場合と比較して大きくなるので、同一放
出電流を得るのに、低いゲート電圧で良い。このため、
正イオンがゲート電圧で加速されてエミッタの電子放出
部を衝撃しても、エミッタ先端の機械的変形が発生する
可能性は、小さくなり、長時間にわたり電気的特性変化
の小さい安定な動作が期待できる。また、エミッタとゲ
ート電極の間の漏洩電流の増加する可能性が小さくな
り、安定な動作が期待できる。更に、放出電流制御のた
めの信号電圧振幅を小さくできるので、ゲート電極等を
駆動する外部回路の負荷が小さくなるという利点もあ
る。
As a result, the electric field strength in the vicinity of the tip of the emitter becomes larger than that in the case of the uniform insulating layer, so that a low gate voltage is sufficient to obtain the same emission current. For this reason,
Even if positive ions are accelerated by the gate voltage and impact the electron emission part of the emitter, the possibility that mechanical deformation of the emitter tip will occur will be small, and stable operation with little change in electrical characteristics over a long time is expected. it can. In addition, the possibility of increase in leakage current between the emitter and the gate electrode is reduced, and stable operation can be expected. Furthermore, since the signal voltage amplitude for controlling the emission current can be reduced, there is an advantage that the load of the external circuit that drives the gate electrode and the like is reduced.

【0020】[0020]

【実施例】本発明の実施例を図面を参照して詳細に説明
する。
Embodiments of the present invention will be described in detail with reference to the drawings.

【0021】(実施例1)図1は、本発明の第1の実施
例を示す電界放出冷陰極素子の構造図である。図1にお
いて、1は導電性の基板、2は電子を放出する円錐状の
エミッタであり、エミッタ2は、基板1と電気的に接続
されている。3は第1絶縁層、4は第2絶縁層、5はゲ
ート電極である。
(Embodiment 1) FIG. 1 is a structural view of a field emission cold cathode device showing a first embodiment of the present invention. In FIG. 1, 1 is a conductive substrate, 2 is a conical emitter that emits electrons, and the emitter 2 is electrically connected to the substrate 1. Reference numeral 3 is a first insulating layer, 4 is a second insulating layer, and 5 is a gate electrode.

【0022】通常の動作中においては、基板1と同電位
のエミッタ2に対し、ゲート電極5には、数10Vの正
の電圧が印加されている。エミッタ2の先端は、極めて
鋭利に形成され、エミッタ2の先端とゲート電極5と
は、極めて近接した位置にあるため、エミッタ2の先端
には、強い電界が加わり、ここから電子が放出される。
1個のエミッタ2と、この周囲にあるゲート電極5の開
口5aとにより微小冷陰極が構成され、単一の微小冷陰
極あるいは複数の微小冷陰極の集合が冷陰極となる。
During normal operation, a positive voltage of several tens of volts is applied to the gate electrode 5 with respect to the emitter 2 having the same potential as the substrate 1. The tip of the emitter 2 is formed to be extremely sharp, and the tip of the emitter 2 and the gate electrode 5 are extremely close to each other. Therefore, a strong electric field is applied to the tip of the emitter 2 to emit electrons. .
A micro cold cathode is constituted by one emitter 2 and the opening 5a of the gate electrode 5 around the emitter 2, and a single micro cold cathode or a set of a plurality of micro cold cathodes serves as a cold cathode.

【0023】基板1とゲート電極5の間の絶縁層は、第
1絶縁層3と第2絶縁層4との2層構造になっており、
第1絶縁層3は比誘電率3.9のシリコン酸化膜(Si
2)、第2絶縁層4は比誘電率7.5のシリコン窒化
膜(Si3 4 )で構成している。
The insulating layer between the substrate 1 and the gate electrode 5 has a two-layer structure of a first insulating layer 3 and a second insulating layer 4,
The first insulating layer 3 is a silicon oxide film (Si having a relative dielectric constant of 3.9).
O 2 ) and the second insulating layer 4 are composed of a silicon nitride film (Si 3 N 4 ) having a relative dielectric constant of 7.5.

【0024】いま、基板1とゲート電極5の間の電圧を
0 、基板1とゲート電極5の間の距離、すなわち全体
の絶縁層の厚さをtとし、第1絶縁層3の両端の電圧、
厚さ、比誘電率をそれぞれV1 、ta1 、ε1 、また第
1絶縁層3中の電界をE1 とする。同様に第2絶縁層4
の電圧、厚さ、比誘電率、電界をそれぞれV2 、ta2
(=t(1−a1 ))、ε2 、E2 とする。この時、第
1絶縁層3の電界E1、電圧V1 は、それぞれ次式で表
される。 E1 =V0 /{t・[1−(1−a1 )(1−ε1 /ε2 )]} …(1) V1 =V0 ・a1 /[1−(1−a1 )(1−ε1 /ε2 )] …(2) 第1絶縁層3と第2絶縁層4との厚さが等しい(a1
0.5)とした時、 E1 =1.32V0 /t V1 =0.66V0 となる。
Now, assuming that the voltage between the substrate 1 and the gate electrode 5 is V 0 , the distance between the substrate 1 and the gate electrode 5, that is, the thickness of the entire insulating layer is t, both ends of the first insulating layer 3 are Voltage,
The thickness and relative permittivity are V 1 , ta 1 , and ε 1 , respectively, and the electric field in the first insulating layer 3 is E 1 . Similarly, the second insulating layer 4
Voltage, thickness, relative permittivity, and electric field of V 2 and ta 2 respectively.
(= T (1-a 1 )), ε 2 , E 2 . At this time, the electric field E 1 and the voltage V 1 of the first insulating layer 3 are expressed by the following equations, respectively. E 1 = V 0 / {t · [1- (1-a 1) (1-ε 1 / ε 2)]} ... (1) V 1 = V 0 · a 1 / [1- (1-a 1 ) (1-ε 1 / ε 2 )] (2) The first insulating layer 3 and the second insulating layer 4 have the same thickness (a 1 =
When 0.5), and E 1 = 1.32V 0 / t V 1 = 0.66V 0.

【0025】一方、絶縁層の誘電率が均一である場合、
すなわちε1 =ε2 の場合(a1 =0.5)、 E1 =1.0V0 /t V1 =0.5V0 となり、第1絶縁層3では、電圧も電界も絶縁層が均一
である場合に比較して30%以上高い値となる。
On the other hand, when the dielectric constant of the insulating layer is uniform,
That is, when ε 1 = ε 2 (a 1 = 0.5), E 1 = 1.0V 0 / t V 1 = 0.5V 0 , and the first insulating layer 3 has uniform voltage and electric field. The value is 30% or more higher than that in the case of.

【0026】図1において、1点鎖線および2点鎖線
は、それぞれ絶縁層の下から10%および50%の位置
から形成される等電位線を示し、数字は、この等電位線
の電位の基板とエミッタ間の電圧V0 に対する割合を示
す。図7の従来技術の等電位線の電位と比較して、同じ
10%の位置から形成される等電位線の電位は1.3倍
になっている。
In FIG. 1, the alternate long and short dash line and the alternate long and two short dashes line show the equipotential lines formed from the positions of 10% and 50% from the bottom of the insulating layer, respectively, and the numeral indicates the substrate of the potential of these equipotential lines. And the voltage V 0 between the emitter and the emitter are shown. The potential of the equipotential line formed from the same 10% position is 1.3 times the potential of the conventional equipotential line in FIG.

【0027】図1の実施例の場合、エミッタ2の周囲の
絶縁層のうち、基板1に近い部分の電界は、同様に絶縁
層全体が均一である従来技術と比較して1.3倍になっ
ている。絶縁層に挾まれ、エミッタ2が収められた空間
における電界も、この絶縁層中の電界を強く反映し、基
板1の表面およびエミッタ2の表面付近の電界も、均一
の絶縁層の場合と比較して大きくなる。同じゲート電圧
で電界が30%高くなることから、同じ電界を実現する
には、印加するゲート電圧は約25%低い値で良いこと
になる。
In the case of the embodiment shown in FIG. 1, the electric field in the portion of the insulating layer around the emitter 2 close to the substrate 1 is 1.3 times as large as that in the conventional technique in which the entire insulating layer is also uniform. Has become. The electric field in the space in which the emitter 2 is housed, which is sandwiched by the insulating layer, strongly reflects the electric field in this insulating layer, and the electric fields near the surface of the substrate 1 and the surface of the emitter 2 are also compared with the case of a uniform insulating layer. And grow bigger. Since the electric field is 30% higher at the same gate voltage, the gate voltage applied may be about 25% lower in order to realize the same electric field.

【0028】また、式(1)から明らかなように、均一
の絶縁層の場合と比較して、第1絶縁層3の誘電率が小
さく、第1絶縁層と第2絶縁層の誘電率の比が大きいほ
ど、また、第1絶縁層3の厚さが薄いほど、エミッタ先
端付近の電界が強くなり、ゲート電圧を低減できる。
As is clear from the equation (1), the dielectric constant of the first insulating layer 3 is smaller than that of the uniform insulating layer, and the dielectric constants of the first insulating layer and the second insulating layer are The larger the ratio and the smaller the thickness of the first insulating layer 3, the stronger the electric field near the tip of the emitter and the lower the gate voltage.

【0029】(実施例2)図2は、本発明の実施例2を
示す断面図である。図2において、図1の構成要素と同
じものについては、同じ符号を付してある。図2におい
て、第1絶縁層3の厚さが0.1t、第2絶縁層4の厚
さが0.9tであることが、図1とは異なる。すなわ
ち、絶縁層のうち基板1と接する最下部10%がシリコ
ン酸化膜(第1絶縁層3)で、残り90%がシリコン窒
化膜(第2絶縁層4)である。この場合、1点鎖線で示
す絶縁層の最下端から10%の位置から形成される等電
位線の電位は、0.18V0 、第1絶縁層3中の電界E
1 は、0.18で、均一絶縁層の場合と比較して約1.
8倍となる。したがって、同じ電界を形成する均一絶縁
層の素子と比較して、約40%のゲート電圧を削減でき
る。
(Embodiment 2) FIG. 2 is a sectional view showing Embodiment 2 of the present invention. 2, the same components as those of FIG. 1 are designated by the same reference numerals. 2 is different from FIG. 1 in that the thickness of the first insulating layer 3 is 0.1 t and the thickness of the second insulating layer 4 is 0.9 t. That is, the lowermost 10% of the insulating layer in contact with the substrate 1 is the silicon oxide film (first insulating layer 3), and the remaining 90% is the silicon nitride film (second insulating layer 4). In this case, the potential of the equipotential line formed from the position of 10% from the lowermost end of the insulating layer indicated by the one-dot chain line is 0.18 V 0 , and the electric field E in the first insulating layer 3 is
1 is 0.18, which is about 1.2 as compared with the case of the uniform insulating layer.
8 times. Therefore, the gate voltage can be reduced by about 40% as compared with a device having a uniform insulating layer that forms the same electric field.

【0030】図3は、本発明の第1および第2の実施例
を示す電界放出素子の製造方法を工程順に示す断面図で
ある。まず図3(a)に示すように、基板1上に、第1
絶縁層3、第2絶縁層4、ゲート電極5となる薄膜層を
順次所定の厚さ、たとえば第1の実施例の場合、第1絶
縁層3を0.5μm、第2絶縁層4を0.5μm、ゲー
ト電極5を0.2μmに積層する。
3A to 3D are sectional views showing a method of manufacturing the field emission device showing the first and second embodiments of the present invention in the order of steps. First, as shown in FIG.
The insulating layer 3, the second insulating layer 4, and the thin film layers to be the gate electrode 5 are sequentially formed to a predetermined thickness, for example, in the case of the first embodiment, the first insulating layer 3 is 0.5 μm and the second insulating layer 4 is 0. 0.5 μm, and the gate electrode 5 is laminated to 0.2 μm.

【0031】次に図3(b)に示すように、ゲート電極
5上にゲート開口とほぼ同じ大きさの開口を持つレジス
トパターンを形成し、このレジストを通してリアクティ
ブイオンエッチングにより、ゲート電極5、第2絶縁層
4、第1絶縁層3に穴をあける。この時、ゲート電極5
とエミッタ2との間の耐圧を高くするため、第2絶縁層
4と第1絶縁層3は、わずかにオーバーエッチされるよ
うな条件で加工する。
Next, as shown in FIG. 3B, a resist pattern having an opening having substantially the same size as the gate opening is formed on the gate electrode 5, and reactive ion etching is performed through the resist to form the gate electrode 5, A hole is formed in the second insulating layer 4 and the first insulating layer 3. At this time, the gate electrode 5
In order to increase the breakdown voltage between the emitter 2 and the emitter 2, the second insulating layer 4 and the first insulating layer 3 are processed under the condition that they are slightly overetched.

【0032】次に図3(c)に示すように、ウェハ全体
を回転させながら、斜め方向から犠牲層6を積層し、ゲ
ート電極5上および開口5aの側面に犠牲層6を形成す
る。
Next, as shown in FIG. 3C, while sacrificing the entire wafer, the sacrificial layer 6 is laminated in an oblique direction to form the sacrificial layer 6 on the gate electrode 5 and on the side surface of the opening 5a.

【0033】次に図3(d)に示すように、モリブデ
ン、ダングステン等のエミッタ金属材料を蒸着によって
堆積すると、犠牲層6上にエミッタ金属層7が形成さ
れ、これと同時に基板1の上には、ゲート開口5aに対
応した位置に円錐状のエミッタ2が形成される。次に図
3(e)に示すように、犠牲層6とエミッタ金属層7を
除去する。
Next, as shown in FIG. 3D, when an emitter metal material such as molybdenum or dangsten is deposited by vapor deposition, an emitter metal layer 7 is formed on the sacrificial layer 6, and at the same time, on the substrate 1. The conical emitter 2 is formed at a position corresponding to the gate opening 5a. Next, as shown in FIG. 3E, the sacrificial layer 6 and the emitter metal layer 7 are removed.

【0034】なお、第1および第2の実施例では、基板
1は、金属あるいは半導体のような導電体としたが、絶
縁体上に導電性薄膜を形成した基板でも同様に使用でき
る。
In the first and second embodiments, the substrate 1 is made of a conductor such as metal or semiconductor, but a substrate having a conductive thin film formed on an insulator can also be used.

【0035】(実施例3)図4は、本発明の第3の実施
例を示す電界放出素子の構造図である。図4は、製法な
らびに構造を図8に示す従来の電界放出素子に本発明を
適用した一実施例であり、8はエミッタ2の先端を形成
する過程で必要な熱酸化膜である。この図に示すような
3層以上の多層絶縁層構造の場合も、エミッタ2の先端
の電界強度は、最下層の熱酸化膜8中の電界が強く影響
する。第1絶縁層3および第2絶縁層4の誘電率と厚さ
を考慮した加重平均誘電率と、第1絶縁層3および第2
絶縁層4の厚さの和をもつ単一の絶縁層と仮定して、熱
酸化膜8中の電界を式(1)から求めることができる。
したがって、加重平均誘電率がエミッタ2と接触する最
下層の絶縁層よりも大きければ、本発明の効果を実現で
きる。
(Embodiment 3) FIG. 4 is a structural view of a field emission device showing a third embodiment of the present invention. FIG. 4 shows an embodiment in which the present invention is applied to the conventional field emission device whose manufacturing method and structure are shown in FIG. 8, and 8 is a thermal oxide film required in the process of forming the tip of the emitter 2. Also in the case of a multi-layered insulating layer structure of three or more layers as shown in this figure, the electric field strength at the tip of the emitter 2 is strongly influenced by the electric field in the thermal oxide film 8 of the lowermost layer. A weighted average dielectric constant considering the dielectric constants and thicknesses of the first insulating layer 3 and the second insulating layer 4, and the first insulating layer 3 and the second insulating layer 4.
The electric field in the thermal oxide film 8 can be calculated from the equation (1) assuming that the insulating layer 4 is a single insulating layer having the sum of the thicknesses.
Therefore, the effect of the present invention can be realized if the weighted average dielectric constant is larger than that of the lowermost insulating layer in contact with the emitter 2.

【0036】図4に示す電界放出素子を製作するには、
図8において絶縁層113を堆積する工程を2段階に分
け、異なる絶縁材料たとえばシリコン窒化物、チタン酸
化物(比誘電率約100)を順次堆積すれば良い。
To manufacture the field emission device shown in FIG.
In FIG. 8, the step of depositing the insulating layer 113 is divided into two steps, and different insulating materials such as silicon nitride and titanium oxide (relative dielectric constant of about 100) may be sequentially deposited.

【0037】なお、第3の実施例では、基板と同一材料
のエミッタを形成する場合を説明したが、第1および第
2の実施例のような堆積法によってエミッタを形成した
場合にも、3層以上の絶縁層に対して同じ考え方が適用
できる。
In the third embodiment, the case where the emitter made of the same material as that of the substrate is formed has been described. However, even when the emitter is formed by the deposition method as in the first and second embodiments, the case where the emitter is formed is 3 The same idea can be applied to more than one insulating layer.

【0038】(実施例4)図5は、本発明の第4の実施
例を示す電界放出素子の構造図である。図5において、
16は絶縁基板、17は薄膜状のエミッタ、18は絶縁
基板16とエミッタ17の間に形成した第1絶縁層、1
9はゲート電極で、図9に示す従来の構造と比較して、
絶縁基板16とエミッタ17の間に第1絶縁層18が追
加されている点が異なる。エミッタ17の先端とゲート
電極19とは、極めて近くに形成されており、エミッタ
17の角あるいは稜には、強い電界が印加されるので、
ここから電子が放出される。絶縁基板16は、比誘電率
約4の石英を用い、第1絶縁層18には、比誘電率約2
の多孔質シリコン酸化膜を用いている。この場合にも、
誘電率の小さい第1絶縁層18の中の電界は、第1絶縁
層18と絶縁基板16とが同一の材料で作られた図7に
示す従来例と比較して大きくなり、エミッタ17の先端
近くの電界も強くなる。
(Embodiment 4) FIG. 5 is a structural view of a field emission device showing a fourth embodiment of the present invention. In FIG.
16 is an insulating substrate, 17 is a thin film emitter, 18 is a first insulating layer formed between the insulating substrate 16 and the emitter 17, 1
Reference numeral 9 is a gate electrode, which is different from the conventional structure shown in FIG.
The difference is that a first insulating layer 18 is added between the insulating substrate 16 and the emitter 17. The tip of the emitter 17 and the gate electrode 19 are formed very close to each other, and a strong electric field is applied to the corner or edge of the emitter 17,
Electrons are emitted from here. The insulating substrate 16 is made of quartz having a relative dielectric constant of about 4, and the first insulating layer 18 is made of quartz having a relative dielectric constant of about 2.
The porous silicon oxide film is used. Also in this case,
The electric field in the first insulating layer 18 having a small dielectric constant is larger than that in the conventional example shown in FIG. 7 in which the first insulating layer 18 and the insulating substrate 16 are made of the same material, and the tip of the emitter 17 is The nearby electric field also becomes stronger.

【0039】(実施例5)図6は、本発明の第5の実施
例を示す電界放出素子の構造図である。図6における各
構成要素の名称は、図1の同じ番号の構成要素と同じで
ある。エミッタ2は、導電性の基板1上に形成され、矩
形状の断面となっている。エミッタ2とゲート電極5
は、狭いギャップを介して対面しており、ゲート電極の
角あるいは稜に強い電界が印加され、ここから電子が放
出される。ゲート電極5と基板1の間の絶縁層は、第1
絶縁層3と第2絶縁層4とで構成され、第1絶縁層3は
シリコン酸化膜、第2絶縁層4はシリコン窒化膜で作ら
れている。誘電率の小さい第1絶縁層3中の電界は、均
一な絶縁層の電界よりも強くなり、エミッタ2の電子放
電部にも強い電界が加わる。
(Embodiment 5) FIG. 6 is a structural view of a field emission device showing a fifth embodiment of the present invention. The names of the constituent elements in FIG. 6 are the same as the constituent elements with the same numbers in FIG. The emitter 2 is formed on the conductive substrate 1 and has a rectangular cross section. Emitter 2 and gate electrode 5
Face each other through a narrow gap, and a strong electric field is applied to the corner or edge of the gate electrode, and electrons are emitted from this. The insulating layer between the gate electrode 5 and the substrate 1 is the first
It is composed of an insulating layer 3 and a second insulating layer 4, the first insulating layer 3 is made of a silicon oxide film, and the second insulating layer 4 is made of a silicon nitride film. The electric field in the first insulating layer 3 having a small dielectric constant is stronger than the electric field in the uniform insulating layer, and a strong electric field is also applied to the electron discharge part of the emitter 2.

【0040】なお、本発明は、ゲート電圧低減のために
従来から提案されている方法と組み合わせて採用して
も、それぞれが効果を示すので、これらを組み合わせて
採用すれば、大きなゲート電圧低減効果が得られる。
Even if the present invention is used in combination with the method conventionally proposed for reducing the gate voltage, each of them exhibits its effect. Therefore, if these methods are used in combination, a large gate voltage reducing effect can be obtained. Is obtained.

【0041】絶縁材料として、シリコン酸化膜、多孔質
シリコン酸化膜、シリコン窒化物、チタン酸化物の例を
示したが、これら以外の絶縁材料でも、本発明の思想を
適用できるのは明らかである。
Although examples of the silicon oxide film, the porous silicon oxide film, the silicon nitride, and the titanium oxide have been shown as the insulating material, it is obvious that the concept of the present invention can be applied to other insulating materials. .

【0042】また、実施例では、絶縁層が2種類および
3種類の絶縁材料で構成されている例を示したが、4種
類以上の絶縁材料で構成された場合にも本発明が適用さ
れる。また、誘電率が連続的に変化する絶縁層であって
も、基板あるいはエミッタ近くの誘電率が小さく、ゲー
ト電極近くの誘電率が大きければ、本発明の思想が適用
されることは明らかである。
Further, in the embodiment, the example in which the insulating layer is made of two kinds and three kinds of insulating materials is shown, but the present invention is also applied to the case of being made of four kinds or more of insulating materials. . Further, even in the case of an insulating layer whose permittivity changes continuously, it is clear that the idea of the present invention is applied if the permittivity near the substrate or the emitter is small and the permittivity near the gate electrode is large. .

【0043】さらに、誘電率変化が連続的であるかある
いは不連続的であるかにかかわらず、層の途中の誘電率
の変化が、基板あるいはエミッタ近くで誘電率が小さ
く、ゲート電極付近で誘電率が大きいという原則に部分
的に一致しなくとも、エミッタ近くの絶縁層とこれ以外
の絶縁層の加重平均誘電率とを比較して、エミッタ近く
の絶縁層の誘電率が他の絶縁層の平均誘電率よりも小さ
ければ本発明が適用されることは明らかである。
Further, regardless of whether the change in permittivity is continuous or discontinuous, the change in permittivity in the middle of the layer is such that the permittivity is small near the substrate or the emitter and near the gate electrode. Even if it does not partially match the principle that the dielectric constant is large, the dielectric constant of the insulating layer near the emitter is compared with that of the other insulating layers by comparing the weighted average dielectric constants of the insulating layers near the emitter with other insulating layers. Obviously, the present invention can be applied if it is smaller than the average dielectric constant.

【0044】[0044]

【発明の効果】以上説明したように本発明の冷陰極にお
いては、エミッタの先端を特別に先鋭化したり、微小陰
極の形状を小型化したり、エミッタに特別の材料を使用
したりせずに、同一電流を放出するゲート電圧を低減で
きる。また、本発明では、従来の製作法を大幅に変更せ
ず、しかも素子構造・製造法を複雑にせずに製作でき
る。
As described above, in the cold cathode of the present invention, the tip of the emitter is not particularly sharpened, the shape of the microcathode is miniaturized, and no special material is used for the emitter. The gate voltage that discharges the same current can be reduced. Further, according to the present invention, it is possible to manufacture without significantly changing the conventional manufacturing method and without complicating the element structure and manufacturing method.

【0045】この結果、エミッタ−ゲート間の絶縁低下
に伴う不安定性の発生可能性が低下し、正イオンのエミ
ッタ電子放出部衝撃によるエミッタ先端の機械的変形の
発生が大幅に減少し、長時間の動作が可能になる。更
に、放出電流を制御するゲート電極駆動回路の負荷を軽
減することができる。
As a result, the possibility of instability due to the reduction of the insulation between the emitter and the gate is reduced, and the mechanical deformation of the tip of the emitter due to the impact of the positive electron on the emitter electron-emitting portion is greatly reduced, and the Can be operated. Further, the load on the gate electrode drive circuit that controls the emission current can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す冷陰極素子の構造
を示す図である。
FIG. 1 is a diagram showing a structure of a cold cathode device according to a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す冷陰極素子の構造
を示す図である。
FIG. 2 is a diagram showing a structure of a cold cathode device according to a second embodiment of the present invention.

【図3】本発明の第1、第2の実施例を示す冷陰極素子
の構造を示す図である。
FIG. 3 is a view showing a structure of a cold cathode device showing first and second embodiments of the present invention.

【図4】本発明の第3の実施例を示す冷陰極素子の構造
を示す図である。
FIG. 4 is a diagram showing a structure of a cold cathode device showing a third embodiment of the present invention.

【図5】本発明の第4の実施例を示す冷陰極素子の構造
を示す図である。
FIG. 5 is a diagram showing a structure of a cold cathode device according to a fourth embodiment of the present invention.

【図6】本発明の第5の実施例を示す冷陰極素子の構造
を示す図である。
FIG. 6 is a diagram showing a structure of a cold cathode device according to a fifth embodiment of the present invention.

【図7】従来例の構造を示す図である。FIG. 7 is a diagram showing a structure of a conventional example.

【図8】従来例の構造を示す図である。FIG. 8 is a diagram showing a structure of a conventional example.

【図9】従来例の構造を示す図である。FIG. 9 is a diagram showing a structure of a conventional example.

【符号の説明】[Explanation of symbols]

1 基板 2 エミッタ 3 第1絶縁膜 4 第2絶縁膜 5 ゲート電極 6 犠牲層 7 エミッタ金属層 8 熱酸化膜 16 絶縁基板 17 エミッタ 18 第1絶縁層 19 ゲート電極 101 基板 102 エミッタ 103 絶縁層 104 ゲート電極 110 絶縁膜マスクパターン 111 シリコン基板 112 熱酸化膜 113 絶縁膜 114 ゲート電極 115 エミッタ 116 絶縁基板 117 エミッタ 119 ゲート電極 1 Substrate 2 Emitter 3 First Insulating Film 4 Second Insulating Film 5 Gate Electrode 6 Sacrificial Layer 7 Emitter Metal Layer 8 Thermal Oxide Film 16 Insulating Substrate 17 Emitter 18 First Insulating Layer 19 Gate Electrode 101 Substrate 102 Emitter 103 Insulating Layer 104 Gate Electrode 110 Insulating film mask pattern 111 Silicon substrate 112 Thermal oxide film 113 Insulating film 114 Gate electrode 115 Emitter 116 Insulating substrate 117 Emitter 119 Gate electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板と、電子放出電極と、絶縁層と、制
御電極とを有する電界放出冷陰極素子であって、 基板は、導電性をもつ基板、或いは絶縁性材料上に導電
層を積層した基板であり、 電子放出電極は、前記基板上に錐状に立上って形成さ
れ、かつ基板に電気的に接続されたものであり、 絶縁層は、電子放出電極の周囲を取囲み、誘電率の異な
る多層に形成され、前記基板に近い絶縁層の誘電率は、
他の絶縁層のものより小さいものであり、 制御電極は、絶縁層上に積層形成され、前記電子放出電
極を取囲む開口を有するものであることを特徴とする電
界放出冷陰極素子。
1. A field emission cold cathode device having a substrate, an electron emission electrode, an insulating layer, and a control electrode, wherein the substrate is a conductive substrate or a conductive layer is laminated on an insulating material. The electron emission electrode is formed in a pyramidal shape on the substrate and electrically connected to the substrate, and the insulating layer surrounds the periphery of the electron emission electrode, The dielectric constant of an insulating layer formed in multiple layers having different dielectric constants and close to the substrate is
A field emission cold cathode device, which is smaller than those of other insulating layers, wherein the control electrode is laminated on the insulating layer and has an opening surrounding the electron emitting electrode.
【請求項2】 前記積層層のうち、基板に近く誘電率が
他の絶縁層より小さい絶縁層は、他の絶縁層よりも薄い
膜厚を有するものであることを特徴とする請求項1に記
載の電界放出冷陰極素子。
2. The insulating layer of the laminated layer, which is closer to the substrate and has a dielectric constant smaller than that of the other insulating layers, has a thickness smaller than that of the other insulating layers. The field emission cold cathode device described.
【請求項3】 薄膜型電子放出電極と、制御電極と、絶
縁体とを有する電界放出冷陰極素子であって、 薄膜型電子放出電極は、電子を放出するものであり、 制御電極は、電子放出電極に電子を引き出す電圧を印加
するものであり、 絶縁体は、少なくとも2以上の絶縁体からなり、電子放
出電極と制御電極とを分離するものであり、電子放出電
極に近い絶縁体の誘電率は、他の絶縁体より小さいもの
であることを特徴とする電界放出冷陰極素子。
3. A field emission cold cathode device having a thin film type electron emission electrode, a control electrode, and an insulator, wherein the thin film type electron emission electrode emits electrons, and the control electrode is an electron. A voltage for extracting electrons is applied to the emission electrode, and the insulator is composed of at least two insulators and separates the electron emission electrode from the control electrode. The dielectric of the insulator close to the electron emission electrode is used. The field emission cold cathode device is characterized in that its rate is smaller than that of other insulators.
JP31050892A 1992-11-19 1992-11-19 Field emission cold cathode device Expired - Fee Related JPH0748346B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31050892A JPH0748346B2 (en) 1992-11-19 1992-11-19 Field emission cold cathode device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31050892A JPH0748346B2 (en) 1992-11-19 1992-11-19 Field emission cold cathode device

Publications (2)

Publication Number Publication Date
JPH06162919A JPH06162919A (en) 1994-06-10
JPH0748346B2 true JPH0748346B2 (en) 1995-05-24

Family

ID=18006072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31050892A Expired - Fee Related JPH0748346B2 (en) 1992-11-19 1992-11-19 Field emission cold cathode device

Country Status (1)

Country Link
JP (1) JPH0748346B2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000215787A (en) 1999-01-21 2000-08-04 Nec Corp Field emission type cold cathode element, its manufacture and image display device
US7449081B2 (en) 2000-06-21 2008-11-11 E. I. Du Pont De Nemours And Company Process for improving the emission of electron field emitters
US7161285B2 (en) 2000-11-20 2007-01-09 Nec Corporation CNT film and field-emission cold cathode comprising the same
KR100730108B1 (en) * 2001-02-15 2007-06-19 삼성에스디아이 주식회사 Electron gun applying cold cathode
US7276844B2 (en) 2001-06-15 2007-10-02 E. I. Du Pont De Nemours And Company Process for improving the emission of electron field emitters
JP2005310724A (en) * 2003-05-12 2005-11-04 Sumitomo Electric Ind Ltd Field emission type electron source and manufacturing method for it
JP4507557B2 (en) * 2003-10-28 2010-07-21 ソニー株式会社 Method for manufacturing electron-emitting device and method for manufacturing display device
JP2006253100A (en) * 2005-02-10 2006-09-21 Sony Corp Electron/ion source device, its manufacturing method, display device, and its manufacturing method
KR101107134B1 (en) * 2005-08-26 2012-01-31 삼성에스디아이 주식회사 Electron emission element, electron emission device and method of manufacturing the same
JP5158224B2 (en) * 2011-04-11 2013-03-06 日本電気株式会社 Emitter manufacturing method, field emission cold cathode using the emitter, and flat image display device

Also Published As

Publication number Publication date
JPH06162919A (en) 1994-06-10

Similar Documents

Publication Publication Date Title
US6144144A (en) Patterned resistor suitable for electron-emitting device
US5666019A (en) High-frequency field-emission device
JP2576760B2 (en) Micro field emission cold cathode and manufacturing method thereof
US6204597B1 (en) Field emission device having dielectric focusing layers
US5828163A (en) Field emitter device with a current limiter structure
US6630781B2 (en) Insulated electrode structures for a display device
US5702281A (en) Fabrication of two-part emitter for gated field emission device
US5404070A (en) Low capacitance field emission display by gate-cathode dielectric
EP0501785A2 (en) Electron emitting structure and manufacturing method
US5378182A (en) Self-aligned process for gated field emitters
KR100235212B1 (en) A field emission cathode and maunfacture thereof
JPH0748346B2 (en) Field emission cold cathode device
KR100243990B1 (en) Field emission cathode and method for manufacturing the same
US5969467A (en) Field emission cathode and cleaning method therefor
US5628663A (en) Fabrication process for high-frequency field-emission device
JP3266503B2 (en) Optimal gate control design and fabrication method for lateral field emission device
US6246069B1 (en) Thin-film edge field emitter device
JP2737618B2 (en) Field emission type electron source
JP2625366B2 (en) Field emission cold cathode and method of manufacturing the same
JP3156903B2 (en) Field emission type electron source
US20130342098A1 (en) Corrugated Dielectric for Reliable High-current Charge-emission Devices
JP3144475B2 (en) Method of manufacturing field emission cold cathode
JPH0652788A (en) Field emission type electron source device and its manufacture
WO2003073480A2 (en) Emission layer formed by rapid thermal formation process
JP4093997B2 (en) Anodizing method for improving electron emission in electronic devices

Legal Events

Date Code Title Description
S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees