JPH11162157A - Memory device and image generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FIFO(first-in first-out) type memory device whose laitancy which is the number of waiting cycles from the application to the output of data is smaller and, further, provide a image processing device in which data can be transferred instantaneously by each processing means and hence a required image can be processed efficiently. SOLUTION: Separately from that data stored in an input register 110 are stored in a RAM 120, the data are shited successively in intermediate registers 131 and 132. Respective data in an output register 140 in which data read out of the respective registers and the RAM 120 are stored can be selected by a data selection circuit 150. When a read request is given at a time 1 cycle after the data input, 2 cycles after the data input, 3 cycles after the data input or 4 or more cycles after the data input, the data in the input register 110, the data in the 1st intermediate register 131, the data in the 2nd intermediate register 132 or the data in the output register 140 are respectively selected and outputted. With this constitution, the data can be outputted immediately in response to the read request.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
It is called FIFO (First In First Out) format. The present invention relates to a memory device and an image generating device capable of efficiently generating a three-dimensional image using the FIFO memory device.

[0002]

2. Description of the Related Art A so-called FIFO memory for reading input data in the order of input is widely used in various electronic circuits. In particular, in recent years, the processing speed has been improved in all electronic devices, and as a result, the processing speed of data between processing units may be different, or it may be difficult to transfer data in an appropriate synchronization. In order to solve this problem, a FIFO memory is frequently provided as a buffer between the processing units. For example, an image processing device that generates a three-dimensional image used for a CAD device, a game device, or the like performs a predetermined process on a large number of pixels at high speed, such as coordinate conversion, texture mapping, and special effect processing for each pixel. Various processing units to be performed are sequentially connected. A large number of FIFO memories are used to perform high-speed and appropriate data transfer between these processing units.

There are various types of such FIFO memories, but those having relatively few storage stages, for example, those having a storage word number of about 4 words or about 8 words,
In many cases, a register is used as a storage element. Further, the number of storage stages larger than that, for example, 32 words or 64
Those having a storage capacity such as a word often use a memory such as a dual-port RAM as a storage element. For example, such a FIFO memory using a dual-port RAM as a storage element generally includes an input register for temporarily storing input data, a dual-port RAM for actually storing data, and a temporary storage for output data. Output register and dual port RAM
And a control unit that controls the

[0004]

However, in such a FIFO memory, usually, input data cannot be read immediately, so that data cannot be efficiently and appropriately transferred between the processing devices. There is a problem that there is.

[0005] For example, the aforementioned dual port RAM
In a FIFO memory using, data is applied to an input terminal, data is set in an input register in the next cycle, data is stored in a dual-port RAM in a second cycle, and the data is stored in a third cycle. The data is read, and the data is set in the output register and output to the outside in the fourth cycle. Therefore, when data is transferred via the FIFO memory, the data can be used only in the fourth cycle after the data is applied to the input portion of the FIFO memory.

In a case where a considerable number of data are input and a sufficient number of data are stored in the FIFO memory and then the data is read out, such a wait cycle number (hereinafter referred to as latency) is used. There is no problem at all, but when it is desired to process the input data as soon as possible as soon as possible, it is a serious problem that the data is input and the four-cycle processing is waited. In the case where data reading can be performed at relatively high speed and data input is discrete, if the value of this latency is large, it is necessary to wait several cycles each time each data is used. There is also a problem that efficiency is deteriorated. In addition, if the value of the latency is large, it is necessary to consider the timing at which valid data can be actually read from the FIFO memory in order to perform a precise circuit design, which causes a problem that the circuit design becomes difficult.

[0007] In the image generating apparatus as described above,
It is necessary to process a large amount of pixel data in real time, and it is necessary to immediately and efficiently process the data generated in the preceding processing. However, when a FIFO memory having a large latency is used as a data transfer unit between the processing units, a problem occurs that a wasteful data waiting time occurs and a desired process cannot be efficiently performed. Therefore, in such an image generating apparatus, there is a demand for using a FIFO memory having a lower latency.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a FIFO type memory device in which the latency, which is the number of wait cycles from when data is applied to when it is output, is small. It is another object of the present invention to provide an image processing apparatus capable of immediately transferring data in each processing means and thereby efficiently performing desired image processing.

[0009]

In order to solve the above-mentioned problems, during a period from when data is applied to a memory circuit until the data can be read out, the data is stored in another register. Then, the data stored in the register is output.

Therefore, a memory device according to the present invention comprises: a memory circuit for sequentially storing input data in a plurality of storage areas; a memory reading means for reading data stored in the memory circuit in the order of input on demand; A shift register in which a predetermined number of registers based on the number of cycles from when the data to be stored is applied to when it is read out are connected so as to sequentially shift the data to be stored applied to the memory circuit; Any one of the input data, the data stored in each of the shift registers, or the data read from the memory circuit so that the input data is immediately output in the input order. Output data selection means for selecting and outputting one.

In such a memory device, while sequentially input data is stored in the memory circuit, the data is shifted in the shift register until the data stored in the memory circuit can be output. deep. When data output is requested and the data can be immediately read from the memory circuit, data from the memory circuit read by the memory reading means is selected and output by the data selecting means. . When the data cannot be immediately read from the memory circuit, the data is stored in one of the shift registers, and the data is selected and output by the data selection means.

Another memory device of the present invention has an input register for storing data to be input, and a plurality of storage areas, each of which is independently accessible and can be accessed in the next cycle after the data to be stored is applied. A first memory circuit and a second memory circuit capable of outputting the data,
Storage control means for storing the data stored in the input register in one of the first memory circuit and the second memory circuit, and storing the data stored in the first memory circuit and the second memory circuit as required. It has read control means for reading data in the order of input, and an output register for storing the read data.

In such a memory device, input data is temporarily stored in an input register, and then stored in either the first memory circuit or the second memory circuit by the storage control means. The data stored in the first memory circuit or the second memory circuit can be immediately read in the next cycle after the cycle to which the data is applied, that is, in the stored cycle. Therefore, even if the data read via the read control means is once stored and output in the output register, the data is output in the second cycle after the data is applied to the memory device. Further, since this memory device has the first and second memory circuits, the storage control means and the read control means access different memory circuits so that data storage and reproduction can be performed simultaneously. Will be

Further, the image generating apparatus of the present invention is capable of
Coordinate conversion means for performing a predetermined coordinate conversion on the vertices of the basic polygon of the three-dimensional image data in which the three-dimensional model is represented by a set of basic polygons indicated by vertices having at least three-dimensional position information; Pixel data generating means for generating the basic polygonal pixel data based on the data of the vertices, a FIFO memory for sequentially storing the generated pixel data, and sequentially reading each generated pixel data from the FIFO memory; Texture mapping means for performing texture mapping using a desired texture pattern to generate three-dimensional image data for display, an image memory for storing the generated three-dimensional image data for display, and stored three-dimensional image data for display Output means for reading out data of a more desired area and outputting it as screen data for display, As serial FIFO memory, having a memory device of the present invention.

In this image generating apparatus, first, coordinate conversion means applies three-dimensional image data represented as a set of basic polygons of an arbitrary three-dimensional solid model to the vertices of the basic polygon. A desired coordinate conversion is performed on the data, and each pixel data is generated by a pixel data generation unit based on the data of the vertices of the converted basic polygon. The generated pixel data is sequentially
The data is input to the texture mapping unit via the O memory, texture-mapped using a desired texture pattern, and stored in a predetermined image memory. Then, data in a desired area is read out from the stored image data and output for display.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the present invention relates to a three-dimensional computer graphics system for displaying a desired three-dimensional image of an arbitrary three-dimensional object model applied to a home game machine or the like at a high speed on a display. The case where the FIFO type memory device is applied will be described.

First, a three-dimensional computer graphics system to which the memory device of the present invention is applied will be described with reference to FIG. In this three-dimensional computer graphics system, a three-dimensional model is expressed as a combination of triangles (polygons) as unit figures,
This system performs a polygon rendering process of determining the color of each pixel on the display screen by drawing the polygon and displaying the color on the display. In addition, in the three-dimensional computer graphics system 1, a three-dimensional object is represented using z coordinates representing depth in addition to (x, y) coordinates representing a plane, and three coordinates of x, y, and z are used. Specifies an arbitrary point in the three-dimensional space.

FIG. 1 is a block diagram showing the configuration of the three-dimensional computer graphics system 1. The three-dimensional computer graphics system 1 includes an input unit 2, a three-dimensional image generation device 3, and a display device 4.
Further, the three-dimensional image generation device 3 includes a geometry calculation unit 3
2. Parameter calculation unit 33, pixel generation unit 34, FIFO
It has a memory device 100, a mapping unit 35, a texture memory 36, a memory control unit 37, an image memory 38, and a display control unit 39.

First, the configuration and function of each unit will be described. The input unit 2 inputs data of a three-dimensional model to be displayed to the three-dimensional image generation device 3. In this embodiment, since the three-dimensional computer graphics system 1 is applied to a home game machine, the input unit 2
Is connected to a main controller for controlling the game itself of the home game machine. The main controller determines the screen to be displayed based on the progress of the game, etc.
A three-dimensional model required for the screen display is selected, and information on the display method is generated. Therefore, the input unit 2 receives the information from the main control device of the consumer game machine,
The image is converted into a form suitable for input to the three-dimensional image generation device 3 and input to the three-dimensional image generation device 3. Specifically, the input unit 2 inputs the polygon data of the three-dimensional model to be displayed as described above to the geometry calculation unit 32 of the three-dimensional image generation device 3. The input polygon data is x, y, z coordinate data of each vertex and accompanying data such as color, transparency, and texture.

The geometry calculation unit 32 arranges the polygon input from the input unit 2 at a desired position in the three-dimensional space, and generates polygon data at that position. Specifically, for each vertex (x, y, z) of the polygon, a geometric transformation process (also referred to as a geometry transformation process) such as a translation transformation, a parallel transformation, and a rotation transformation is performed. The polygon data subjected to the geometry conversion processing is output to the parameter calculation unit 33.

The parameter calculator 33 is required for the pixel generator 34 to generate pixel data inside the polygon based on the polygon data input from the geometry calculator 32, that is, the data of each vertex of the polygon. The parameters are obtained and output to the pixel generator 34. Specifically, for example, information on color, depth, and texture inclination is obtained.

The pixel generator 34 is provided with a geometry calculator 32.
Based on the polygon data subjected to the geometry conversion processing in step (1) and the parameters calculated by the parameter calculation unit 33, linear interpolation is performed between the vertices of the polygon to generate pixel data of the inside and the edge of the polygon. In addition, the pixel generation circuit 34 has a predetermined 2 corresponding to the display of the pixel data.
Generate addresses on a dimensional plane. The generated pixel data and addresses are sequentially stored in the FIFO memory device 100.
Is input to

The FIFO memory device 100 is a buffer that sequentially stores pixel data and addresses generated by the pixel generator 34 and is sequentially read from the mapping unit 35 in the order of input. And especially this FIFO memory device 10
Reference numeral 0 denotes a FIFO memory device with a latency of 1 that can read the data from the mapping unit 35 immediately after the next cycle after the data is input from the pixel generation unit 34. The configuration of the FIFO memory device 100 will be described later in detail.

The mapping unit 35 reads out the pixel data and the address generated by the pixel generation unit 34 from the FIFO memory device 100, and uses the texture data stored in the texture memory 36 for the pixel data. Perform mapping processing. The pixel data and address after the texture mapping process are
Output to the memory control unit 37.

The texture memory 36 stores the mapping unit 3
5 is a memory for storing texture patterns used when performing texture mapping.

The memory control unit 37 generates new pixel data based on the pixel data and address input from the mapping unit 35 and the corresponding pixel data already stored in the image memory 38, 38
To memorize. That is, the memory control unit 37 reads the pixel data corresponding to the address input from the mapping unit 35 from the image memory 38, and uses the pixel data and the pixel data input from the mapping unit 35,
A desired pixel calculation process is performed, and the obtained pixel data is written to the image memory 38. When a display area is designated by the display control unit 39, the memory control unit 37 reads out pixel data of the display area from the image memory 38 and outputs the pixel data to the display control unit 39.

The image memory 38 is a memory for recording image data for display, and has two memory buffers, a frame buffer and a Z buffer, which can be accessed simultaneously. Frame data, which is color information of each pixel, is stored in the frame buffer. The Z buffer stores Z data as depth information (Z value) of each pixel.

The display control section 39 converts the pixel data of the display area read from the image memory 38 via the memory control section 37 into, for example, a predetermined analog signal which can be displayed on the display device 4 and outputs it to the display device 4. I do. Prior to this, the display control unit 39 requests the memory control unit 37 for pixel data of a display area to be displayed.

In the present embodiment, the display device 4 is
This is a television receiver having a video input terminal and the like generally used in homes and the like. 3D image generation device 3
An analog video signal is input from the display control unit 39 via a video signal input terminal, and a three-dimensional image is displayed on a screen based on the signal.

Next, the operation of the three-dimensional computer graphics system 1 will be described. First, when a three-dimensional image to be displayed is determined in a main control device or the like that controls the game itself of the home-use game machine, information on a three-dimensional model required for displaying the screen is input to the input unit 2. Based on this information, the input unit 2 converts the polygon data of the three-dimensional model for displaying the image into a three-dimensional image generating device 3.
To enter. Each polygon data input to the three-dimensional image generation device 3 is first processed by the geometry calculation unit 32.
Geometry transformation processing such as translation, parallel transformation, and rotation transformation is performed so as to be arranged at a desired position in a three-dimensional space for screen display.

Next, for the polygon data subjected to the coordinate conversion, parameters necessary for generating pixel data inside the polygon are obtained in the parameter calculation unit 33, and the pixel generation unit 34 actually calculates the polygon data. Pixel data of the inside of the polygon and the edge portion is generated by linearly interpolating between the vertices. The generated pixel data is
The input pixel data is sequentially input to the mapping unit 35 via the FO memory device 100, and the mapping unit 35 performs texture mapping processing with reference to the texture pattern data recorded in the texture memory 36, and generates pixel data. Image memory 38 via control unit 37
Is stored.

The pixel data stored in the image memory 38 is appropriately subjected to a desired process based on other pixel data input through a similar route or arbitrary control data. As a result, the latest image data is always stored in the image memory 38 and used for screen display. That is, a request to output data in a predetermined area to be displayed on the display device 4 is made from the display control unit 39 to the memory control unit 37, and pixel data in that area is read from the image memory 38 as appropriate. The display control section 39 converts the signal into a predetermined signal for screen display and outputs the signal to the display device 4. Thereby, a desired image is displayed on the screen of the display device 4.

Next, the FIFO memory device 100 will be described with reference to FIGS. As previously mentioned,
In the three-dimensional computer graphics system 1, each component sequentially performs predetermined processing to generate desired image data for screen display. However, output and processing of processing result data between the components are performed. Requests for the data of interest are not made synchronously. Specifically, the mapping unit 35 performs the texture mapping process on the pixel data generated by the pixel generation unit 34. The timing at which the pixel generation unit 34 generates the pixel data and the processing performed by the mapping unit 35 The request timing of the target pixel data does not match. Therefore, in order to absorb the timing difference, the FIFO memory device 100 is provided between the pixel generator 34 and the mapping unit 35.

FIG. 2 shows a configuration of the FIFO memory device 100 suitable for application to such a three-dimensional computer graphics system 1. FIFO memory device 10
0 is an input register (REG1) 110, a dual-port RAM (Dport RAM) 120, a first intermediate register (REG2) 131, and a second intermediate register (RE
G3) 132, output register (REG4) 140, selection circuit (MUX) 150, write pointer unit (Wpointer)
160, write ready signal generation unit (WRDY Gen) 17
0, a read pointer section (Rpointer) 180 and a read ready signal generation section (RRDY Gen) 190.

First, the configuration and function of each unit will be described. The input register 110 stores the FIFO memory device 100
Is a register for temporarily storing the data DATAin input to the register, and stores the input data DATAin at the rising timing of the clock CLK when the write enable signal WE is active. The data stored in the input register 110 is stored in the dual port RAM 120, the first
Are output to the intermediate register 131 and the selection circuit 150.

The dual-port RAM 120 is a 32-bit × 64-word memory capable of simultaneously writing and reading, and sequentially records data input through the input register 110. Dual port RAM1
The data RAM 20 stored in the input register 110 is applied to its data input terminal, and the data is sequentially stored in the storage area of the dual port RAM 120 based on a write control signal from the write pointer unit 160. You. The data stored in the dual port RAM 120 is read out and output from the data output terminals in the order in which they are stored, based on a read control signal from the read pointer unit 180.

In the dual port RAM 120,
These storage and read operations are performed at the same time as completely separate and independent operations. If the applied data is output immediately in the dual port RAM 120, the data is stored in the next cycle in which the data is applied, and is read out in the next cycle. That is, the dual port RAM 120 has a latency of 2
Memory.

The first intermediate register 131 and the second intermediate register 132 are registers for sequentially storing the data stored in the input register 110. As shown, the first intermediate register 131 and the second intermediate register 132 are connected in series to the input register 110, and constitute a shift register together with the input register 110. Therefore, the data applied to the input register 110 is sequentially transmitted to the first intermediate register 131 and the second intermediate register 131.
Is shifted to the intermediate register 132. The output of each register including the input register 110 is supplied to the selection circuit 150.
Is also output. Therefore, input register 110
Is applied to the input register 110 by being shifted through these shift registers.
Until the cycle, the data is output to the selection circuit 150 via any of these registers.

The output register 140 stores the data RAMo read from the dual port RAM 120 based on the read control signal output from the read pointer section 180.
ut is stored and output to the selection circuit 150. As described above, the latency of the dual port RAM 120 is 2
Therefore, the input register 110 and the output register 140
, The data is applied to the input register 110 and then the dual port RA
It takes at least four cycles before the data is output from the output register 140 via M120.

The selection circuit 150 includes a read pointer unit 18
Based on the selection signal SEL input from 0, any one of the input data is selected and output as output data DATAout from the FIFO memory device 100. The selection circuit 150 stores the data stored in the input register 110, the data stored in the first intermediate register 131, the data stored in the second intermediate register 132, and the data stored in the output register 140. Are input. As described above, these data are data one cycle after being applied to the input register 110, data two cycles after, and
The data after the cycle and the data after four cycles. Therefore, the selection circuit 150 selects and outputs any of the four data based on when the data requested to be read is applied to the FIFO memory device 100, that is, the input register 110.

That is, when the requested data is the data just applied to the input register 110 one cycle before, the data output from the input register 110 is selected, and the data applied to the input register 110 two cycles before is selected. Sometimes, the data output from the first intermediate register 131 is selected, and when the data is applied to the input register 110 three cycles before, the data output from the second intermediate register 132 is selected. In the case of data applied to the input register 110, the normal dual port RAM 1 output from the output register 140
20. The data read from 20 is selected.

The write pointer section 160 generates a storage control signal for the dual port RAM 120 based on the write enable signal WE input to the FIFO memory device 100, and controls the storage of data in the dual port RAM 120. Also, the write pointer unit 160
Controls the storage of data in the input register 110, the first intermediate register 131, and the second intermediate register 132 based on the write enable signal WE.
Note that the write pointer section 160 is valid only when a write ready signal generation section 170 described later is in a writable state.

The write ready signal generation unit 170
This is a circuit that generates a write ready signal WRDY indicating whether data can be further stored in the O memory device 100. The write ready signal generation unit 170 is generated based on the write address and the read address for the dual port RAM 120 managed by the write pointer unit 160 and the read pointer unit 180, and the transition state thereof.

The read pointer section 180 receives a dual port RA based on a read enable signal RE which is a read request signal input to the FIFO memory device 100.
A read control signal for M120 is generated and applied to dual port RAM 120. Thereby, desired data is read from the dual port RAM 120 and output to the output register 140. Note that the read pointer unit 1
80 is valid only when a read-ready signal generation unit 190 described later is in a readable state and when the read enable signal RE is input simultaneously with the write enable signal WE.

The read pointer unit 180 outputs a selection signal SEL to the selection circuit 150 based on the relationship between the cycle in which the read enable signal RE is input and the cycle in which the data to be output is input to the FIFO memory device 100. It is generated and output to the selection circuit 150. That is, how many cycles before the data to be output
10 based on whether the data applied to input register 1
10. A signal for selecting data output from one of the first intermediate register 131, the second intermediate register 132, and the output register 140 is applied to the selection circuit 150.

The read ready signal generation unit 190
This is a circuit for generating a read ready signal RRDY indicating whether or not there is data to be read in the O memory device 100. The read ready signal generation unit 190 is generated based on the write address and the read address for the dual port RAM 120 managed by the write pointer unit 160 and the read pointer unit 180, and the transition state thereof.

Next, the operation of the FIFO memory device 100 will be described with reference to FIG. In FIG. 3, the signal C
LK is an operation clock of the FIFO memory device 100, a signal DATAin is input data to the FIFO memory device 100 and data applied to the input register 110,
The signal WE is a write enable signal for the FIFO memory device 100, and the signal RAMin (REGout) is stored in the input register 110 and is stored in the dual port RAM 120.
And the signal REG2out is the data stored in the first intermediate register 131 and the signal RET.
3out is the data stored in the second intermediate register 132, and the signal REG4out is the dual port RAM1
Data read from the memory 20 and stored in the output register 140, a signal RE is a read enable signal for the FIFO memory device 100, and a signal SEL is a selection circuit 150.
And the signal DATAout are output signals from the FIFO memory device 100. It should be noted that the numbers above the clock CLK are numbers indicating the respective cycles added for ease of explanation.

For FIFO memory device 100, as in cycle 1, for example, write enable signal WE
Is set high, and data D0 to be stored is applied to the input terminal, whereby data is stored. The input data D0 is the clock CL between cycle 1 and cycle 2.
At the rise of K, the data is stored in the input register 110.
Are output to the intermediate register 131 and the selection circuit 150. Then, in the next cycle 3, the data D0 stored in the input register 110 is stored in the dual port RAM 120.

The data D0 stored in the input register 110 is stored in the dual port RAM 120 at the same time as the first intermediate register 131 in cycle 3.
Is shifted to Further, the data D0 stored in the first intermediate register 131 is supplied to the second
Is shifted to the intermediate register 132. On the other hand, the data stored in the dual port RAM 120 in cycle 3 is read out from the dual port RAM 120 in cycle 4 and applied to the output register 140, and the data stored in cycle 5
And stored in the output register 140
It is output to the selection circuit 150.

Therefore, in the selection circuit 150,
In cycle 2, as the output of the input register 110, in cycle 3, as the output of the first intermediate register 131, in cycle 4, as the output of the second intermediate register 132, and in cycle 5, as the output of the output register 140, In any case, the data D0 can be selected. The data stored in the output register 140 is data that is sequentially read from the dual-port RAM 120 and updated according to the read enable signal RE. Thereafter, the data D0 continues to be output. That is, FIF
At any time after the next step after the data D0 is applied to the O memory device 100, the selection circuit 150 outputs the data D0.
Can be selected and output.

In cycle 2, data D1
Is applied to the FIFO memory device 100, but since the write enable signal WE is at a low level,
The data D1 is not substantially input to the input register 110. Since the write enable signal WE is active again after cycle 3, the sequentially input data D2, D3, D4,... Are first stored in the input register 110 in the same manner as described above. At the same time as being stored in the RAM 120, the first intermediate register 131 and the second intermediate register 132 are sequentially shifted.

In the state where data is sequentially stored in this manner, a read enable signal RE which is a data read signal is input to the FIFO memory device 100, for example, in cycle 1. Then, the read pointer unit 180
Detects a register in which data to be output is stored based on the read enable signal RE, and selects a selection signal SE for selecting output data from the register.
L is output to the selection circuit 150. The data to be output is the data that has been input first among the data that has not been read yet that has been input to the FIFO memory device 100. In this case, the data to be input in cycle 1 This is the data D0 applied to the FIFO memory device 100.

In response to the read enable signal RE input in the cycle 1, the read pointer unit 180 controls the register in which the data D0 is stored in the cycle 2,
That is, a selection signal SEL for selecting the input register 110 is generated and output to the selection circuit 150. As a result, in cycle 2, the data D0 stored in the input register 110 is selected by the selection circuit 150,
Output from the FIFO memory device 100.

Thereafter, similarly, read enable signal RE
Is input, the read pointer unit 180 generates a selection signal SEL based on the relationship between the input cycle of the read enable signal RE and the input cycle of data to be output, and the selection circuit 150 selects the data. You. For example, for read enable signal RE input in cycle 4, first intermediate register 131 is selected by selection circuit 150, and in cycle 5,
The stored data D2 is output. In addition, the first intermediate register 131 is similarly selected for the read enable signal RE input in cycle 5, and the stored data D3 is output in cycle 6.

Further, for read enable signal RE input in cycles 7 and 8, respectively, second intermediate register 132 is selected, and stored data D4 and D5 are output in cycles 8 and 9. Is done. In addition, as a result of the read enable signal RE being invalidated once in cycle 9, the output register 140 is selected for the read enable signal RE input in each of the subsequent cycles 10 and 11, and the read register 140 is read from the dual port RAM 120. The data D6 and D7 output and stored in the output register 140 are output. As a result, in the subsequent cycles, the dual port RAM 120
As long as enough data is stored, the read data is always data that has passed four or more cycles after being applied to the FIFO memory device 100. Therefore, the output register 140 is always selected by the selection circuit 150, and the data is read from the dual port RAM 120. The read data is output.

As described above, the FIFO of the first embodiment
The memory device 100 stores data in the FIFO memory device 10.
The data can be immediately output in the next cycle applied to 0, and the FIFO memory has a latency of 1. Therefore, the input data can be immediately read and provided for a desired process, and the data can be efficiently provided to a subsequent processing unit without waiting time. Further, since the data thus stored can be read out immediately, there is no need to consider the timing of input / output of complicated data at the time of circuit design, and the circuit design becomes easy.

Then, the FIFO memory device 100 having such a configuration is connected to the three-dimensional image generation device 3 of the three-dimensional computer graphics system 1 as described above.
Specifically, for example, if the pixel data generated by the pixel generating unit 34 is input to the mapping unit 35 via the FIFO memory device 100, the pixel data is generated by the pixel generating unit 34. When the mapping is started, the mapping unit 35 can immediately perform texture mapping using the data. That is, the waiting time in the mapping unit 35 immediately after the start of the pixel data generation can be eliminated, the texture mapping can be performed efficiently, and the desired image can be efficiently generated.

Second Embodiment The specific structure of the memory device according to the present invention is not limited to the FIFO memory device 100 according to the first embodiment.
Various other configurations are possible. Other configuration examples of the memory device according to the present invention will be specifically illustrated below as second to seventh embodiments. The memory devices according to the following embodiments are all similar to the FIFO memory device 100 according to the first embodiment.
This is a memory device that can be provided and used between the memory device and the mapping unit 35. Therefore, the description of the application example of each memory device will be omitted, and only each memory device will be described. In each embodiment, the same reference numerals are given to components having the same functions and configurations, and description thereof will be omitted.

First, a second embodiment of the memory device according to the present invention will be described with reference to FIG. The FIFO memory device 101 according to the second embodiment has the first
The operation is the same as that of the FIFO memory device 100 of the second embodiment, but the FIFO memory device is different from the first embodiment in the data selection method and the like. The FIFO memory device 101 includes an input register (REG1) 110, a dual port RAM (Dport RAM) 120, a first intermediate register (REG2) 131, and a selection circuit (MU).
X) 150b, output register (REG4) 141, write pointer unit (Wpointer) 160, write ready signal generation unit (WRDY Gen) 170, read pointer unit (Rpoi)
nter) 181 and a read ready signal generator (RRDY)
Gen) 190. The input register 110, the dual port RAM 120, the first intermediate register 131, the write pointer unit 160, the write ready signal generation unit 170, and the read ready signal generation unit 190 have exactly the same functions as those of the first embodiment, and Since the operation is performed, the description is omitted.

The selection circuit 150b has the same function and performs the same operation as the selection circuit 150 of the first embodiment, but the input / output data is different from that of the first embodiment. In the selection circuit 150b, the input register 110 input to the selection circuit 150 of the first embodiment is used.
, The data stored in the first intermediate register 131, the data stored in the second intermediate register 132, and the data stored in the output register 140 after being read from the dual port RAM 120. One cycle before each data, that is, the data applied to the input register 110, the input register 1
10, the data stored in the first intermediate register 131, and the dual port RAM 12
Data read from 0 is input. Then, the selection circuit 150b selects any one of the data based on the selection signal SEL input from the read pointer unit 181.

The output register 141 is connected to the selection circuit 150b.
Is a register for temporarily storing the data selected in step (1) and outputting it as output data DATAout from the FIFO memory device 101.

The read pointer section 181 controls the dual port RAM 120 based on the read enable signal RE, similarly to the read pointer section 180 of the first embodiment, and also controls the cycle in which the read enable signal RE is input and the output. If the target data is the FIFO memory device 100
Selection circuit 1 based on the relationship with the cycle input to
Generate a select signal SEL for 50. However, the read pointer section 180 outputs the selection signal SEL in the cycle next to the input of the read enable signal RE, but the read pointer section 181 outputs the same selection signal to the same cycle in which the read enable signal RE is input. To the selection circuit 150. This corresponds to the earlier input data to the selection circuit 150b being one cycle earlier.

The FIFO memory device 10 having such a configuration
1, the data input to the selection circuit 150b is one cycle earlier than the selection circuit 150 as described above, but the selection signal SEL is also output one cycle earlier correspondingly. Therefore, in the end, the selection circuit 150b includes the FIFO memory device 100
The same data as the selection circuit 150 is selected one cycle earlier. Since the selected data is received and output once by the output register 141, the output timing of the data becomes the same as that of the FIFO memory device 100 after all. That is, when viewed from the outside, the FIFO memory device 101 is the F / F of the first embodiment.
The operation is exactly the same as that of the IFO memory device 100.

Therefore, the FIFO memory device 101 also has the latency 1 so that the input data can be read immediately. Further, the FIFO memory device 101 of the second embodiment is different from the FIFO memory device 100 of the first embodiment in that:
The configuration is such that the number of registers is smaller by one for the second intermediate register 132. Therefore, a memory device having the same function can be configured with a simpler circuit.

Further, the FIFO memory device 101
Output the data once stored by the output register 141 directly as output data DATAout,
This is effective when the subsequent path to the output data is a critical path. Conversely, input data DATA
in is the output register 141 after passing through the selection circuit 150b.
Since the delay on the input side is large,
It is not preferable if the setup time cannot be sufficiently secured. However, in such a case, the FIFO memory device 100 of the first embodiment in which the input data is immediately received by the input register 110 is preferable. That is, the FIFO memory device 100 of the first embodiment
And the FIFO memory device 101 of the second embodiment may be properly used depending on the characteristics of the circuits before and after.

Third Embodiment A third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, a description will be given of a larger capacity FIFO memory device 200 formed by connecting two FIFO memory devices 100 of the first embodiment. FIG. 5 shows the FIFO memory device 20.
FIG. 6 is a diagram showing a configuration of the FIFO memory device 2.
10 is a timing chart for explaining the operation of the control unit 00.

The FIFO memory device 200 stores the first FI
In this configuration, the FO memory device _100-1 and the second FIFO memory device _100-2 are connected as shown. That is, so as to input the output data of the first FIFO memory device 100 _-1 directly as input data of the second FIFO memory device 100 _2. Further, the read ready signal RRDY the first FIFO memory device 100 _-1, the second
Connect the write enable signal WE for the FIFO memory device 100 _-2 second FIFO memory device 1
00 _-2 write ready signal WRDY connected as a read enable signal RE of the first FIFO memory device 100 _-1. The configuration of each of the FIFO memory devices 100 _-1 and 100 _-2 is exactly the same as the FIFO memory device 100 of the first embodiment described above.

The FIFO memory device 20 having such a configuration
0, first, as shown in FIG.
When the data DATAin to the memory device 100 _-1 is input, the first FIFO memory device 100 _-1, the second F
IFO memory device 100 _-2 write ready signal WRDY
Since _2 is input as the read enable signal, the first FIFO memory device _100-1 immediately performs the data read process. As a result, the first F
Reitanshi of IFO memory device 100 _-1 1, so
The next cycle already the data is output to the second FIFO memory device 100 _-2 as the data output of the first FIFO memory device 100 _-1.

[0069] Also at this time, a read ready signal of the first FIFO memory device 100 _-1, which is the second FIFO memory device 100 _-2 write enable signal of the signal R
RDY_1 since also output, in the second FIFO memory device 100 _-2, immediately the process of storing data. Then, since the latency of the second FIFO memory device 100 _-2 is also 1, if the read enable signal RE is input to the second FIFO memory device 100 _-2 , the data is transmitted in the next cycle. 2
From the FIFO memory device _100-2 .

Further, the second FIFO memory device 100 _-2
When the storage capacity is full, the write ready signal WRDY of the second FIFO memory device 100 _-2 becomes not ready, since the read enable signal RE for the first FIFO memory device 100 _-1 becomes invalid, Since then
The first FIFO memory device _100-1 to the second FIFO memory
The transfer of data to the memory device _100-2 is stopped.

Such a FIFO memory device 200 is
Latency is 2, and the latency is １ ／ compared to the FIFO memory device (latency 4) having the same configuration using the dual port RAM. That is, also in the FIFO memory device 200, the input data can be read and used in an earlier cycle.

When the storage capacity of the FIFO memory is increased, for example, if the capacity of the dual port RAM is simply increased, there may be a problem that it takes a long access time and high-speed processing cannot be performed. However, as described above, the FIFO memory device 100 having a predetermined capacity is used.
It is preferable that the capacity be increased by a method of connecting to a device, because high-speed operation can be maintained. At this time, each time one FIFO memory device 100 is connected, the latency of the FIFO memory device as a whole increases by one. A FIFO memory device can be configured. Also, while allowing for increased latency,
The FIFO memory device 200 is also effective when maintaining high-speed operation.

Fourth Embodiment A fourth embodiment of the present invention will be described with reference to FIGS. As a fourth embodiment, a FIFO memory device using a single-port RAM as a storage element and thereby reducing the latency will be described. FIG.
2 is a block diagram showing a configuration of the FIFO memory device 102. The FIFO memory device 102 includes an input register (REG1) 110, a first single-port RAM.
(SportRAM0) 121, a second single-port RAM (SportRAM1) 122, and a selection circuit (SELE).
CTOR) 152, output register (REG4) 141, write pointer unit (Wpointer) 162, write ready signal generation unit (WRDY Gen) 170, read pointer unit (Rpoi)
nter) 182 and a read ready signal generator (RRDY)
Gen) 190. The input register 110, the output register 141, the write ready signal generation section 170, and the read ready signal generation section 190 have exactly the same functions and perform the same operations as in each of the above-described embodiments, and a description thereof will be omitted.

The first single-port RAM 121 and the second single-port RAM 122 are ordinary DRAMs each having a configuration of 32 bits × 32 words, and transfer data input via the input register 110 from the write pointer unit 162 to the write pointer unit 162. The information is sequentially stored based on the input control signal. At this time, the data is stored in one of the RAMs. Data stored in the first single-port RAM 121 or the second single-port RAM 122 is sequentially read out in the order of storage based on a read control signal from the read pointer unit 182 and output to the selection circuit 152. Is done. Note that these single-port RAMs 121 and 122 can perform only one of input and output operations in one cycle, but during data writing, the write data is output from the output terminal.

The selection circuit 152 includes the read pointer unit 18
The first single-port RAM 121 or the second single-port RAM 122 is selected based on the read RAM selection signal input from the second and the data output from the RAM is output to the output register 141.

Write pointer section 160 generates a storage control signal for first single-port RAM 121 and second single-port RAM 122 based on write enable signal WE input to FIFO memory device 102, Is stored in either the first single-port RAM 121 or the second single-port RAM 122 via the input register 110. In the present embodiment, the write pointer unit 160 stores the sequentially input data in the first single-port RAM 1.
21 and the second single port RAM 122 alternately. The write pointer unit 160 is valid only when the write ready signal generation unit 170 is in a writable state (write ready).

The read pointer section 180 outputs the first stored data which has not been read yet based on the read enable signal RE which is a read request signal input to the FIFO memory device 100. 1 single port RAM 121, 2nd single port R
The AM 122 and the selection circuit 152 are controlled. That is, the data to be read is stored in the first single-port RAM 121 and the second single-port RAM 12.
2 is stored in the first single-port RAM 1 so that the data is read out.
A read control signal is applied to the 21st and the second single port RAM 122. Further, a read RAM selection signal for the selection circuit 152 is generated so that the read data is appropriately selected by the selection circuit 152. Note that the read pointer section 180 is valid only when the read ready signal generation section 190 is in a readable state (read ready).

The operation of the FIFO memory device 102 will be described with reference to FIGS. FIG.
5 is a timing chart for explaining the internal operation of the FIFO memory device 102. Here, FI
The operation of the FIFO memory device 102 when data is sequentially and continuously input to the FO memory device 102 and data is sequentially read out in parallel with the data is described.

As shown in FIG. 8, for example, data D applied to FIFO memory device 102 in cycle 1
0 is stored in the input register 110 in cycle 2 (R
EG1out), the write pointer unit 162 in cycle 3
Is first stored in the first single-port RAM 121 (RAM0in). At this time, the stored data is output to the output terminal of the first single port RAM 121 (RAM 0 out). Therefore, if the read enable signal RE is input, the data output from the first single-port RAM 121 is selected by the selection circuit 152, immediately stored in the output register 141, and the output data from the FIFO memory device 102 is output. It is output as DATAout (REG4out).

Well, in cycle 2, the FIFO memory device 1
The data D1 applied to 02 is stored in the input register 110 in cycle 3 and then stored in the second single-port RAM 122 under the control of the write pointer unit 162 (cycle 4). Then, the read pointer unit 1
Based on the read RAM selection signal from 82, in cycle 4, the second single-port RAM 122 is selected by the selection circuit 152, and the output data D1 is stored in the output register 141. The data stored in the output register 141 is output from the FIFO memory device 102 in cycle 5.

Thereafter, similarly, the input data is sequentially and alternately stored in the first single-port RAM 121 and the second single-port RAM 122. Data is read out in order from the single-port RAM in which the data storage operation is not performed, that is, the second single-port RAM 122 and the first single-port RAM 12.
1 and 1 are alternately accessed, and are sequentially performed.

As described above, the FIFO of the fourth embodiment
The memory device 102 includes two single-port RAMs, and cannot control storage and readout simultaneously by controlling data storage and readout so that storage and readout are not performed simultaneously for one single-port RAM. Using a single port RAM, a FIFO memory device capable of simultaneously storing and reading data was constructed. Generally, for the same storage capacity, a dual-port RAM has a circuit size nearly twice that of a single-port RAM. Therefore, the FIFO memory device 102
Can significantly reduce the circuit scale as compared with an equivalent FIFO memory device using a dual port RAM. This is particularly effective when the FIFO memory device is formed on an integrated circuit.

In general, a single-port RAM has better AC characteristics than a dual-port RAM, so that high-speed operation is possible. That is, the FIFO memory device 102
Can operate faster than an equivalent FIFO memory device using a dual port RAM.
Further, as described above, since the single-port RAM has its data appearing at the output terminal during data storage, the latency of the single-port RAM itself is 1 in that the stored data is immediately read. Therefore, the latency of the FIFO memory device 102 is 3, and the latency can be reduced as compared with the case where the FIFO memory device is configured using the dual port RAM. As a result, it is possible to read out the input data more quickly and provide the desired processing.

In the present embodiment, the write pointer unit 162 controls the storage of the data so as to store the data alternately in the two single-port RAMs. Optional. For example, a single-port RAM for storing data may be selected by giving priority to data reading and storing data in a single-port RAM from which data has not been read.

Fifth Embodiment A fifth embodiment of the present invention will be described with reference to FIG. As a fifth embodiment, F of the fourth embodiment
A larger capacity FIFO memory device 203 formed by connecting two IFO memory devices 102 is illustrated. FI
The FO memory device 203 is the first FIFO memory device 1
02 _-1, the second FIFO memory device 102 _-2 are connected to each as shown. This connection method uses the FIFO memory device 2 of the third embodiment configured by connecting two FIFO memory devices using a dual-port RAM.
It is exactly the same as 00. The operation of the FIFO memory device 203 is almost the same as that of the FIFO memory device 200 of the third embodiment.

The FIFO memory device 1 according to the fourth embodiment
02 may be used in such a form. Such F
In the FIFO memory device 203, the storage capacity of the FIFO memory can be increased while maintaining high-speed processing with a small circuit scale. In particular, when a high-speed and relatively large-capacity FIFO memory is formed on an integrated circuit, that is, for example, when the above-described three-dimensional image generating apparatus is formed on an integrated circuit, a FIFO used therein is used.
As the O memory, such a FIFO memory device 203 is used.
Is preferred. FIFO memory device 2 of such a form
03 is also within the scope of the present invention.

Sixth Embodiment A sixth embodiment of the present invention will be described with reference to FIG. FIFO memory device 104 of the sixth embodiment
Is different from the FIFO memory device 102 of the fourth embodiment in that the first intermediate register 131 and the selection circuit 150 are the same as those of the FIFO memory device 100 of the first embodiment.
And the latency is set to 1. The FIFO memory device 104 includes an input register (REG1) 110, a first single-port RAM (S
port RAM 0) 121, second single port R
AM (Sport RAM1) 122, first intermediate register (REG2) 131, selection circuit (SELECTOR) 15
2. Output register (REG4) 141, selection circuit (MU)
X) 154, a write pointer unit (Wpointer) 162, a write ready signal generation unit (WRDY Gen) 170, a read pointer unit (Rpointer) 182, and a read ready signal generation unit (RRDY Gen) 190. The configuration and operation of these units are the same as those of the above-described embodiment.

In the FIFO memory device 104, the selection circuit 154 for selecting the output data uses the data stored in the input register 110, the first intermediate register 1
One data is selected from the three data stored in the output register 141 and the data read from the first single-port RAM 121 or the input terminal 12 and stored in the output register 141. This is the fourth
This is because the FIFO memory device 102 according to the embodiment is originally a FIFO memory device having a latency of 3, so that a path for delaying input data by 3 cycles using an intermediate register is unnecessary. Therefore, as compared with the FIFO memory device 100 of the first embodiment, the second intermediate register 132 is not required, and the selection circuit 154 can be configured with a simpler selector.

Therefore, the FIFO memory device 10
4 has a simpler circuit configuration and can operate at high speed when the storage element is a single-port RAM.
The FIFO memory device has a latency of 1.

Seventh Embodiment A seventh embodiment of the present invention will be described with reference to FIG. FIFO memory device 105 of the seventh embodiment
Applies a configuration similar to that of the FIFO memory device 101 of the second embodiment to the FIFO memory device 102 of the fourth embodiment, and sets the latency to 1.
It is a memory device. The FIFO memory device 105 includes an input register (REG1) 110, a first single port R
AM (Sport RAM0) 121, second single-port RAM (Sport RAM1) 122, selection circuit (SELECTOR) 152, selection circuit (MUX) 154b,
Output register (REG4) 141, write pointer unit (Wpointer) 162, write ready signal generation unit (WRD)
Y Gen) 170, read pointer section (Rpointer) 182
And read ready signal generation unit (RRDY Gen) 190
Having. The configuration and operation of these units are the same as those of the above-described embodiment.

In the FIFO memory device 105, the latency is reduced to 1 without any need for an intermediate register.
And the circuit configuration is further simplified. Such a configuration can be adopted when the latency of the storage element portion is originally 1 and a sufficient setup time on the data input side can be ensured. Also FI
The FO memory device 105 is, as in the second embodiment,
Since the data once stored by the output register 141 is directly output as the output data DATAout, it is effective when the subsequent path to the output data is a critical path.

The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, F of the first embodiment described with reference to FIG.
The dual port RAM 120 applied to the FIFO memory device 100 and the FIFO memory device 101 according to the second embodiment described with reference to FIG. Although two RAMs are used, a RAM that can read data written in the same cycle may be used. In such a configuration, the FI of the first embodiment is used.
In the FO memory device 100, the second intermediate register 1
32 is a FIFO memory device 101 according to the second embodiment.
In the above, the first intermediate register 131 is not required, and the configuration can be further simplified. As the dual port RAM 120, a RAM having a configuration in which data and address inputs are latched may be used. In such a case, the input register 110 is not required even in the case of high-speed operation, and the configuration can be further simplified.

In the present embodiment, the FIFO
As an application example of the memory device 100, a three-dimensional image generation device has been illustrated.
The O memory can be applied to any suitable device.

[0094]

As described above, according to the memory device of the present invention, in the FIFO type memory device, the latency from the time when data is applied to the time when data is output can be further reduced, and the input of data can be reduced. The data can be read immediately and supplied to the subsequent processing. Further, according to the image generating apparatus of the present invention, the latency of the FIFO type memory device used for data transfer between the processing means can be further reduced, so that the input data is immediately read and the Can be supplied to the processing of
Thereby, desired image processing can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a three-dimensional computer graphics system 1 to which an embodiment of the present invention is applied, to which a memory device of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of the FIFO memory device shown in FIG. 1 and according to the first embodiment of the present invention;

FIG. 3 is a timing chart for explaining an operation of the FIFO memory device shown in FIG. 2;

FIG. 4 is a block diagram illustrating a configuration of a FIFO memory device according to a second embodiment of this invention;

FIG. 5 is a block diagram showing a configuration of a FIFO memory device according to a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining an operation of the FIFO memory device shown in FIG. 5;

FIG. 7 is a block diagram illustrating a configuration of a FIFO memory device according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart for explaining an operation of the FIFO memory device shown in FIG. 7;

FIG. 9 is a block diagram illustrating a configuration of a FIFO memory device according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a FIFO memory device according to a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a FIFO memory device according to a seventh embodiment of the present invention.

[Explanation of symbols]

1. 3D computer graphics system 2.
Input unit, 3 ... 3D image generation device, 4 ... Display device, 32
... Geometry calculation unit, 33 ... Parameter calculation unit, 34 ...
Pixel generation unit, 35 mapping unit, 36 texture memory, 37 memory control unit, 38 image memory, 39 ...
Display control unit, 100, 101, 102, 10
4, 105 FIFO memory device, 110 input register, 120 dual port RAM, 121 first single port RAM, 122 second single port R
AM, 131: first intermediate register, 132: second intermediate register, 140, 141 ... output register, 150,
152, 154 selection circuit, 160, 162 write pointer section, 170 write ready signal generation section, 180
181, 182: read pointer unit; 190: read ready signal generation unit; 200: FIFO memory device

Claims (20)

[Claims] 1. A memory circuit for sequentially storing input data in a plurality of storage areas, and upon request, data stored in the memory circuit.
A memory reading unit that reads the order of input, and a predetermined number of registers based on the number of cycles from application of data to be stored to the memory circuit to reading of the data, A shift register connected so as to sequentially shift the data of the input data, so that the input data is output immediately in response to the request in the order of the input, as required. Output data selecting means for selecting and outputting any one of data stored in each shift register or data read from the memory circuit. 2. An input register for storing the input data; a memory circuit for sequentially storing the data stored in the input register in a plurality of storage areas; Data
The memory reading means for reading in the input order; an output register for storing data read from the memory circuit; and a minimum number of cycles from application of data to be stored to the memory circuit to reading. The shift registers serially connected to the input register so that a corresponding number of registers sequentially shift the data stored in the input register; and The data stored in the input register, the data stored in each register of the shift register, or the data stored in the output register so that the data is immediately output in response to the request in the order of input. And output data selecting means for selecting and outputting any one of the following.
A memory device as described. 3. The memory circuit is a memory circuit capable of reading the applied data in a second cycle after the application of the data. The shift register includes a first register and a second register. Registers are serially connected to the input register in this order in a shift register. In the next cycle after the application to the register, the data stored in the input register is selected, and in the second cycle after the application, the first cycle is selected.
The data stored in the second register is selected, and if it is the third cycle after the application, the data stored in the second register is selected.
3. The memory device according to claim 2, wherein the data stored in said output register is selected in a cycle or later. 4. The memory device according to claim 3, wherein said memory circuit is a dual port memory capable of storing and reading data in the same cycle. 5. An input register for storing the input data; a memory circuit for sequentially storing data stored in the input register in a plurality of storage areas; and a memory stored in the memory circuit on demand. Data
The memory read means for reading in the order of input, and a number of registers corresponding to a number obtained by subtracting 1 from a minimum number of cycles from application of data to be stored to the memory circuit to readout, The shift register serially connected to the input register so as to shift the data stored in the input register in order; and upon request, the input data is immediately output in the order of the input in response to the request Data to be stored applied to the input register, data stored in the input register, data stored in each register of the shift register, or read by the memory reading means. Any one of the issued data
The memory device according to claim 1, further comprising: an output data selection unit that selects one of the output data; and an output register that stores the selected data. 6. The shift circuit according to claim 1, wherein the memory circuit is capable of reading the applied data in a second cycle after the application of the data. The output data selection means is a register connected in series, and if the cycle at the time of data selection is a cycle in which data whose output is requested is applied to the input register as data to be stored, Select the data applied to the register,
In the next cycle after the application, the data stored in the input register is selected, and in the second cycle after the application, the data stored in the register of the shift register is selected. 6. The memory device according to claim 5, wherein in a third cycle after the application, the data read by said memory reading means is selected. 7. The memory device according to claim 6, wherein said memory circuit is a dual port memory capable of storing and reading data in the same cycle. 8. A memory circuit for sequentially storing data input together with a storage request signal in a plurality of storage areas, and a memory for reading data stored in the memory circuit in the order of input based on a read request signal. Reading means, and a predetermined number of registers based on the number of cycles from when the data to be stored is applied to the memory circuit until the data is read out, sequentially shifts the data to be stored applied to the memory circuit. A shift register connected to the input data and stored in each register of the shift register so as to immediately output the input data in the order of the input in response to the input of the read request signal. Output data for selecting and outputting each of the data stored in the memory circuit or one of the data read from the memory circuit. Selecting means; read-ready signal generating means for generating a read-ready signal indicating that the stored and not-yet-read data exists in the memory circuit; and capable of newly storing data in the memory circuit. A plurality of write-ready signal generating means for generating a write-ready signal indicating that a region exists; and a plurality of memory devices, each of which outputs the output data of the preceding memory device to the succeeding memory device. Input as data to be stored, input the read ready signal of the preceding memory device as the storage request signal to the subsequent memory device, and input the write ready signal of the subsequent memory device to the preceding memory device. A memory device sequentially connected so as to input the read request signal. 9. An input register for storing data to be input, and a memory circuit for sequentially storing data stored in the input register in a plurality of storage areas, wherein the memory circuit stores data in a next cycle in which data to be stored is applied. Is a memory circuit capable of outputting the data, and upon request, the data stored in the memory circuit is
Memory reading means for reading in the order of input, and, as required, data to be stored applied to the input register so that the input data is immediately output in the order of input in response to the request. Or any one of the data read by the memory reading means.
A memory device comprising: output data selecting means for selecting one; and an output register for storing the selected data. 10. An input register for storing data input together with a storage request signal, and a memory circuit for sequentially storing data stored in the input register in a plurality of storage areas, wherein data to be stored is applied. In the next cycle, a memory circuit capable of outputting the data, a memory read means for reading data stored in the memory circuit in the order of input in response to a read request signal, and the input data To select any one of the data to be stored applied to the input register or the data read by the memory read means, so that the data is immediately output in response to the read request signal in the order of the inputs. Data selection means, an output register for storing and outputting the selected data, and the memory circuit Read-ready signal generation means for generating a read-ready signal indicating that data which has not been read yet exists; and a write-ready signal indicating that there is an area in which data can be newly stored in the memory circuit. A plurality of memory devices having write-ready signal generating means for generating, and the plurality of memory devices input output data of the preceding memory device as data to be stored to the succeeding memory device, and The read-ready signal of the device is input to the subsequent memory device as the storage request signal, and the write-ready signal of the subsequent memory device is sequentially input to the preceding memory device as the read request signal. Memory device. 11. An input register for storing data to be input, each of which has a plurality of storage areas and is independently accessible,
In the next cycle to which the data to be stored is applied, the first memory circuit and the second memory circuit capable of outputting the data are provided.
A memory control means for storing data stored in the input register in one of the first memory circuit and the second memory circuit; and A memory device, comprising: a read control unit that reads out data stored in a circuit and the second memory circuit in the order of input, and an output register that stores the read data. 12. The memory device according to claim 11, wherein said storage control means stores sequentially input data in said first memory circuit and said second memory circuit alternately. 13. The first memory circuit reading means for reading the data stored in the first memory circuit in the order of the input, and the data stored in the second memory circuit. A second memory circuit reading means for reading the data in the order of input, and a data read by the first memory circuit reading means or a data read by the second memory circuit reading means. 2. A read data selecting means for selecting any one of the previously inputted data.
3. The memory device according to 2. 14. The memory device according to claim 13, wherein each of said first memory circuit and said second memory circuit is a single port memory. 15. The memory device according to claim 14, wherein said input register, said first memory circuit, said second memory circuit, said storage control means and said read control means are configured as an integrated circuit. 16. A second register for storing data stored in the input register, wherein the input data is output in the order of the input and immediately in response to the request. An output data selecting means for selecting and outputting any one of data stored in an input register, data stored in the second register, and data stored in the output register. Item 13. The memory device according to Item 12. 17. The data to be stored applied to the input register or the read control means so that the input data is output immediately in response to the request in response to the request. 14. The memory device according to claim 13, further comprising an output data selection unit that selects any one of the read data, wherein the output register stores the data selected by the output data selection unit. 18. The memory device according to claim 17, wherein said read data selection means and said output data selection means are constituted by one selection circuit. 19. An input register for storing data input together with a storage request signal, each of which has a plurality of storage areas and is independently accessible,
In the next cycle to which the data to be stored is applied, the first memory circuit and the second memory circuit capable of outputting the data are provided.
A memory circuit for storing the data stored in the input register in one of the first memory circuit and the second memory circuit; and Read control means for reading out the data stored in the memory circuit and the second memory circuit in the order of input, an output register for storing and outputting the read out data, the first memory circuit or In the second memory circuit,
A read-ready signal generating unit that generates a read-ready signal indicating that the stored data that has not been read exists; and wherein the first memory circuit or the second memory circuit includes:
A plurality of write-ready signal generating means for generating a write-ready signal indicating that a new data-storable area exists; and the plurality of memory devices output data from the preceding memory device. The memory device of the subsequent stage is inputted as data to be stored, the read ready signal of the memory device of the preceding stage is inputted as the storage request signal to the memory device of the subsequent stage, and the write ready signal of the memory device of the subsequent stage is inputted. A memory device sequentially connected to a preceding memory device so as to input the read request signal. 20. A three-dimensional image data in which an arbitrary three-dimensional solid model is shown as a set of basic polygons indicated by vertices having at least three-dimensional position information, with respect to the vertices of the basic polygon. Coordinate conversion means for performing predetermined coordinate conversion; pixel data generation means for generating pixel data of the basic polygon based on data of vertices of the basic polygon; FIFO for sequentially storing the generated pixel data A memory; texture mapping means for sequentially reading the generated pixel data from the FIFO memory; performing texture mapping using a desired texture pattern; and generating display three-dimensional image data; An image memory for storing as three-dimensional image data, and a desired area from the stored three-dimensional image data for display. Output means for reading out data as display screen data, the FIFO memory comprising: a memory circuit for sequentially storing pixel data sequentially inputted in a plurality of storage areas; Memory reading means for reading the pixel data stored in the memory in the order of input, and a predetermined number of registers based on the number of cycles from the application of the pixel data to be stored to the memory circuit until the data is read out, A shift register connected to sequentially shift the pixel data to be stored applied to the memory circuit, and upon request, the input pixel data is immediately output in the order of the input in response to the request As described above, the input pixel data, each pixel data stored in each register of the shift register, or And an output data selection means for selecting one of the pixel data read from the memory circuit, an image generating device for outputting the selected pixel data to the texture mapping unit.