JPH11161594A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer data to a desired module device without using the absolute address. SOLUTION: This system is provided with one or more module devices 200,..., 210, a DRAM controller 300 for controlling the input/output of the data between the respective module devices and a DRAM 400 and an RBUS connected to the respective devices in common for which only the DRAM controller 300 becomes a bus master. Further, the RBUS can transmit at least one command among the command for obtaining relative address information, the command for instructing the set of the absolute address to a marker and the command for turning an address under consideration to the value set by the marker.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system for transferring data stored in a memory to a desired module device without using an absolute address.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration example of a conventional data transfer system. This data transfer system includes a CPU (Central Processing Unit) 10, a dynamic random access memory (DRAM) 40 for storing data, and a DRAM 40 connected to the DRAM 40 by an address line 58 and a data line 59.
40, and two module devices 21 and 22. Each of the module devices 21 and 22 has a data line 5
2, address line 53, control line 54, and data line 5
5, DRAM 30 via address line 56 and control line 57
And a data bus 50 and an address bus 51 are commonly connected to each of the devices 10, 20, 21, and 30.

The DRAM controller 30 inputs / outputs data to / from the module device 20 via the data line 52 using a control signal transmitted / received via the control line 54, and transmits / receives data via the control line 57. The data is input / output to / from the module device 21 via the data line 55 using the control signal. As described above, in each of the configuration between the DRAM controller and the module device, the control line and the data line are provided so that the DRA
The data stored in M40 is transferred to the module device.

[0004]

However, in the conventional data transfer system, the data transfer process is performed by using the address lines 53 and 56 when transferring data, and by transmitting an absolute address to these address lines. I was going.

Therefore, when transferring a large amount of data stored in the DRAM 40 to a specific module device at a time, a large amount of addresses to be transferred makes it impossible to perform a rapid data transfer process.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a system for transferring data to a desired module device without using an absolute address.

[0007]

According to one aspect of the present invention, there is provided a system for transferring data stored in a memory, wherein at least one system performs predetermined data processing. And a memory control device for controlling data input / output between the one or more module devices and the memory, wherein each of the devices is commonly connected and only the memory control device is a bus master. A command for obtaining relative address information indicating a relative value of an address of data of interest with respect to an address of a certain data;
A data transfer system capable of transmitting at least one command of a command for setting an absolute address to a marker and a command for setting a target address to a value set by a marker.

According to this, since the memory control device uses the memory bus and performs the data transfer process using the relative address information, the marker, and the like, the conventional physical address is not used, and the address bus becomes unnecessary. At the same time, addressing of data to be transferred becomes free.

Further, the invention according to claim 2 is characterized in that, in claim 1, the address is expressed in a multidimensional manner. According to this, since the address can be expressed in multi-dimensions, for example, by handling addresses expressed in two dimensions, data transfer processing of image data, audio data, and the like becomes possible.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a data transfer system according to an embodiment of the present invention.

This data transfer system uses an R (not shown)
A CPU (central processing unit) 100 that performs an operation according to a procedure described in advance in a storage medium such as an OM, and a plurality of module devices 200,..., 210 (only two are shown in FIG. 1 for easy understanding) And a dynamic random access memory for storing image data and the like
And a DRAM controller 300 connected to the DRAM 400 via an address line 401 and a data line 402 and performing a data transfer process between the DRAM 400 and each device.

Further, a memory bus (RBUS) in which only the DRAM controller 300 is a bus master includes an R bus I / F 110, an R bus I / F 201, and an R bus I / F 2
11 and each of the R bus I / F 310
PU (central processing unit) 100, module device 200,
The module device 210 and the DRAM controller 300 are connected.

The RBUS transmits RDAT which is a data transfer bus (data bus), RCMD which is a command transfer bus (command bus) for data transfer, and a clock supplied from a clock supply unit (not shown). RCLK, which is a bus to be used. Therefore, since the memory bus includes the command bus and the data bus, a command can be sent at the same time as the data transfer, and a quick data transfer can be realized. And RBUS
Is configured such that data transmission between devices connected to the bus is controlled by a dedicated protocol.

Further, the function of each interface connecting each of the module devices 200,..., 210 and the DRAM controller 300 as viewed from the RBUS side is configured to be the same.

FIG. 3 shows the structure of the R bus I / F. In this specification, only the elements necessary for the description are described to facilitate the understanding. As shown in FIG.
/ F, a data conversion unit 600 for converting data transmitted and received via RDAT, a decoding unit 610 for decoding commands transmitted and received via RCMD and generating a control signal corresponding to the decoding result, X register 611 and Y register 612 for storing addresses
And two types of marker registers MX61 described later.
3 and MY614, so that a clock supplied via RCLK can be supplied to a necessary portion inside the device. Note that two-dimensional address values (address X, address Y) are output from 611 to 614.

The data conversion performed by the data conversion unit 600 is, for example, a bit length conversion for converting 16-bit data to 8-bit data, or changing the data access direction from bidirectional (reading and writing) to unidirectional (reading only). Conversion of data access direction and the like can be mentioned. The control signal generated by the decoding unit 610 is sent to a predetermined location inside the device, and the device performs an operation according to the control signal. The control signal includes a signal indicating the valid period of the RBUS for the own module, a read / write signal, a buffer inside the module, an address signal of a register, and the like. As described above, since the R bus I / F has a function of performing a decoding process and generating a control signal for performing operation control inside the module device, it is only necessary to adapt and manufacture the interface unit itself for each module. In addition, it becomes easy to connect various module devices to the memory bus.

In this system, a command is transmitted and received via the RCMD, and the format is, as shown in FIG. 4, a 4-bit operation code and data on the RDAT is a byte ("0") or a word ("1"). 5) and a 6-bit operand, and various commands as shown in FIGS. 5 and 6 can be transmitted.

Next, the module device 200 is
The operation in the case where a request to read data stored in 00 and the DRAM controller 300 transfers the data to the module device 200 will be described.

First, the DRAM controller 300 stores an AREQ (Ask for REQuest: DRA) on the RCMD every time the data transfer of the DRAM which has once started the service is completed.
M service request request) command, and receives a request for a DRAM data transfer service from each module device (DRAM service request request).

Next, upon receiving the AREQ command on the RCMD, the module device 200 that has issued the DRAM data read request immediately asserts a pre-allocated 1 bit on the RDAT in the same clock cycle as the AREQ command. (DRAM service request).

Next, the DRAM controller 300
The status of the DAT is monitored, and the status of the DRAM data transfer service request from each module device is grasped. Then, it is determined that the DRAM data transfer service to the module device 200 having the highest service priority among the module devices that have requested the DRAM data transfer service is selected as the next DRAM data transfer service. Note that the service priority may be set in advance, and in this embodiment, it is assumed that the service priority of the module device 200 is the highest.

Therefore, the DRAM controller 300
In order to notify the module device 200 that the DRAM data transfer service request has been accepted, the DRA from the module device 200 is requested in the next clock cycle.
TX using M data transfer service request ID as operand
An ID (Transmitt ID: service start ID transmission) command is issued. The DRAM data transfer service request I
D is set in advance for each module device (D
RAM service ID notification). Note that (DRAM service request request), (DRAM service request), and (DRAM service ID notification) correspond to data transfer request processing.

The DRAM controller 300 that has selected the next DRAM data transfer service starts a memory access operation to read desired data in the DRAM 400. The DRAM controller 300 uses the access time until read data is read from the DRAM to set an initial address and the like for an input buffer (not shown) of the module device 200 using the SETX.
This is executed using an (X address setting) command, a SETY (Y address setting) command, or the like.

When data reading from the DRAM 400 is started, the DRAM data is transferred on the RDAT. In synchronization with this DRAM data transfer, DR
The AM access addressing sequence command (which indicates commands from INCX to SETMY in FIG. 6) is transferred.

More specifically, INCX (X address increment) command, INCY (Y address increment) command, SETX (marker X address setting) command, SETY (marker Y address setting) command, GMX (marker X address Jump) command, GMY (marker Y address jump) command, etc. are used in synchronization with data transfer,
Any access address sequence in AM page units can be expressed (DRAM data transfer). Note that this (DRAM data transfer) corresponds to the data transfer process, and in particular, the initial address setting corresponds to the initialization process.

Here, the address sequence operation using a specific command will be described in further detail assuming a specific scene. In the case where image data and the like are stored in the DRAM 400, there are virtual boundaries in data storage such as pages and banks, and when performing read / write access of data across these boundaries. ,
The DRAM controller 300 requires additional cycles other than the normal cycle. Therefore, when performing burst access, which is access across page boundaries,
In order to increase the data transfer speed, it is necessary to optimize the data access order and reduce the number of page breaks that occur across page boundaries.

For example, three pixels vertically and three pixels horizontally (one pixel is one pixel)
If there is no page boundary in the 3 × 3 block (occupying one address), the data access order is as shown in FIG. 7 (access order when there is no page break). In order to reduce the number of page breaks, it is necessary to perform data access in the order shown in FIG. 8, for example. Since the position of the page boundary is arbitrary for each burst access, the addressing data command needs to be able to correspond to any data access order.

Using the access sequence shown in FIG. 8 as an example of an addressing sequence, data access from the DRAM 400 to the module device 200 by the DRAM controller 300 using the addressing sequence command will be described.

After the above-described data transfer processing, the DRAM controller 300 starts a memory access operation for reading data of a 3 × 3 block in the DRAM 400. The DRAM controller 300 issues an access pointer (X, Y) and a marker (MX, MY) in a buffer in the module device 200 during an access cycle from the issuance of a read command to the DRAM 400 until data is read. Is initialized to 0.

Specifically, “Opcode; SETX,
Operand; x = 0 ”, the operand value x = 0 is set in the X register and the MX register in the R bus I / F 201. Also, "Opcod
e; SETY, Operand; y = 0 ", the operand value y = 0 is changed to the R bus I / F 20
1 are set in the Y register and MY register.

Next, in synchronization with the read data (shown by "0" in FIG. 8) from the DRAM 400, the DRAM controller 300 issues an INCX command indicating the addressing of the next read data (shown by "1" in FIG. 8). RCM
Issue on D.

Specifically, "Opcode; INCX,
Operand; dx = 1 ”, as addressing information for storing the next read data (illustrated by“ 1 ”in FIG. 8), the X register in the R bus I / F 201 has a value incremented by 1 and the Y register has Is set as is.

Next, in synchronization with the read data from the DRAM 400 (illustrated by "1" in FIG. 8), the DRAM controller 300 issues an INCY command indicating the addressing of the next read data (illustrated by "2" in FIG. 8). RCM
Issue on D.

More specifically, “Opcode; INCY,
In response to the command of “Operand; dy = 1”, the X register in the R bus I / F 201 stores the value of the marker MX = 0 and the Y register as addressing information for storing the next read data (shown by “2” in FIG. 8). Is set to a value incremented by one.

Next, in synchronization with the read data from the DRAM 400 (illustrated by "2" in FIG. 8), the DRAM controller 300 issues an INCX command indicating the addressing of the next read data (illustrated by "3" in FIG. 8). RCM
Issue on D.

Specifically, "Opcode; INCX,
In response to a command of “Operand; dx = 1”, as an addressing information for storing the next read data (shown by “2” in FIG. 8), the X register in the R bus I / F 201 is incremented by 1 and the Y register is The value is set as is.

Next, in synchronization with the read data (illustrated by “3” in FIG. 8) from the DRAM 400, the DRAM controller 300 issues a GMY command indicating the addressing of the next read data (illustrated by “4” in FIG. 8). RCMD
Issue above.

Specifically, "Opcode; GMY, O
In response to a command of “perand; dx = 1”, as an addressing information for storing the next read data (illustrated by “4” in FIG. 8), the X register in the R bus I / F 201 is incremented by 1 and the Y register is The value of the marker MY = 0 is set.

Next, the DRAM controller 300 accesses the read data (illustrated by "4" in FIG. 8).
Here, an access cycle occurs before the data is read to cross the page boundary. The marker MX is set during this access cycle.

More specifically, "Opcode; SETM
The start value of the access address of the new page area is set to the marker MX in preparation for accessing the next page boundary by the command of X, GMY, Operand;

Next, in synchronization with the read data from the DRAM 400 (illustrated by "4" in FIG. 8), the DRAM controller 300 issues an INCY command indicating the addressing of the next read data (illustrated by "5" in FIG. 8). RCM
Issue on D.

More specifically, "Opcode; INCY,
In response to a command of “Operand;“ @ ””, the X register in the R bus I / F 201 stores the value of the marker MX as addressing information for storing the next read data (illustrated by “5” in FIG. The value incremented by one is set.

Next, in synchronization with the read data from the DRAM 400 (illustrated by "5" in FIG. 8), the DRAM controller 300 issues an INCY command indicating the addressing of the next read data (illustrated by "6" in FIG. 8). RCM
Issue on D.

Specifically, "Opcode; INCY,
In response to the command of “Operand; dy = 1”, the X register in the R bus I / F 201 stores the value of the marker MX as addressing information for storing the next read data (shown in FIG. The value incremented by one is set.

Next, the DRAM controller 300 accesses the read data (shown by "6" in FIG. 8).
Here, an access cycle occurs before the data is read to cross the page boundary. During this access cycle, an X functioning as an access pointer and a marker MX are set.

Specifically, "Opcode; SETX,
In response to a command of “Operand; x = 0”, the R bus I
The value of the X register and the marker MX in / F201 is set to the start value of the access address of the new page area.

Next, in synchronization with the read data from the DRAM 400 (illustrated by “6” in FIG. 8), the DRAM controller 300 issues an INCX command indicating the addressing of the next read data (illustrated by “7” in FIG. 8). RCM
Issue on D.

Specifically, "Opcode; INCX,
In response to a command of “Operand; dx = 1”, as an addressing information for storing the next read data (shown by “7” in FIG. 8), the X register in the R bus I / F 201 is incremented by 1 and the Y register is The value is set as is.

Next, in synchronization with the read data from the DRAM 400 (illustrated by “7” in FIG. 8), the DRAM controller 300 issues an INCX command indicating the addressing of the next read data (illustrated by “8” in FIG. 8). RCM
Issue on D.

Specifically, "Opcode; INCX,
Operand; dx = 1 ”, addressing information for storing the next read data (shown by“ 8 ”in FIG. 8) is stored in the X register in the R bus I / F 201 as a value incremented by 1, and in the Y register. The value is set as is.

Next, the DRAM controller 300 accesses the read data (shown by "8" in FIG. 8).
Here access is made across page boundaries,
An access cycle occurs until data is read. The marker MX is set during this access cycle.

More specifically, “Opcode; SETM
X, Operand; By the command "-",
As a preparation for accessing the next page area, the value of the marker MX in the R bus I / F 201 is set to the start value of the access address of the new page area.

Next, in synchronization with the read data from the DRAM 400 (illustrated by "8" in FIG. 8), the DRAM controller 300 sends a TXDONE signal indicating the end of the read data.
Issue a command on the RCMD.

Specifically, "Opcode; TXDON
A command “E, Operand; dx = 1” ”indicates the end of data transfer. Thus, finally,
The DRAM controller 300 issues a TXDONE (transfer end) command in synchronization with the end of the DRAM data transfer service, and one DRAM transfer service ends (DRAM data transfer end).

As a command for obtaining relative address information indicating the relative value of the address of the data of interest with respect to the address of a certain data, for example, INCX, INC
Commands where Y instructs the setting of the absolute address to the marker include, for example, SETMX and SETMY, and commands for setting the target address to a value set by the marker include, for example, GMX and GMY.

As described above, according to this embodiment, data transfer can be performed only with relative addresses, so that an address bus is not required, and all necessary addresses can be expressed with a small number of commands. For example, a certain address and a predetermined address range therefrom, a certain address B
, And the address of data shifted by a predetermined address from certain data can be easily expressed. Therefore, the command transfer at the time of data transfer can be simplified.

Further, since the address is not represented by an absolute address, data can be transferred without concern for the real address of the memory. Since no absolute address is used, addressing independent of the memory configuration can be performed, and the memory configuration can be easily changed.

In this embodiment, the address is 2
Although the description has been given of the case where the address is expressed in a dimension, generally, since the address can be expressed in a multi-dimensional manner, transfer of image data and data having a multi-layered audio data structure is facilitated.

[0059]

As described above, according to the first aspect of the present invention, an address bus becomes unnecessary, and the addressing of data to be transferred becomes free.

According to the second aspect of the invention, for example, data transfer processing of image data, audio data, and the like can be performed by handling addresses expressed in two dimensions.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transfer system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional data transfer system.

FIG. 3 is a configuration diagram of an R bus I / F.

FIG. 4 is an explanatory diagram of a command format.

FIG. 5 is an explanatory diagram of a command.

FIG. 6 is an explanatory diagram of a command.

FIG. 7 is an explanatory diagram of an embodiment of the present invention.

FIG. 8 is an explanatory diagram of an embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 CPU (central processing unit) 110 R bus I / F 120 G bus I / F 200 module device 201 R bus I / F 202 G bus I / F 210 module device 211 R bus I / F 212 G bus I / F 300 DRAM controller 310 R bus I / F 320 G bus I / F 400 DRAM 401 address line 402 data line 600 data conversion unit 610 decoding unit 611 X register 612 Y register 613 MX (marker) 614 MY (marker)

Claims (2)

[Claims] 1. A system for transferring data stored in a memory, comprising: at least one module device for performing predetermined data processing; and data transfer between the at least one module device and the memory. A memory control device for controlling input and output, wherein each of the devices is connected in common, and a memory bus is provided in which only the memory control device serves as a bus master.The memory bus further comprises: At least one of a command for obtaining relative address information indicating a relative value of an address of data of interest, a command for setting an absolute address to a marker, and a command for setting the address of interest to a value set by a marker A data transfer system capable of transmitting a command. 2. The data transfer system according to claim 1, wherein the address is expressed in a multi-dimensional manner.