JPH11161593A - Data transfer system and testing method for data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily transfer data by simple constitution. SOLUTION: This system is provided with a CPU 100, plural module devices 200,..., 210, a DRAM 400 and a DRAM controller 300. To a GBUS for which only the CPU 100 becomes a bus master, through the respective ones of a G bus I/F 120, the G bus I/F 202, the G bus I/F 212 and the G bus I/F 320, the CPU 100, the module device 200, the module device 210 and the DRAM controller 300 are connected. Also, to an RBUS for which only the DRAM controller 300 becomes the bus master, by the respective ones of an R bus I/F 110, the R bus I/F 201, the R bus I/F 211 and the R bus I/F 310, the CPU 100, the module device 200, the module device 210 and the DRAM controller 300 are connected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system for transferring a large amount of image data and the like stored in a memory to a module device or a central processing unit and a test method therefor.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration example of a conventional data transfer system. This data transfer system includes a CPU (Central Processing Unit) 10, a dynamic random access memory (DRAM) 40 for storing data, and a DRAM 40 connected to the DRAM 40 by an address line 56 and a data line 57.
40, and two module devices 21 and 22. Each of the module devices 21 and 22 has a data line 5
2, connected to the DRAM 30 via a control line 53, a data line 54, and a control line 55, and a data bus 50 and an address bus 51 are connected to the respective devices 10, 20, 2
1, 30 are commonly connected.

The DRAM controller 30 inputs / outputs data to / from the module device 20 via the data line 52 using a control signal transmitted / received via the control line 53, and transmits / receives data via the control line 55. The data is input / output to / from the module device 21 via the data line 54 using the control signal. As described above, in each of the configuration between the DRAM controller and the module device, the control line and the data line are provided so that the DRA
The data stored in M40 is transferred to the module device.

[0004]

However, in such a conventional data transfer system, a control line and a data line are provided between the DRAM controller and the module device, respectively. As the number increases, the wiring becomes complicated, and the number of wirings increases to increase the wiring area.

[0005] Such a complicated wiring and an increased wiring area increase the complexity of the manufacturing process when implementing the LSI, and also increase the cost. Further, in the conventional data transfer system, since the data transfer protocol for each module device is different, in order to test each module device, a test is performed between the DRAM controller 30 and each of the module devices 20 and 21. Therefore, a separate test circuit for providing data for the module to the module device must be provided, and an increase in test cost has become a problem.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a system which can easily transfer data with a simple configuration. Also,
It is another object of the present invention to provide a test method for this system.

[0007]

According to one aspect of the present invention, there is provided a system for transferring data stored in a memory, comprising: a central processing unit; One or more module devices that perform processing, and a memory control device that controls input and output of data between the central processing unit or the one or more module devices and the memory, wherein the devices are commonly connected. And a first bus in which only the central processing unit serves as a bus master, and a second bus in which the devices are connected in common and only the memory control device serves as a bus master. Data transfer system.

According to this, only the central processing unit and only the memory control unit serve as bus masters of the first bus and the second bus, respectively. The control device can perform data transfer between the memory and the module device. Since each module device is commonly connected to the second bus, the memory control device can transfer data stored in the memory to a plurality of module devices at once.

Further, since the central processing unit is also commonly connected to the second bus, all the module units including the CPU can perform the data transfer processing with the same protocol.

According to a second aspect of the present invention, in the first aspect, each of the interfaces connecting each of the one or more module devices and the central processing unit has a function viewed from the first bus side. In addition, all of the interfaces for connecting each of the one or more module devices and the memory control device have the same function as viewed from the second bus side.

According to this, the function of the connection interface with the central processing unit of each module device viewed from the first bus side is common, and the memory of each module device viewed from the second bus side. Since the connection interface with the control device is common, the module device can be easily changed or added, and the module device can be handled socketably.

According to a third aspect of the present invention, in any one of the first and second aspects, the second bus is a dedicated protocol between the central processing unit or the one or more module units and the memory. It is characterized by being controlled by.

According to this, since the second bus is controlled by the dedicated protocol, data transfer between each module device and the memory is facilitated. Further, the invention according to claim 4 is the test method of the data transfer system according to any one of claims 2 and 3, wherein the same test data is transmitted to one or more buses via each interface on one bus side. Data transfer to a module device, and performing a test of the module device by determining whether a result of the test data processing in each of the module devices to which the test data is provided is a desired result. This is a test method for the system.

According to this, since the function of the connection interface with the central processing unit of each module device viewed from the first bus side is common, the same test data can be given to each module device. All test circuits for testing the module device are
You only need to prepare one.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a data transfer system according to an embodiment of the present invention.

This data transfer system uses an R (not shown)
A CPU (central processing unit) 100 that performs an operation according to a procedure described in advance in a storage medium such as an OM, and a plurality of module devices 200,..., 210 (only two are shown in FIG. 1 for easy understanding) And a dynamic random access memory for storing image data and the like
And a DRAM controller 300 connected to the DRAM 400 via an address line 401 and a data line 402 and performing a data transfer process between the DRAM 400 and each device.

A first bus (GBUS) in which only a CPU (central processing unit) 100 is a bus master has a G bus I / F (I / F is an interface) 120 and a G bus I / F.
/ F202, G bus I / F 212, and G bus I / F
The CPU (central processing unit) 10 via each of the F212
0, module device 200, module device 210, D
The RAM controller 300 is connected.

Further, a second bus (RBUS) in which only the DRAM controller 300 is a bus master includes an R bus I / F 110, an R bus I / F 201, and an R bus I / F 2
11 and each of the R bus I / F 310
PU (central processing unit) 100, module device 200,
The module device 210 and the DRAM controller 300 are connected.

First bus (hereinafter referred to as "GBUS")
Includes a GDAT that is a data transmission bus, a GADR that is an address transmission bus, a GCTRL that is a control signal transmission bus, and a GCLK that is a bus that transmits a clock supplied from a clock supply unit (not shown). A second bus (hereinafter, referred to as “RBUS”) is used for transmitting an RDAT that is a data transmission bus, an RCMD that is a transmission bus for a command related to data transfer, and a clock supplied from a clock supply unit (not shown). RCLK, which is a bus for transmission. And
The RBUS is configured such that data transmission between devices connected to the bus is controlled by a dedicated protocol.

Further, as viewed from the RBUS side, an interface function for connecting the module device 200 and the DRAM controller 300, and the module device 210 and the DR
The function of the interface for connecting to the AM controller 300 is configured to be the same as that of the GB controller.
The configuration is such that the function of the interface for connecting the module device 200 and the central processing unit 100 and the function of the interface for connecting the module device 210 and the central processing unit 100 are the same as viewed from the US side.

FIG. 3 shows the configuration of the R bus I / F. In this specification, only the elements particularly necessary for the description are described to facilitate the understanding. As shown in FIG.
/ F has a data conversion unit 600 for converting data transmitted and received via RDAT, and a decoding unit 610 for decoding a command transmitted and received via RCMD and generating a control signal corresponding to the decoding result. , RC
A clock supplied via the LK can be supplied to a necessary portion inside the device.

The data conversion performed by the data conversion unit 600 is, for example, bit length conversion for converting 16-bit data to 8-bit data, or changing the data access direction from bidirectional (reading and writing) to unidirectional (reading only). Conversion of the data access direction and the like can be mentioned. The control signal generated by the decoding unit 610 is sent to a predetermined location inside the device, and the device performs an operation according to the control signal. The control signal includes a signal indicating a valid period of the RBUS with respect to its own module device, a read / write signal, a buffer inside the module, an address signal of a register, and the like. As described above, since the R bus I / F has a function of performing a decoding process and generating a control signal for performing operation control inside the module device, it is only necessary to adapt and manufacture the interface unit itself for each module. It is easy to connect various module devices to the RBUS.

In this system, a command is transmitted and received via the RCMD, and the format of the command is, as shown in FIG. 4, a 4-bit operation code and data on the RDAT is a byte ("0") or a word ("1"). )) And a 6-bit operand, and various commands as shown in FIGS. 5 and 6 can be transmitted.

Now, if the module device 200 is the DRAM 4
The operation when a request to read data stored in 00 and the DRAM 400 transfers the data to the module device 200 will be described.

First, the DRAM controller 300 stores an AREQ (Ask for REQuest: DRA) on the RCMD every time the data transfer of the DRAM which has once started the service is completed.
M service request request) command, and receives a request for a DRAM data transfer service from each module device (DRAM service request request).

Next, upon receiving the AREQ command on the RCMD, the module device 200 that has issued the DRAM data read request immediately asserts a pre-allocated 1 bit on the RDAT in the same clock cycle as the AREQ command. (DRAM service request).

Next, the DRAM controller 300
The status of the DAT is monitored, and the status of the DRAM data transfer service request from each module device is grasped. Then, it is determined that the DRAM data transfer service to the module device 200 having the highest service priority among the module devices that have requested the DRAM data transfer service is selected as the next DRAM data transfer service. Note that the service priority may be set in advance, and in this embodiment, it is assumed that the service priority of the module device 200 is the highest.

Therefore, the DRAM controller 300
In order to notify the module device 200 that the DRAM data transfer service request has been accepted, the DRA from the module device 200 is requested in the next clock cycle.
TX using M data transfer service request ID as operand
An ID (Transmitt ID: service start ID transmission) command is issued. The DRAM data transfer service request I
D is set in advance for each module device (D
RAM service ID notification).

The DRAM controller 300 that has selected the next DRAM data transfer service starts a memory access operation to read desired data in the DRAM 400. The DRAM controller 300 uses the access time until read data is read from the DRAM to set an initial address and the like for an input buffer (not shown) of the module device 200 using the SETX.
This is executed using an (X address setting) command, a SETY (Y address setting) command, or the like.

When data reading from the DRAM 400 is started, the DRAM data is transferred on the RDAT. In synchronization with this DRAM data transfer, DR
The AM access addressing sequence command is transferred.

Specifically, INCX (X address increment) command, INCY (Y address increment) command, SETX (marker X address setting) command, SETY (marker Y address setting) command, GMX (marker X address Jump) command and GMY (marker Y address jump) command are used in synchronization with data
Any access address sequence in M page units can be expressed (DRAM data transfer).

Finally, the DRAM controller 30
0 is synchronized with the end of the DRAM data transfer service,
Issue a TXDONE (transfer end) command and
The RAM transfer service ends (DRAM data transfer ends).

Further, the other module device 201
The data stored in the M400 is requested to be read, and the data is transmitted from the DRAM 400 to the module device 20.
The transfer to 1 is performed in exactly the same manner. The difference from the previous data transfer is that when an AREQ command on the RCMD is received, there is a difference in the position where 1 bit to be asserted on the RDAT is allocated, and the TXID (Transmit
(t ID: service start ID transmission) The only difference is the DRAM data transfer service ID of the command, and the operation including control by the data transfer protocol is exactly the same.

As described above, the RBUS is controlled by the protocol dedicated to data transfer, so that large-capacity DRAM data transfer can be performed quickly. Further, independently of the DRAM data transfer using RBUS described above,
The operation control of each module device using GBUS can also be performed. For example, when the CPU 100 selects an operation mode of each module device or grasps an operation state of each module device, a control register or a status register (not shown) in each module device connected to the GBUS is used. By accessing C
The PU 100 can control the operation of each module device independently of the transfer of the DRAM data using the RBUS.

In this way, the CPU 100
, The module devices 200, ..., 2
01, while performing the control operation of the DRAM controller 300, the DRAM controller 300 becomes an RBUS bus master, and the CPU 100, the module device 200,
, And 201, the CPU 100 and the DR
The bus control can be performed independently of the AM controller 300. The DRAM controller 3
00 allows data stored in the DRAM 400 to be transferred to a plurality of module devices at once.

Further, since the RBUS is controlled by a dedicated protocol, the CPU 100, the module device 200,
.., 201, data transfer between the DRAM 400 is facilitated.

Furthermore, the function of the connection interface with the CPU 100 of each of the module devices 200,..., 201 as viewed from the GBUS side is common, and the memory of each of the module devices 200,. Since the connection interface with the control device is common, the module devices 200,..., 201 can be easily changed, added, etc., and the module devices can be handled socketably (easily exchangeable).

As shown in FIG. 1, a test circuit 500 for supplying test data for testing the module devices 200,..., 201 is provided so as to be able to supply data to the RDAT. The DRAM controller 300 supplies data to the module devices 200,.
It is possible to check whether or not the result of the processing performed at 0,..., 201 is a desired result, and to test the module devices 200,.

This is because the connection interfaces of the respective module devices 200,..., 201 are common as viewed from the RBUS side, and it is no longer necessary to provide a test circuit for each module device as in the related art.

[0040]

As described above, according to the first aspect of the present invention, only the central processing unit and only the memory control unit serve as the bus masters of the first bus and the second bus, respectively, and perform the central processing. While the device controls each module device, the memory control device can transfer data between the memory and the module device.

According to the second aspect of the present invention, the module device can be easily changed or added, and the module device can be handled socketably. According to the third aspect of the present invention, data transfer between each module device and the memory is facilitated.

Further, according to the fourth aspect of the present invention, it is possible to obtain an effect that it is sufficient to prepare one test circuit for testing a module device for all the module devices.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transfer system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional data transfer system.

FIG. 3 is a configuration diagram of an R bus I / F.

FIG. 4 is an explanatory diagram of a command format.

FIG. 5 is an explanatory diagram of a command.

FIG. 6 is an explanatory diagram of a command.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 CPU (central processing unit) 110 R bus I / F 120 G bus I / F 200 module device 201 R bus I / F 202 G bus I / F 210 module device 211 R bus I / F 212 G bus I / F 300 DRAM controller 310 R bus I / F 320 G bus I / F 400 DRAM 401 address line 402 data line 600 data conversion unit 610 decoding unit

Claims (4)

[Claims] 1. A system for transferring data stored in a memory, comprising: a central processing unit; one or more module units for performing predetermined data processing; and the central processing unit or the one or more modules A memory control device that controls input and output of data between the device and the memory, wherein each of the devices is commonly connected, and a first bus in which only the central processing unit is a bus master; A data transfer system, comprising: a second bus connected to the devices in common, and only the memory control device serving as a bus master. 2. The device according to claim 1, wherein the functions of each interface connecting each of the one or more module devices and the central processing unit as viewed from the first bus side are all the same. A data transfer system, wherein functions of each interface connecting each of one or more module devices and the memory control device are the same as viewed from the second bus side. 3. The memory device according to claim 1, wherein the second bus is controlled by a dedicated protocol between the central processing unit or the one or more module devices and the memory. Data transfer system. 4. A test method for a data transfer system according to claim 2, wherein the same test data is supplied to one or more module devices via each interface on one bus side. A test method for a data transfer system, comprising: determining whether a result of the test data processing in each of the module devices to which the test data is given is a desired result and performing a test of the module device.