JPH11161234A - Display microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display microcomputer by which power consumption can be reduced and flickers in a display screen can be surely prevented. SOLUTION: A display RAM 2 is divided into an even number address area and an odd number address area, and in a liquid crystal display time, dot data are outputted simultaneously from two corresponding even number address and odd number address in the display RAM 2 so as to be latched in a latch circuit 12. Latch data in the latch circuit 12 are sequentially latched in a latch circuit 13 by a 16 bit unit. The latch data in the latch circuit 13 are latched in a latch circuit 14. A drive circuit 15 converts the latch data in the latch circuit 14 into a driving signal for turning on/off a light so as to display characters on a liquid crystal panel 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display microcomputer suitable for displaying characters (characters, numerals, pictures, etc.) on a display panel (liquid crystal panel, etc.).

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional display microcomputer. In FIG. 3, (101)
Denotes a liquid crystal panel in which m common electrodes and n segment electrodes are arranged in a matrix, and a predetermined character is displayed by turning on or off a dot at an intersection of the common electrode and the segment electrode. (102) is RA for display
M, dot data constituting a character for one screen of the liquid crystal panel (101) is written at an address corresponding to a display position of the liquid crystal panel (101) on a one-to-one basis. The dot data written to and read from the display RAM (102) instructs lighting when the logical value is "1" and turns off when the logical value is "0". For each screen of the liquid crystal panel (101), Rewritten with the contents to be displayed. The reading speed of the dot data from the display RAM (102) is set so that the frequency until the liquid crystal display for one screen of the liquid crystal panel (101) is completed becomes a predetermined alternating frequency. . (103) is a parallel-serial conversion circuit, and a display RAM (102)
Is converted from the parallel state to the serial state from the dot data read in units of words. (10
Reference numeral 4) denotes an n-bit shift register, which sequentially shifts word-unit serial data output from the parallel-serial conversion circuit (103) in synchronization with the dot clock DCLK, and converts one line of dots of the liquid crystal panel (101). It holds data. (105) is an n-bit latch circuit for latching the n-bit dot data held in the shift register (104) in synchronization with the latch clock LCLK. Reference numeral (106) denotes a drive circuit for sequentially selecting a common electrode for each row of the liquid crystal panel (101) and for selecting a segment electrode according to latch data of the latch circuit (105). That is, the drive circuit (106) lights the intersection of the selected common electrode and segment electrode. This operation is
Repeating this operation completes character display for one screen of the liquid crystal panel (101).

The intersection of the common electrode and the segment electrode of the liquid crystal panel (101) is in a capacitively coupled state. FIG. 4 illustrates a voltage change state at the intersection of the common electrode and the segment electrode. In the characteristic diagram of FIG. B, the horizontal axis t indicates time, the vertical axis V indicates the absolute value of the voltage at the intersection of the common electrode and the segment electrode, the shaded area indicates the voltage range in which the liquid crystal display of the liquid crystal panel (101) flickers,
The period T indicates the time required for displaying one screen of the liquid crystal panel (101) (reciprocal of the alternating frequency). LCD panel (1
The intersection of the common electrode and the segment electrode of 01) is turned on by applying a voltage set at a predetermined duty and a predetermined bias between the common electrode and the segment electrode. However, since the common electrode and the segment electrode of the liquid crystal panel (101) are capacitively coupled, if a lighting voltage is applied only once between the common electrode and the segment electrode, the voltage between the common electrode and the segment electrode is reduced. The absolute value of （gradually decreases as indicated by the broken line according to the time constant based on the capacitive coupling, and when entering the shaded area, the liquid crystal panel (101) may be flickered. Therefore, a lighting voltage is repeatedly applied at a period T between the common electrode and the segment electrode of the liquid crystal panel (101) to prevent the voltage between the common electrode and the segment electrode from dropping to the shaded area. (101) is prevented from flickering.

[0004]

[Problem 1] For example,
The liquid crystal panel (101) is 32 dots vertically and 80 dots horizontally,
One word of the display RAM (102) is 8 bits, and each of the shift register (104) and the latch circuit (105) is 8 bits.
When the alternating frequency is set to 75 Hz in the liquid crystal display device composed of 0 bits (alternating frequency 75 Hz is a frequency at which the liquid crystal display does not flicker), the liquid crystal panel (101)
The ideal frequency for displaying one dot is 192 KHz (= 3
2 × 80 × 75 Hz). Actually, display RAM
Since the read time of (102), the conversion time of the parallel / serial conversion circuit (103), the shift time of the shift register (104), the latch timing time of the latch circuit (105), etc. are required, one dot display of the liquid crystal panel (101) is required. Is about 384 KHz, which is twice the ideal frequency. However, when the frequency required for one-dot display of the liquid crystal panel (101) increases to the above value, there is a problem that the current consumption of the display microcomputer increases. [Problem 2] The parallel-serial conversion circuit (103) and the shift register (104) are deleted, and the display RAM (1
02), a latch circuit for sequentially latching the read data in units of one word is added.
The frequency required for dot display is 48 KHz (= 384 KH
z ÷ 8), and the current consumption of the display microcomputer can be made smaller than [Problem 1]. Now, as the operation oscillation source of the microcomputer, RC / ceramic /
Any of the crystal oscillators is used. For example, when an RC / ceramic oscillator is used, the oscillation frequency of the RC / ceramic oscillator may be divided to the display frequency (48 KHz). Had an unsuitable problem.
On the other hand, although the crystal oscillator itself consumes a small amount of current, there is a problem that the oscillation frequency (32 KHz) cannot be multiplied to the display frequency (48 KHz). In particular, when dot display is performed at the oscillation frequency of the crystal oscillator, the alternating frequency becomes 50 Hz.
(= 32 kHz {2} 10} 32), that is, the voltage at the intersection of the common electrode and the segment electrode of the liquid crystal panel (101) drops to the shaded area in FIG. was there.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display microcomputer which consumes a small amount of current and does not cause character display on a display panel to flicker.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and character data for displaying a predetermined character on a display panel is stored in a pair at a display position of the display panel. A display RAM written to an address corresponding to 1; a first latch circuit for latching character data read from the display RAM;
A drive circuit for displaying a character corresponding to the latch data of the first latch circuit on the display panel.
A second latch circuit is provided between the output of M and the input of the first latch circuit for latching character data read from the display RAM in units of a plurality of words.

In addition, a display R for writing character data for displaying a predetermined character on the display panel at an address corresponding to the display position of the display panel on a one-to-one basis.
AM, a first-stage latch circuit for sequentially latching character data read from the display RAM in units of a plurality of bits, a next-stage latch circuit for collectively latching the latch data of the first-stage latch circuit, and the next-stage latch circuit And a drive circuit for displaying a character corresponding to the latch data on the display panel, wherein the display RAM is stored in a plurality of divided address areas and in each address in the plurality of divided address areas. It is characterized in that the number of output bits is such that character data can be output simultaneously. In particular, an address circuit is provided for simultaneously addressing each associated address in a plurality of divided address areas of the display RAM when a predetermined character is displayed on the display panel.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram for explaining a display microcomputer of the present invention. In FIG. 1, (1) is a liquid crystal panel (display panel) in which m common electrodes and n segment electrodes are arranged in a matrix, and the intersection of the common electrode and the segment electrode is turned on or off to display dots. Is what you do.

(2) a display RAM, in which dot data constituting a character for one screen of the liquid crystal panel (1) is written at an address corresponding to a display position of the liquid crystal panel (1) on a one-to-one basis. It is. The dot data written and read into the display RAM (2) instructs lighting when the logical value is "1" and turns off when the logical value is "0". Rewritten with the contents to be displayed. The reading speed of the dot data from the display RAM (2) is equal to that of the liquid crystal panel (1).
The frequency until the liquid crystal display for the screen is completed is set to be a predetermined alternating frequency.

The display RAM (2) has an even address area in which the least significant bit A0 of the address data has a logical value "0".
Further, the least significant bit A0 of the address data is divided into an odd address area having a logical value of "1", and has an independent output terminal for reading dot data in the even address area and the odd address area. That is, when addressing the display RAM (2) by the program of the CPU, one address is sequentially designated as in the past, and when addressing the display RAM (2) by the address counter for the liquid crystal display, Two even-numbered addresses and odd-numbered addresses determined from the lower second bit A1 onward of the address data are specified simultaneously. One machine cycle for executing a program instruction of the display microcomputer includes six states S1 to S6, as shown in FIG. S1, S3, and S5 constituting one machine cycle are used for addressing the display RAM (2) by the program counter of the CPU, and S2, S4, and S6 (inversion of S1, S3, and S5) are used for liquid crystal display. Display RAM with address counter
Used for addressing in (2). That is, the display RA
The address of M (2) can be specified by a single port, and the configuration of the display RAM (2) can be prevented from becoming complicated.

A switching circuit comprising AND gates (3) and (4) and an OR gate (5) is used for display by the CPU when the logical sum (S1 + S3 + S5) of S1, S3 and S5 constituting one machine cycle is at a high level. When the address of the RAM (2) is specified, the least significant bit A0 (= logical value “0”) of the even address of the value of the address register is displayed on the display RA.
M (2) is supplied to the address input, and the logical sum (S2 + S4) of S2, S4, and S6 constituting one machine cycle
When + S6) is at the high level, the least significant bit A0 (= logical value "0") fixed separately from the value of the address counter for liquid crystal display is switched to the address input of the display RAM (2) and supplied. Things. On the other hand, when the logical sum (S1 + S3 + S5) of S1, S3 and S5 constituting one machine cycle is at a high level, the switching circuit composed of the AND gates (6) and (7) and the OR gate (8) is used to display the RAM for display by the CPU. At the time of address designation in (2), the least significant bit A0 of the odd address in the value of the address register
(= Logical value “1”) is supplied to the address input of the display RAM (2), and S2, which constitutes one machine cycle,
When the logical sum of S4 and S6 (S2 + S4 + S6) is at the high level, the least significant bit A0 (= logical value "1") fixed separately from the value of the address counter for the liquid crystal display is displayed in the display RAM (2). It is supplied by switching to address input. When the address of the display RAM (2) is designated by the CPU, the least significant bit A0 has only one of the logical values "1" and "0" each time the address is designated. The least significant bit A0 of both the even and odd address areas in (2) is not determined simultaneously. Therefore, when addressing the display RAM (2) on the CPU side, reading is performed from either the even or odd address. On the other hand, the least significant bit A0 of the value of the address counter for the liquid crystal display is equal to the R for display.
In the even and odd address areas of AM (2), the logic values are always fixed to "0" and "1", respectively. Therefore, when addressing the display RAM (2) on the liquid crystal display side, each time addressing is performed, two even-numbered addresses and odd-numbered addresses are used in accordance with the address counter values An to A1 excluding the least significant bit A0. Reading is performed at the same time. AND
The switching circuit including the gates (9) and (10) and the OR gate (11) forms S1, S3,
When the logical sum of S5 (S1 + S3 + S5) is at a high level,
When the address of the display RAM (2) is specified by the CPU,
RAM for displaying An to A1 excluding least significant bit A0
The logical sum (S2 + S4 +) of S2, S4, and S6 that is supplied to the address input of (2) and constitutes one machine cycle
When S6) is at the high level, An to A1 excluding the least significant bit A0 of the value of the address counter for liquid crystal display are switched to the address input of the display RAM (2) and supplied. By providing the above three switching circuits, when the CPU specifies the address of the display RAM (2) in accordance with the timings of S1 to S6 constituting one machine cycle, the display RAM (2) has an even number or When writing or reading is performed by specifying one of the odd addresses and the display RAM (2) is addressed on the liquid crystal display side, two even numbers and ones corresponding to one-to-one of the display RAM (2) are used. Reading can be performed from both of the odd addresses.

The read data at the time of specifying the address of the display RAM (2) on the CPU side is the display RA (2).
The data is transferred to a peripheral circuit (not shown) via a data bus (not shown) for one word of M (2). However, the display RAM (2) is designed so that the write data of both the even and odd addresses can be transferred to the peripheral circuit.
The output terminal for two words in (2) must be connected to the data bus for one word, that is, the output terminal for two words in the display RAM (2) must be switched and transferred to the data bus for one word. . Here, the display RAM (2) is a pre-charge type static RAM, and the read data of any one of the unselected even-numbered and odd-numbered addresses does not change while all bits remain at the logical value “1”. Since it is determined that it has not been specified, the display RAM
There is no problem if the data bus for one word is used for the output terminal for two words in (2).

Reference numeral (12) denotes a two-word latch circuit, which synchronizes two-word dot data simultaneously output from two even-numbered and odd-numbered addresses of the display RAM (2) with a clock LCLK1 during liquid crystal display. And latch it. (13) is an n-bit latch circuit, which is composed of divided blocks in units of the number of bits of two words, and each divided block supplies clocks T1, T2, T3... Sequentially generated after the generation of the clock LCLK1. receive. That is, the latch circuit (13) uses the latch data of the latch circuit (12) as a unit to generate clocks T1, T2, T3,.
Are sequentially latched in synchronization with. (14) is an n-bit latch circuit for latching the latch data of the latch circuit (13) in synchronization with the clock LCLK2. (15) is a drive circuit, and a liquid crystal panel (1)
And a segment electrode is selected in accordance with the latch data of the latch circuit (14). That is, the drive circuit (15) turns on the intersection of the selected common electrode and segment electrode. When this operation is repeated m times, the liquid crystal panel (10
The character display for one screen of 1) is completed.

For example, the liquid crystal panel (1) has a length of 32 dots and a width of 80 dots, one word of the display RAM (2) has 8 bits, the latch circuit (12) has 16 bits, and the latch circuits (13) and (14) have In a liquid crystal display device composed of 80 bits each, it is assumed that the lowest alternating frequency is set to 75 Hz (alternating frequency 75 Hz is the lowest guaranteed frequency at which the liquid crystal display does not flicker). In this case, the display frequency per dot of the liquid crystal panel (1) is 24K.
Hz (= 384 KHz ÷ 16), which can be obtained by dividing the oscillation frequency (32 KHz) of the crystal oscillator.
When a crystal oscillator is used, the alternating frequency is 100H
Since z (= 32 KHz ÷ 2 ÷ 32 ÷ 5), which is higher than the lowest frequency, the liquid crystal display does not flicker.

As described above, when a liquid crystal display similar to the conventional one is performed, the current consumption can be reduced, and the flicker of the liquid crystal display can be reliably prevented. In the embodiment of the present invention, the display RAM (2) is divided into even and odd address areas. However, using the lower 2nd bit or more of the address data, 2 ↑ 2 (べ き is a power) or more is used. May be divided.

[0016]

According to the present invention, when a character is displayed on a display panel under the same display conditions as in the prior art, the current consumption can be reduced, and further, the flicker of the display panel can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram for explaining a display microcomputer of the present invention.

FIG. 2 is a waveform diagram showing one machine cycle of the display microcomputer.

FIG. 3 is a circuit block diagram for explaining a conventional display microcomputer.

FIG. 4 is a characteristic diagram illustrating a charge / discharge state of a liquid crystal panel.

[Explanation of symbols]

(1) Liquid crystal panel (2) Display RAM (3) (4) (6) (7) (9) (10) AND gate (5) (8) (11) OR gate (12) (13) Latch circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 5/24 650 G09G 5/24 650S

Claims (3)

[Claims] 1. A display RAM in which character data for displaying a predetermined character on a display panel is written at an address corresponding to a display position of the display panel on a one-to-one basis.
A first latch circuit for latching character data read from the display RAM; and a drive circuit for displaying a character corresponding to the latch data of the first latch circuit on the display panel. In the computer, a second latch circuit is provided between the output of the display RAM and the input of the first latch circuit for latching character data read from the display RAM in a plurality of words. Display microcomputer. 2. A display RAM in which character data for displaying a predetermined character on a display panel is written at an address corresponding to a display position of the display panel on a one-to-one basis.
A first-stage latch circuit for sequentially latching character data read from the display RAM in units of a plurality of bits; a next-stage latch circuit for batch-latching the latch data of the first-stage latch circuit; A drive circuit for displaying a character corresponding to latch data on the display panel, wherein the display RAM comprises: a plurality of divided address areas;
A display microcomputer having a sufficient number of output bits to simultaneously output character data stored at each address in a plurality of divided address areas. 3. An address circuit for simultaneously addressing each associated address in a plurality of divided address areas of the display RAM when displaying a predetermined character on the display panel. 3. The display microcomputer according to claim 2, wherein: