JPH0990911A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power required for driving a common data line connected to a data line driver and to suppress a radiation level of an unwanted electromagnetic wave from the common data line related to a liquid crystal display device(LCD). SOLUTION: This device is provided with the drivers 41 , 42 ,... driving respective data lines DLj in a liquid crystal panel 1 and a signal lines group 6 containing the common data line 7 transmitting the display data Dn outputted from a control circuit 2 and various control signals required for write-in and a display of the display data on respective pixels to the data line drivers, and is constituted so that the data line drivers are arranged on one side of the liquid crystal panel 1, and the inversion input function of the display data Dn is given to the drivers.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a liquid crystal display (L).
CD), and more particularly, to a technique of supplying a drive signal adapted when a liquid crystal panel is driven from one side in an LCD.

[0002]

2. Description of the Related Art With the recent miniaturization of personal computers and the like, further miniaturization of LCD is required. Therefore, as a method of reducing the outer shape of the LCD, there is known a method in which the lead-out portion of the electrode of the liquid crystal panel is one of the upper and lower sides. This is because the mounting area of the electrodes and the driving unit can be reduced by disposing the liquid crystal driving unit (in this case, the data line driver) on one side of the liquid crystal panel. Therefore, the mounting area of the liquid crystal panel is excluded from the entire LCD. The portion (so-called frame area) can be made relatively small.

Conventionally, a "vertical line inversion" driving method has been known as a technique for driving a liquid crystal panel from one side.
According to this driving method, the polarity of the write voltage of the display data to each pixel is inverted every one vertical line (that is, the data lines arranged in the vertical direction in the liquid crystal panel). Therefore, in this vertical line inversion driving method, it is necessary to invert all the bits of the display data for each dot and supply them to the data line driver.

In the conventional technique, the bit inversion of the display data is performed in synchronization with the data transfer clock in the display data conversion unit, and the display data conversion unit is
It was built in a control circuit for controlling the liquid crystal driver (scan line driver and data line driver). This control circuit typically provides signals and data necessary for performing various controls for writing and displaying display data to each pixel, based on display data and control signals input from the outside. It has the function of supplying to the driver. The various control signals generated by the control circuit are supplied to the data line driver via the common signal line group together with the display data bit-inverted by the display data conversion unit.

At this time, since the display data changes according to the change of the data transfer clock, in the process of transmitting the display data to the data line driver through the common data line, the input capacitance of the driver and the common data are transmitted. Charge and discharge are repeated for the stray capacitance of the line.

[0006]

As described above, in the prior art, the display data supplied from the display data conversion section to the data line driver via the common data line always changes every half cycle of the data transfer clock. Therefore, there has been a problem that the power required to charge / discharge (that is, drive) the input capacitance of the driver and the stray capacitance of the common data line is not negligible.

In particular, in a system in which a data line driver is divided into a plurality of driver units (ICs) to drive a liquid crystal panel having a large display capacity, both the input capacity of the driver and the stray capacity of the common data line increase. The problem of such power consumption becomes more prominent. Also, because the signal level is frequently inverted on this common data line, the electromagnetic wave emission level from the common data line relatively increases, and therefore, the conditions defined by the radio wave standards are cleared. There was also the disadvantage that it was difficult to do.

The present invention has been made in view of the above problems in the prior art, and reduces the power required to drive the common data line connected to the data line driver and eliminates the unnecessary power from this common data line. An object of the present invention is to provide a liquid crystal display device capable of suppressing the emission level of electromagnetic waves.

[0009]

In order to solve the above-mentioned problems of the prior art, the present invention increases the number of signal level inversions on a common data line (that is, the frequency of display data propagating through the common data line). The display data necessary for driving the liquid crystal panel on one side can be supplied to the driver without performing the above operation.

Therefore, according to the present invention, a liquid crystal panel in which scan lines and data lines connected to each pixel are arranged in a matrix, and a first driver (scan line. Driver), a second driver (data line driver) for driving each data line in the liquid crystal panel, and the first and second drivers based on display data and control signals input from the outside. On the other hand, a control circuit that outputs various control signals necessary for writing and displaying the display data to the pixels together with the display data, and a control signal and the display data output from the control circuit to the second control signal. A signal line group including a common data line for transmitting to the driver, the second driver being disposed on one side of the liquid crystal panel, The liquid crystal display device is provided, wherein the driver that gave the inverting input function of the display data.

According to the configuration of the liquid crystal display device of the present invention, the second driver (data line driver) which connects the bit inversion function of the display data, which has been conventionally performed in the control circuit, to the subsequent stage of the common data line. The display data supplied to the data line driver after propagating through the common data line does not change depending on the cycle of the data transfer clock unlike the conventional type. That is, the frequency of the display data propagating on the common data line does not increase.

This makes it possible to reduce the power required to charge and discharge the stray capacitance of the common data line and the input capacitance of the driver. This is more advantageous especially in the method of driving the data line by dividing into a plurality of driver units. Further, since the number of times the signal level is inverted on the common data line does not increase, the level of electromagnetic waves emitted from this common data line can be suppressed. Therefore, it becomes possible to easily meet the conditions defined by the radio wave standards and the like.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of a liquid crystal display device according to an embodiment of the present invention. In this embodiment, the liquid crystal panel in the active matrix type TFT LCD is driven by "vertical line inversion" from one side. In FIG. 1, reference numeral 1 denotes a liquid crystal panel, in which P _ij (i, j = 1,2, ...) Represents a minimum display unit called “pixel”. Each pixel P _ij has a plurality of scan lines SL _i (i = 1, 2, ..., M) arranged in a matrix.
And a plurality of data lines DL _j (j = 1,2, ..., n, ...)
Are arranged at the intersection of.

Reference numeral 2 denotes a control circuit for controlling the entire LCD, which includes display data Dn and a control signal (clock C which is given in synchronization with the display data Dn) inputted from the outside.
K, a horizontal synchronizing signal HS, a vertical synchronizing signal VS, etc.), and has a function of performing various controls for writing and displaying the display data Dn to each pixel. This control circuit 2
Is a variety of control signals (start signals T1, T2, etc.) necessary to drive the liquid crystal panel 1 via the respective drivers described later.
The clocks CK1 and CK2, the latch signal LP, and the data inversion signal INV) are output together with the display data Dn.

Reference numeral 3 denotes a scan line driver integrated into an IC, and each scan line S in the liquid crystal panel 1 in response to control signals T2 and CK2 supplied from the control circuit 2.
It has a function of sequentially driving L _i . 4 ₁ , 4 ₂ .....,
Indicates a data line driver unit integrated into an IC, and control signals T1, CK1, LP, INV, display data Dn, and a drive voltage Vn corresponding to a gradation level supplied from a reference power supply circuit 5 described later are respectively set. in response, the corresponding data line group in the liquid crystal panel 1 (for example, in the case of the driver unit 4 _1, the data line DL ₁ through DL _n)
Has the function of driving. As shown, the data line driver units 4 ₁ , 4 ₂ , ..., Are connected to each other in a cascade connection. That is, one data line driver start signal T1 that is input from the control circuit 2 to the data line driver unit 4 ₁ of the first stage as a whole successively sends it to the next stage of the driver unit is configured.

Reference numeral 5 denotes a reference power supply circuit, which has a function of generating a plurality of drive voltages to be applied to each of the data lines DL _j described above, appropriately selecting, switching and amplifying the drive voltages and outputting the drive voltage Vn. Have Reference numeral 6 denotes a signal line group, which is display data D output from the control circuit 2.
n and control signals CK1 and L related to data line driving
P, INV for each data line driver unit 4 ₁ , 4
It is intended to be communicated to ₂ . The signal line group 6 includes display data Dn, clock CK1, and
It has a common data line 7, signal lines 8, 9 and 10 for transmitting the latch signal LP and the data inversion signal INV.

The characteristics of the liquid crystal display device according to this embodiment are as follows.
That is, each data line driver unit 4 ₁ , 4 ₂ , ..., Arranged on one side of the liquid crystal panel 1 is provided with a reverse input function of the display data Dn. Below, the data line
The internal structure of the driver unit will be described. In FIG. 2, each data line driver unit (in the illustrated example,
The configuration of the data line driver unit 4 ₁ ) is shown.

In the configuration shown in the figure, the feature of the present invention is that an exclusive OR gate 15 responsive to the display data Dn and the data inversion signal INV is provided in the first stage of the driver unit as a data inversion input function. . Furthermore, the data line driver unit 4 ₁ includes a shift register 20, respectively the display data Dn first memory 30 with a capacity of the number of bits (bit display data Dn after inversion ') ₁ to 30 _n and the second Memory 40 ₁ to 40 _n
, Decoders 50 ₁ to 50 _n , and selectors 60 _{1 to} 60
have _n and.

In such a configuration, the shift register 20
Starts its operation by the start signal T1 supplied from the control circuit 2 for each display line, and proceeds by the clock CK1 supplied via the signal line 8 to generate the timing signals TS _{1 to} TS _n . First memory 30 ₁ to 30
_{The n} takes in the bit-reversed display data Dn ′ output from the exclusive OR gate 15 in response to the timing signals TS _{1 to} TS _n . The second memories 40 ₁ to 40 _n have the first memory
After the data is fetched in the memories 30 ₁ to 30 _{n of the same} , the data in the first memory is responded to the latch signal LP supplied via the signal line 9 before the data of the next display line arrives. Take in. Next, the decoders 50 _{1 to} 5
0 _n decodes the digital data stored in the second memories 40 ₁ to 40 _n . Selector 60 _{1 to} 60 _n
Selects a prescribed drive voltage Vn based on the decoding result. That is, the selectors 60 _{1 to} 60 _n are a kind of D / A for generating analog signals corresponding to the digital data stored in the second memories 40 ₁ to 40 _n.
Functions as a converter. The specified drive voltage Vn selected in this way is output to the corresponding data lines DL _{1 to} DL _n in the liquid crystal panel.

Although not shown in the figure because it has nothing to do with the gist of the present invention, the scan line driver 3 is also constructed in the same manner and includes a shift register and each scan line SL _i.
And a driver provided corresponding to. In such a configuration, the shift register starts its operation by the start signal T2 supplied from the control circuit 2 and advances by the clock CK2 similarly supplied from the control circuit 2 to shift each scan line SL _i in the liquid crystal panel 1. Signals for driving are sequentially generated. The start signal T2 has the same period as the vertical synchronizing signal VS described above, and the clock C
K2 has the same cycle as the horizontal synchronizing signal HS. Then
Each driver outputs the TF of each pixel from the output of the shift register.
Performs level conversion to a voltage that can control ON / OFF of T,
It functions as a binary output circuit for outputting to the corresponding scan line SL _i . As a result, the gate voltage of the TFT, which is an analog switch, can be controlled to turn on / off the switch function, and each data line DL _j output from the data line driver units 4 ₁ , 4 ₂ , ... The signal voltage of the above display data is T for each display line.
It is possible to write to the liquid crystal capacitance through the FT.

FIG. 3 shows an example of operation timing waveforms of the above-mentioned data line driver unit, and
FIG. 4 shows an example of drive waveforms output by the data line driver unit. As shown in FIG. 3, as the data inversion signal INV, a signal that is inverted every cycle of the clock CK1 is used. Therefore, the data inversion signal INV is supplied to the exclusive OR gate 1 together with the display data Dn.
5 (see FIG. 2), when the display data Dn is constant at the “L” level as shown in FIG.
The output Dn ′ of the R gate 15 becomes a signal inverted every one cycle of the clock CK1.

That is, as shown in detail in FIG. 4, the display data for even lines and the display data for odd lines with respect to each data line to be driven have a relationship of being inverted for each data bit. There is. As described above, according to the present embodiment, the bit inversion function of the display data Dn is included in each of the data line driver units 4 ₁ , 4 ₂ , ... OR
Since it has the gate 15), it propagates through the common data line 7 and each driver unit 4 ₁ , 4 ₂ ,.
The display data Dn supplied to ... Does not change depending on the cycle of the data transfer clock as seen in the prior art, and therefore its frequency does not increase.

This makes it possible to greatly reduce the power required to charge and discharge the stray capacitance of the common data line 7 and the input capacitance of each driver unit. In the present embodiment, since the data lines are driven by being divided into a plurality of driver units, such an effect is more remarkable than the case where the data line driver is provided independently.

Further, since the number of times the signal level is inverted on the common data line 7 does not increase, the level of unnecessary electromagnetic waves radiated from this common data line 7 can be suppressed low. This makes it possible to easily meet the conditions defined by the radio wave standards and the like. In the above-described embodiment, the data line driver is divided into a plurality of driver units and driven for a liquid crystal panel having a relatively large display capacity. However, depending on the display capacity, a plurality of driver units are not always required. It is needless to say that the data line driver may be provided independently.

[0025]

As described above, according to the present invention, it is necessary to drive the common data line by providing the data line driver connected to the subsequent stage of the common data line with the bit inversion function of the display data. The power can be reduced and the level of unnecessary electromagnetic waves emitted from this common data line can be suppressed,
It is possible to easily clear the conditions defined by the radio wave standards and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention.

2 is a block diagram showing a configuration of each data line driver unit in FIG. 1. FIG.

FIG. 3 is a timing diagram showing an example of the operation of the driver unit in FIG.

FIG. 4 is a diagram showing an example of drive waveforms output from the driver unit of FIG.

[Explanation of symbols]

1 ... liquid crystal panel 2 ... control circuit 3 ... first driver (scan line driver) 4 _1, 4 ₂ ... second driver (data line driver unit) 5 ... reference power supply circuit 6 ... signal line group 7 ... Common Data lines 8 to 10 ... Signal line 15 ... Exclusive OR gate Dn, Dn '... Display data CK, CK1, CK2 ... Clock DL _j ... Data line HS ... Horizontal sync signal INV ... Data inversion signal LP ... Latch signal _Pij ... Pixel SL _i ... Scan line T1, T2 ... Start signal VS ... Vertical sync signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mikio Oshiro 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Satoshi Sekido 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (4)

[Claims] 1. A liquid crystal panel (1) in which scan lines (SL _i ) and data lines (DL _j ) connected to each pixel (P _ij ) are arranged in a matrix, and each scan line in the liquid crystal panel is driven. a first driver (3), said second driver for driving the data lines in the liquid crystal panel (4 _1, 4 _2, .........) and the display data input from the outside (Dn) and control Based on signals (CK, HS, VS), various control signals necessary for writing and displaying the display data in each pixel are output to the first and second drivers together with the display data. A control circuit (2); and a signal line group (6) including a common data line (7) for transmitting a control signal and display data output from the control circuit to the second driver, Driver of the above Place it on one side of the LCD panel,
A liquid crystal display device characterized in that the second driver is provided with an inversion input function of the display data. 2. The second driver has a plurality of driver units (4 ₁ , 4 ₂ , ...), which are provided in correspondence with a predetermined number of data line groups in the liquid crystal panel. , Each driver unit inputs display data (Dn) independently from the common data line, and sequentially sends the start control signal (T1) input from the control circuit to the driver unit at the first stage to the driver unit at the next stage. The liquid crystal display device according to claim 1, wherein one driver is configured as a whole. 3. The driver circuit includes a gate circuit (15) which responds to display data (Dn) and a data inversion signal (INV) input through the signal line group.
And display data (Dn ′) output from the gate circuit
To a clock (CK
Circuits taken in response to 1) (20, 30 ₁ to 30 _n )
And a circuit (40 ₁ to 40 _n ) for holding the fetched display data in response to a latch signal (LP) input via the signal line group, and defining according to the held display data. Drive voltage (Vn) of the selected liquid crystal panel and corresponding data line groups (DL _{1 to} DL _n ) in the liquid crystal panel.
3. The liquid crystal display device according to claim 2, further comprising a circuit (50 ₁ to 50 _n , 60 _{1 to} 60 _n ) for driving the liquid crystal display device. 4. The gate circuit is constituted by an exclusive OR gate (15), and the gate circuit is provided with 1 of the clock (CK1).
The liquid crystal display device according to claim 3, wherein a signal (INV) that is inverted every cycle is input as the data inversion signal.