JP3593448B2 - Liquid crystal display device and data signal line driver - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology that is effective in reducing the power consumption of a liquid crystal display device, particularly a liquid crystal display device incorporated in a portable information terminal or the like.
[0002]
[Prior art]
2. Description of the Related Art A simple matrix type liquid crystal display device of the STN (Super Twisted Nematic) type is widely used as a display device of a notebook computer or the like.
[0003]
FIG. 5 is a block diagram showing a schematic configuration of a conventional STN type simple matrix type liquid crystal display device, wherein 101 is a display control device, 102 is a power supply circuit, and LCD is a liquid crystal display panel.
[0004]
The liquid crystal display panel LCD includes a pair of glass substrates arranged to face each other with a liquid crystal interposed therebetween, and extends on the liquid crystal side of one of the glass substrates in the X direction and is arranged in the Y direction. M common electrodes (scanning lines) are formed, and each of the m common electrodes is connected to a corresponding common driver (IC-C1 to IC-C5).
[0005]
On the liquid crystal side of the other glass substrate, n segment electrodes (data lines) extending in the Y direction and juxtaposed in the X direction are formed. The electrode is divided into upper and lower two, and each of the n divided segment electrodes is a corresponding upper segment driver (IC-U1 to IC-Un) or a corresponding lower segment driver. (IC-L1 to IC-Ln).
[0006]
The intersections of the plurality of segment electrodes and the plurality of common electrodes constitute a pixel region, and each of the upper segment drivers (IC-U1 to IC-Un) and each of the lower segment drivers (IC-L1 to IC-Ln). ) And the common drivers (IC-C1 to IC-C5) apply the respective drive voltages to the plurality of segment electrodes and the plurality of common electrodes to drive the pixels.
[0007]
In FIG. 5, a liquid crystal panel display control device 101 controls each segment driver (IC-U1 to IC-Un, IC-L1 to IC-Ln) based on a display control signal and display data transferred from a host computer or the like. And controls each common driver (IC-C1 to IC-C5).
[0008]
The power supply circuit 102 generates different data signal line driving voltages VH, VM, VL, and scanning line signal driving voltages VxH, VxL, Vcc, and GND, and outputs the voltages VH, VM, VL, Vcc, and GND, respectively. The voltage is supplied to the segment drivers (IC-U1 to IC-Ln), and the voltages of VxH, VM, VxL, Vcc and GND are supplied to the common drivers (IC-C1 to IC-C5).
[0009]
Further, in a simple matrix type liquid crystal display device, a so-called alternating current is used in which each driving voltage applied to the plurality of segment electrodes and the plurality of common electrodes is inverted at a predetermined cycle so that no DC voltage is applied to the liquid crystal. A driving method is adopted.
[0010]
FIG. 6 is a diagram for explaining an example of the data signal line driving voltage applied to the segment electrodes of the liquid crystal panel LCD shown in FIG. 5 and the scanning line signal driving voltage applied to the common electrodes.
[0011]
In the example shown in FIG. 6, when the AC signal M is at a high level, the drive voltage VL is supplied from the power supply circuit 102 to each segment electrode of the display data “1”, and the segment electrode of the data “0” is supplied to each segment electrode. Is supplied with a drive voltage VH from the power supply circuit 102 and is applied thereto.
[0012]
Similarly, when the AC signal M is at the low level, the drive voltage VxH supplied from the power supply circuit 102 is applied to the selected common electrode. When the AC signal M is at the high level, the power supply is applied to the selected common electrode. The drive voltage VxL supplied from the circuit 102 is applied, and the drive voltage of VM supplied from the power supply circuit 102 is applied to the unselected common electrodes regardless of whether the AC signal M is at a high level or a low level. You.
[0013]
FIG. 3 is a block diagram of the conventional segment driver shown in FIG.
[0014]
The segment driver shown in FIG. 3 includes a shift register circuit 301, a bit latch circuit 302, a line latch circuit 303, an output circuit 304, and a random logic circuit 310. Note that the random logic circuit 310 includes a standby circuit 307 that sets one segment driver to a standby state when a data latch is not required. Reference numeral 308 denotes an EIO1 circuit, and 309 denotes an EIO2 circuit, which inputs a carry signal from the preceding segment driver in accordance with the shift direction of the segment driver, and outputs the internal carry signals CAR1, CAR2 to the shift register circuit 301 and the standby signal STBY to the standby circuit 307. Or a carry signal is output to the next-stage segment driver. FIG. 3 shows a segment driver having 240 outputs, and Y1 to Y240 indicate output terminals.
[0015]
Next, the data fetch and output operations of the segment driver shown in FIG. 3 will be described.
[0016]
In the random logic circuit 310, the display data latch clock CL2 input from the display control device 101 is converted into an internal data latch clock SCL2. Based on the internal data latch clock SCL2, the shift register circuit 301 A data capture signal 302 is generated and output to the bit latch circuit 302.
[0017]
Further, 4-bit display data DATA input from the display control device 101 is also converted into internal data SD. The internal data latch clock SCL2 and the internal data SD are fixed at the low level in the standby state.
[0018]
The bit latch circuit 302 latches the internal data SD based on a data fetch signal input from the shift register circuit 301.
[0019]
Although not shown, the line latch circuit 303 latches the display data captured by all the bit latch circuits 302 based on the output timing control line clock CL1, and outputs the display data to the output circuit 304.
[0020]
The output circuit 304 converts the voltage level of the display data input from the line latch circuit 303 into a high voltage level for driving the liquid crystal, and selects a three-level data signal line driving voltage supplied from the power supply circuit 102. Therefore, the above-described AC operation is performed from the data converted to the high voltage level and the AC signal M, and one of the three-level data signal line driving voltages supplied from the power supply circuit 102 is converted into each segment. Output to electrodes (data signal lines).
[0021]
FIG. 7 shows an operation state diagram of each segment driver for each one-line data writing period.
[0022]
In FIG. 7, as shown in FIG. 5, display data for one line arranged in the X direction is output by n segment drivers. In this case, each of the segment drivers (IC-U1 to Un, IC-L1 to Ln) starts operation by a carry signal (EIO1 or EIO2) described later, and performs an operation of fetching display data. The segment drivers (IC-U1 to Un, IC-L1 to Ln) to which the carry signal is not input do not need to take in the display data, and thus are in a standby state in which the internal operation is stopped. Further, the segment drivers (IC-U1 to Un, IC-L1 to Ln) which have finished taking in the display data stop the internal operation and enter the standby state. Conventionally, each of the segment drivers (IC-U1 to Un, IC-L1 to Ln) is set to a standby state for each unit to reduce power consumption.
[0023]
FIG. 4 shows a timing chart in the segment driver, showing the carry signal (EIO1 or EIO2) and the operation inside the segment driver.
[0024]
FIG. 4 shows an example in which the shift register 301 shown in FIG. 3 shifts the data fetching signal from left to right, so that the carry signal bar EIO1 is input, the carry signal bar EIO2 is output, and Input is made to carry inputs of the segment drivers (IC-U1 to Un, IC-L1 to Ln) of the stage. Although the inside of the segment driver is divided into internal circuits as shown in FIG. 3, the operation starts in all the circuits almost simultaneously with the input of the carry signal EIO1, and the internal data buses SD and All the internal data latch clocks SCL2 were operated.
[0025]
[Problems to be solved by the invention]
In the above prior art, the standby state can be controlled only by one segment driver, and the power consumption is insufficient.
[0026]
SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional technique, and an object of the present invention is to provide a technique that enables a liquid crystal display device to reduce power consumption of a liquid crystal driving device. Is to do.
[0027]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0028]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0029]
According to one aspect of the present invention, a shift register, a bit latch circuit, a line latch circuit, and an output circuit of a segment driver are divided into blocks every arbitrary number of outputs, and each block has a standby function. The circuit stops except for latching data.
[0030]
According to another aspect of the present invention, the internal data bus and the internal data latch clock are also divided for each block unit, and the divided internal data bus and internal data latch clock also have a standby function. During the stop, the divided internal data bus and the internal data latch clock are also stopped.
[0031]
According to another aspect of the present invention, the internal data bus and the internal data latch clock are also divided for each block unit, and the divided internal data bus and internal data latch clock also have a standby function, and To start the operation, a start signal from the preceding block is used, and to stop the operation of the block, a stop signal from the operating block is used.
[0032]
According to the above configuration, the standby function is not configured in units of one liquid crystal driving device, but is subdivided internally, so that power consumption is reduced by the subdivision.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention in which the present invention is applied to an STN type simple matrix type liquid crystal display device will be described in detail with reference to the drawings.
[0034]
In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
[0035]
FIG. 1 shows an embodiment of the present invention and shows a block diagram of a segment driver.
[0036]
The shift register 301, the bit latch circuit 302, the line latch circuit 303, and the output circuit 304 are divided into blocks for every 40 outputs, and a standby circuit 305 is provided for each block. Here, SSSD indicates a data bus in the block, and SSSCL2 indicates a data latch clock signal line in the block. Further, the internal data bus SSD and the internal clock signal line SSCL2 are also divided for each block, and the standby circuit 306 is provided for each of the divided internal data bus SSD and the internal clock signal line SSCL2.
[0037]
In addition, the random logic circuit 310 includes a standby circuit 307 that sets a segment driver in a standby state in a unit as in the related art. The internal data bus SD and the internal clock signal line SCL2 are input to the standby circuit 307 to the standby circuit 306.
[0038]
An output timing control line clock CL1, 4-bit display data DATA, a display data latch clock CL2, an AC signal M, and carry signals EIO1 and EIO2 are input to the random logic circuit 310.
[0039]
FIG. 2 shows a timing diagram of the block shown in FIG. The right shift (Y1 → Y240) will be described below for the sake of explanation, but the same applies to the left shift (Y240 → Y1).
[0040]
Until the carry signal (EIO1) is input from the liquid crystal driving device at the preceding stage, the inside of the segment driver is all in the standby (stop) state as in the related art.
[0041]
When the carry signal (EIO1) is input, the internal logic circuit, the internal data bus SD, and the internal clock signal SCL2 start operating. The standby circuits 306 (1), 306 (2), 306 (3) are released from the standby state, and the internal data buses SSD (1), SSD (2), SSD (3), internal clock signal SSCL2 (1), SSCL2 (2) and SSCL2 (3) operate. Further, the standby state of the standby circuit 305 (1) is released, the intra-block data bus SSSD (1) and the intra-block clock signal SSSCL2 (1) in the block ICBLK1 operate, and the display control device 101 in the latch circuit 302 of the block ICBLK1. The input display data DATA is latched.
[0042]
Since the display data DATA is supplied using a 4-bit data bus and 1-bit data is latched at one output, the number of pulses of the data latch clock signal CL2 is required to latch 40-output data. Becomes 10.
[0043]
When latching the data of the outputs Y1 to Y40, the block ICBLK1 transfers the carry to the next block, and the standby circuit 305 (1) enters the standby state, and the intra-block data bus SSSD (1) and the intra-block clock signal SSSCL2 (1). Is fixed at a low level, and the circuit inside the block is stopped. In addition, the standby circuit 306 (1) enters the standby state, and the internal data bus SSD (1) and the internal clock signal SSCL2 (1) are also fixed at the low level to stop the operation.
[0044]
Next, the standby circuit 305 (2) is changed from the standby state to the operating state by the carry input from the block ICBLK1, and the intra-block data bus SSSD (2) and the intra-block clock signal SSSCL2 (2) are supplied to the block ICBLK2 to display data. Latched. When the data of the outputs Y41 to 80 is latched, the block ICBLK2 transfers the carry to the next block, and the standby circuit 305 (2) enters the standby state, and the intra-block data bus SSSD (2) and the intra-block clock signal SSSCL2 (2). Is fixed at a low level, and the circuit inside the block is stopped. In addition, the standby circuit 306 (2) enters the standby state, and the internal data bus SSD (2) and the internal clock signal SSCL2 (2) are fixed at the Low level to be in the stop state.
[0045]
The block ICBLK3 operates similarly.
[0046]
Next, the internal data bus SSD (4), internal clock signal SSCL2 (4), and block ICBLK4 are changed from the standby state to the operating state by the carry input from the block ICBLK3, and the block ICBLK4 latches the display data.
[0047]
When the data of the outputs Y121 to 160 is latched, the block ICBLK4 transfers the carry to the next block and enters a standby state, and fixes the in-block data bus SSSD (4) and the in-block clock signal SSSCL2 (4) to Low level. Stop the circuit. Note that the internal data bus SSD (4) and the internal clock signal SSCL2 (4) maintain their operating states to transmit data and clock to the block ICBLK (5).
[0048]
The internal data bus SSD (5), the internal clock signal SSCL2 (5), and the block ICBLK5 are changed from the standby state to the operating state by the carry input from the block ICBLK4 to latch the display data. When the data of the outputs Y161 to 200 is latched, the block ICBLK5 transfers the carry to the next block, enters a standby state, and fixes the intra-block data bus SSSD (5) and the intra-block clock signal SSSCL2 (5) to Low level, Stop the internal circuit. Note that the internal data bus SSD (5) and the internal clock signal SSCL2 (5) also maintain the operating state as in the previous stage.
[0049]
The block ICBLK6 operates similarly. When the data of the outputs Y201 to 240 is latched, the carry EIO2 is output to the next-stage segment driver, and the internal data bus SD and the internal clock signal SCL2 are fixed to the low level by the standby circuit 307, and the entire segment driver is set to the standby state and the internal circuit To stop.
[0050]
As described above, the size of the circuit that operates can be reduced as compared with the related art, so that low power consumption can be achieved. In the liquid crystal driving circuit, the width of the wiring is reduced, the thickness of the insulating film of the stacked wiring tends to be thinner, and the capacitance and resistance of the wiring are increased. For this reason, power consumption by wiring cannot be ignored, and power consumption can be reduced by stopping signals as in the above configuration.
[0051]
FIG. 8 is a circuit diagram at the time of outputting 320, and FIG. 9 is a timing chart thereof. The operation is the same as in the case of 240 outputs. However, when the carry signal (EIO1) from the liquid crystal driving device at the preceding stage is input, the internal data buses from which the standby mode is released are SSD (1), SSD (2), SSD (3), and SSD (4). . In the case of 320 outputs, first, the standby of the blocks ICBLK1 to 4 related to the outputs 1 to 160 is released, and after the output Y160 is latched by the block ICBLK4, the remaining half of the internal data buses SSD (5), SSD (6), The standby of the SSD (7) and the SSD (8) is released.
[0052]
Next, the operations of the standby circuits 305 and 306 will be described for the right shift (from Y1 to Y240).
[0053]
First, the standby operation in the block ICBLK2 in FIG. 1 will be described with reference to FIGS. FIG. 10 is a circuit diagram of the standby circuit 305, and FIG. 11 is an operation timing chart of the standby circuit 305. In FIG. 11, SOUT is a data fetch signal of the latch circuit 302 output from the shift register circuit 301, SOUT1 is a first data fetch signal of the block ICBLK1, and SOUT10 is a last data fetch signal.
[0054]
The standby circuit 305 shown in FIG. 10 first receives the reset signal of the flip-flop circuit FSR1 on the signal line CLEAR, fixes the outputs of the intra-block data bus SSSD and the intra-block clock SSSCL2 to Low level, and is in a standby state.
[0055]
To release the standby state of the standby circuit 305, the data fetch signal SOUT from the shift register circuit 301 is used. As an example, a case where the standby of the block ICBLK2 is released will be described.
[0056]
As shown in FIG. 11, at the timing when the data of the output Y40 is taken into the latch circuit 302 in the block ICBLK1, the data taking-in signal SOUT10 is outputted. The data capture signal SOUT10 is input to the signal line SET_N of the standby circuit 305 shown in FIG. 10 as a standby release signal of the block ICBLK2.
[0057]
When the signal line SET_N goes low (however, the signal line SET_N is valid at low level), the standby signal STBYN is fixed at high level by the flip-flop circuit FSR1, and the internal data bus SSD and the internal clock SSCL2 are respectively set in the block. It outputs to the data bus SSSD and the clock SSSCL2 in a block.
[0058]
Next, in order to return to the standby state, when the data of the output Y80 is taken into the latch circuit 302 in the block ICBLK2, the data taking-in signal SOUT from the shift register circuit 301 of the block ICBLK2 is used as the carry signal of the block ICBLK2. Input to the signal. When the carry signal RESET_N is input, the standby signal STBYN is fixed at a low level, the output of the intra-block data bus SSSD and the intra-block clock SSSCL2 is fixed at a low level, and the block ICBLK2 enters a standby state.
[0059]
As described above, the release of the standby state of the clock SSSCL2 in the block is canceled by using the data capture signal of the preceding block, so that the standby state of the clock SSSCL2 in the block is released in advance for the data captured in the latch circuit 302. Improve the setup and hold time margin for latching data. Further, the flip-flops F / F (A) and F / F (B) cause the block ICBLK2 to be in the standby state two cycles of the clock signal SSCL2 after the input of the carry signal RESET_N. Can be imported.
[0060]
FIG. 12 is a circuit diagram of the standby circuit 306.
[0061]
FIG. 13 is an operation timing chart of the standby circuit 306.
[0062]
The operation of the standby circuit 306 between the internal data buses SSD (2) and SSD (3) in FIG. 1 will be described with reference to FIGS. When the operation is performed from the block ICBLK1, the reset signal of the shift register (the above-described signal CLEAR) is input as the SET_N signal. When the signal line SET_N is input, the flip-flop circuit FSR fixes the signal line STBYN2 to High level, and connects the internal data bus SSD (3) and the internal clock signal SSCL2 (3) to the internal data bus SSD (2) and the internal data bus SSDL2, respectively. Output to the clock signal SSCL2 (2). As the signal RESET_N, the RES_N signal generated by the standby circuit 305 is input. When the RES_N signal is input, the standby signal STBYN2 is fixed at a low level, the outputs of the internal data bus SSD (2) and the internal clock signal SSCL2 (2) are fixed at a low level, and a standby state is set.
[0063]
Next, the operation of the standby circuit 306 between the internal data buses SSD (5) and SSD (6) in FIG. 1 will be described with reference to FIG. As the signal SET_N, a carry signal of the last-stage shift register of the block ICBLK4 is input to the signal SET_N. When the signal SET_N is input, the flip-flop circuit FSR fixes the standby signal STBYN2 to High level and outputs the internal data buses SSD (5) and SSCL2 (5) to the internal data buses SSD (6) and SSCL2 (6), respectively. I do. The signal RESET_N inputs a reset signal of the shift register (the above-mentioned CLEAR). When the signal RESET_N is input, the standby signal STBYN2 is fixed at a low level, the outputs of the internal data bus SSD (2) and the internal clock signal SSCL2 (2) are fixed at a low level, and the apparatus enters a standby state. When the reset signal (CLEAR described above) of the shift register is not input and the data latch is completed up to the last stage, the entire chip enters a standby state, the internal data bus SD and the internal clock signal SCL2 are fixed at the low level, and the standby state is established. Become.
[0064]
Although the above description has been made with reference to a 4-bit bus, the same applies to an 8-bit bus and a 12-bit bus. In the above description, the output is divided every 40 outputs. However, the above object can be achieved if the division is an integral multiple of the bus width.
[0065]
【The invention's effect】
According to the above configuration, the standby function is not configured in units of one segment driver but is subdivided internally, so that power consumption is reduced by the subdivision.
[0066]
In addition, since the power consumption of the segment driver for driving the liquid crystal panel is reduced, the power consumption of the liquid crystal display device can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a liquid crystal driving device according to one embodiment of the present invention.
FIG. 2 is a timing chart of the liquid crystal driving device according to one embodiment of the present invention.
FIG. 3 is a block diagram of a conventional liquid crystal driving device.
FIG. 4 is a timing chart of a conventional liquid crystal driving device.
FIG. 5 is a block diagram showing a schematic configuration of a conventional liquid crystal display device.
FIG. 6 is a voltage waveform diagram showing a driving voltage of the liquid crystal display device.
FIG. 7 is a timing chart showing an operation state of a conventional liquid crystal display device.
FIG. 8 is a block diagram of a liquid crystal driving device according to one embodiment of the present invention.
FIG. 9 is a timing chart of a liquid crystal driving device according to one embodiment of the present invention.
FIG. 10 is a circuit diagram of a standby circuit according to one embodiment of the present invention.
FIG. 11 is a timing chart of a standby circuit according to an embodiment of the present invention.
FIG. 12 is a circuit diagram of a standby circuit according to one embodiment of the present invention.
FIG. 13 is a timing chart of a standby circuit according to one embodiment of the present invention.
FIG. 14 is a timing chart of a standby circuit according to an embodiment of the present invention.
[Explanation of symbols]
101: display control device, 102: power supply circuit, 301: shift register circuit, 302: bit latch circuit, 303: line latch circuit, 304: output circuit, LCD: liquid crystal display panel, IC-U1 to IC-Un, IC- L1 to IC-Ln: Segment driver, IC-C1 to IC-C5: Common driver, CL1: Data latch clock, CL1: Line clock, M: Alternating signal, Yn: Output.

Claims (6)

A liquid crystal display element,
A first latch circuit and a second latch circuit for latching display data of the liquid crystal display element;
A first shift register connected to the first latch circuit, a second shift register connected to the second latch circuit,
A first data bus for supplying display data to the first latch circuit;
A first clock signal line for supplying a clock to the first shift register;
A second data bus for supplying display data to the first data bus and the second latch circuit;
A second signal line for supplying a clock to the first clock signal line and the second shift register;
A first standby circuit provided between the first data bus and the second data bus, and between the first clock signal line and the second clock signal line; ,
In a one-line data write period, a clock is supplied to the first shift register via the first clock signal line, and display data is supplied to the first shift register via the first data bus. Then, when a clock is supplied to the second shift register via the second clock signal line and display data is supplied to the second latch circuit via the second data bus, A liquid crystal display device, wherein a first standby circuit sets the first clock signal line and the first data bus to a standby state. A third latch circuit and a fourth latch circuit for latching display data of the liquid crystal display element,
A third shift register connected to the third latch circuit, a fourth shift register connected to the fourth latch circuit,
A fourth data bus for supplying display data to the fourth latch circuit;
A fourth clock signal line for supplying a clock to the fourth shift register;
A third data bus for supplying the data to the fourth data bus and the third latch circuit,
A third signal line for supplying a clock to the fourth clock signal line and the third shift register,
A second standby circuit provided between the third data bus and the fourth data bus, and between the third clock signal line and the fourth clock signal line; ,
In the one-line data writing period, a clock is supplied to the third shift register via the third clock signal line, and display data is supplied to the third shift register via the third data bus. 2. The liquid crystal display device according to claim 1, wherein the second standby circuit puts the fourth clock signal line and the fourth data bus in a standby state. In the one-line data writing period, a clock is supplied to the third shift register via the third clock signal line, and display data is supplied to the third shift register via the third data bus. This is because after the clock is supplied to the second shift register via the second clock signal line and the display data is supplied to the second latch circuit via the second data bus. The liquid crystal display device according to claim 2, wherein: After a clock is supplied to the second shift register via the second clock signal line and display data is supplied to the second latch circuit via the second data bus, the second 4. The liquid crystal display device according to claim 1, wherein the shift register and the second latch circuit are in a standby state. A first data bus for supplying display data to the first latch circuit;
A first clock signal line for supplying a clock to the first shift register;
A second data bus for supplying display data to the first data bus and the second latch circuit;
A second signal line for supplying a clock to the first clock signal line and the second shift register;
A first standby circuit provided between the first data bus and the second data bus, and between the first clock signal line and the second clock signal line; ,
In a one-line data writing period, a clock is supplied to the first shift register via the first clock signal line, and display data is supplied to the first shift register via the first data bus. Then, when a clock is supplied to the second shift register via the second clock signal line and display data is supplied to the second latch circuit via the second data bus, A data signal line driver, wherein the first standby circuit sets the first clock signal line and the first data bus in a standby state. After a clock is supplied to the second shift register via the second clock signal line and display data is supplied to the second latch circuit via the second data bus, the second The data signal line driver according to claim 5, wherein the shift register and the second latch circuit are in a standby state.

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