JPH1115451A - Liquid crystal driving circuit and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of the blackout of a liquid crystal display by performing a synchronization without utilizing a system resetting function at the time of eliminating a synchronous deviation when the synchronous deviation is generated in the circuit. SOLUTION: A slave mode liquid crystal driving circuit outputs gradation level signals L1', L2' from a control circuit 24 of itself to input them to a self- diagnostic circuit 28. Here, they are compared with gradation level signals L1, L2 to be inputted from the control circuit 14 of a master mode liquid crystal driving circuit as to whether L1=L1', L2=L2' or not, and when they are not matched with each other, the circuit 28 judges that a synchronous deviation is generated to invert the logic of a signal REFRHB from the circuit 28 whilst they are noncoincident. The synchronous deviation is dissolved by the inversion of the logic of the signal REFRHB. Then, the synchronous deviation is eliminated by inserting an 'H' pulse during a period when a frame signal FRMB to be inputted from the master liquid crystal driving circuit to the control circuit 24 while the logic of the signal REFRHB is inverted is an 'L'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving circuit, and more particularly, to a liquid crystal driving circuit having a control circuit such as a display RAM, a display RAM address, and a gradation operation circuit, and a control method therefor.

[0002]

2. Description of the Related Art In recent years, PDAs (Personal Digital Assist) have been developed.
(ants portable information terminals), etc., since low power consumption is regarded as important, control circuits such as a display RAM, a display RAM address circuit, and a gradation calculation circuit are built in the column-side liquid crystal drive circuit of the liquid crystal display device. A technique for reducing the power consumption of a device using this liquid crystal display device has been developed. The drive circuit of such a liquid crystal display device combines the output of a liquid crystal drive circuit for gradation display, which is a column side liquid crystal drive circuit, and the output of a line selection liquid crystal drive circuit, which is a row side liquid crystal drive circuit. Is performed.

The column-side liquid crystal drive circuit has two modes, a master mode and a slave mode. In the master mode, an internal oscillator is operated and a synchronization signal is transmitted to the slave mode liquid crystal drive circuit and the row-side liquid crystal drive circuit. Since each column-side liquid crystal drive circuit has a built-in display RAM and control circuit, the control circuit of each slave liquid crystal drive circuit controls the master liquid crystal drive circuit based on the synchronization signal from the master liquid crystal drive circuit. It is configured to synchronize with the circuit. However, if external noise or the like gets on the supply signal line from the master liquid crystal drive circuit and the slave liquid crystal drive circuit erroneously determines this noise as a signal, it will be out of synchronization with the operation of the gradation calculation circuit of the control circuit between the master and the slave. The liquid crystal display display represented by the difference between the column-side liquid crystal drive output value generated by the gradation operation circuit and the row-side liquid crystal drive output value output based on the liquid crystal gradation level signal is used as the master drive. Due to the slave drive circuit out of synchronization with the circuit, the display abnormality of the liquid crystal display panel of the vertical line corresponding to the output continues.

Such a synchronization shift is generated by a master-side control circuit and transmitted to a low-side liquid crystal drive circuit, and a gray-scale level signal generated by each control circuit of a slave liquid crystal drive circuit. In the conventional LCD drive circuit, the self-diagnosis circuit in the slave LCD drive circuit determines the synchronization deviation, and the determined slave LCD drive circuit supplies a system reset signal to all slave LCD drive circuits. In addition, all the liquid crystal drive circuits on the column side are initialized to eliminate the synchronization deviation. However, this initialization causes a problem that the liquid crystal display is momentarily blacked out. Hereinafter, this will be described in detail.

FIG. 12 is a block diagram showing an example of a conventional liquid crystal display device. In a configuration in which three column-side liquid crystal drive circuits IC2 to IC4 are provided in the 480 × 240 size liquid crystal display 1 and one row-side liquid crystal drive circuit IC5 is provided, the The drive circuit 2 is set to the master mode, the other column side liquid crystal drive circuits 3 and 4 are set to the slave mode, and the liquid crystal drive circuit 2 in the master mode connects the external resistor R1 for oscillation and operates the internal oscillator. , The liquid crystal drive timing signal STB, the frame signal FRMB, and the gradation level signals L1 and L2 are supplied to the column-side slave mode liquid crystal drive circuits 3 to 4 and the row-side liquid crystal drive circuit 5, and a self-diagnosis is performed. The circuit output REFRHB is applied to each column side liquid crystal drive circuit 2
4 are connected to each other. The CPU interface signal 7 and the system reset signal 6 are input from outside.

Next, referring to FIG. 13, the configuration and connection relationship between master mode 2 and slave mode 3 in the column-side liquid crystal drive circuit will be described. Both the master mode 2 and the slave mode 3 include oscillators 13 and 23, timing generators 12 and 22, self-diagnosis circuits 18 and 28, control circuits 14 and 24, display RAMs 15 and 25, and output circuits 16 and 26.

In practice, the self-diagnosis circuit 18 is unnecessary in the column-side liquid crystal drive circuit designated for the master mode, and the oscillator 23 and the timing generator 22 are provided in the column-side liquid crystal drive circuit designated for the slave mode. Although unnecessary, the same liquid crystal drive circuit is used, so that these switches are switched by the switches SW1 to SW8. In the master mode 2, when the switches SW1 to SW4 are turned on, the oscillator 13 to which the oscillator external resistor R1 is attached operates, and the timing generator 12 outputs the liquid crystal drive timing signal STB and the frame signal FRMB. The signal is input to its own control circuit 14, the display RAM 15 and the output circuit 16 operate, and the liquid crystal drive output is performed. Also, these signals are in slave mode 3
And to the row-side liquid crystal drive circuit 5 shown in FIG. Also, the control circuit 14 outputs the gradation level signal L
1 and L2 are output, and these signals are supplied to the slave mode 3 and the low-side liquid crystal drive circuit 5.

In the slave mode liquid crystal drive circuit 3, since the switches SW5 to SW8 are turned off and the oscillator 23 and the timing generator 22 are stopped, the signals STB and FRMB to the control circuit 24 and the signals to the self-diagnosis circuit 28 F
The RMB receives these signals from master mode 2,
The display RAM 25 and the output circuit 26 are operated to perform liquid crystal drive output, and the control circuit 24 outputs the gradation level signals L1 and L2, and the signal L to the self-diagnosis circuit 28.
1 'and L2'. As described above, the signals L1 and L2 to the self-diagnosis circuit 28 are input from the control circuit 14 in the master mode 2, and the signals L1 and L2
2 is compared with L1 'and L2', and as a result, a self-diagnosis circuit output REFRHB is generated, and its own AND circuit 2
7 is ANDed with a system reset signal input to one of the terminals,
EFRHB is also supplied to the master mode 2 and other slave modes 4.

Next, the configuration and operation of the self-diagnosis circuit 28 will be described with reference to FIG. When the set signal S is "H" and the self-diagnosis circuit output REFRHB is set to "H", the signals L1 and L1 'and L2 and L2' are matched by XOR1 and XOR2 and NOR1. , The "L" level is input to the data D of the flip-flop FF1, and in that state, the frame signal RR
When MB rises, the output Q of FF1 changes from "H" to "L", and this output is a circuit composed of delay circuit D1, inverter circuit INV1, NOR circuit NOR2, N-type MOS transistor Nch, and pull-up resistor RU. Accordingly, the self-diagnosis circuit output REFRHB is configured to be "L" for the delay time of the delay circuit D1.

Next, with reference to FIG. 15, a description will be given of the operation from the occurrence of a synchronous shift in the conventional liquid crystal drive circuit to the recovery of the shift. First, the operation cycle of the gradation level signals L1 and L2 output in the master mode 2 will be described with reference to FIG.
This will be described with reference to FIG. One cycle is one cycle in which the frame signal FRMB is input with four low pulse signals F1 to F4, and the liquid crystal drive timing signal S
TB has a rising signal input 121 times between an “L” pulse of the frame signal FRMB and the next “L” pulse.

When an "L" pulse is input at the timing of F1 of the first frame signal FRMB, when the first rising signal of the liquid crystal drive timing signal STB, L1 =
“H”, L2 = “H” is output, and the rising signal of the STB signal until the next “L” pulse of F2 is input.
The level of 2 is inverted. Hereinafter, when F2, L1 =
“H”, L2 = “L”, and when F3, L1 = “L”, L2
= “L”, F4, L1 = “L”, L2 = “H”, the level of L2 is inverted at the first rising of STB.

Next, referring to FIG. 15A, a case where noise (N1) is superimposed on the frame signal FRMB will be described. First, the system reset signal RESETB is input,
During the period S1 of one cycle of L1 and L2, the initialization time of the liquid crystal drive circuit is reached, and the Y output is turned off (blackout) to prevent flickering of the display on the liquid crystal display. After S2, the Y output is the display-on output. Then, in the ON output of S2, noise N1
Is one pulse on the frame signal FRMB, a synchronization shift occurs at the rising edge of the next liquid crystal drive timing signal STB3, and the detection timings K1 to K1 of the self-diagnosis circuit 28
1 at K6, the synchronization shift is detected, and the self-diagnosis circuit output RE is output.
FRHB becomes "L" for a predetermined period, and all the column-side liquid crystal driving circuits IC2 to IC4 including itself are reset and initialized by the AND circuit 27 and the like. Therefore, the gradation level signals L1 and L2 are synchronized, but in the next cycle S3, Y
The output turns off and turns on after the next cycle S4.

[0013]

As described above, in the conventional liquid crystal driving circuit, for example, when a noise occurs in a frame signal and a synchronization shift occurs between the master and slave gradation level signals, a self-diagnosis detecting the synchronization shift is performed. Circuit output REFRHB
Is transmitted to all the other column-side liquid crystal driving circuits, and all the column-side liquid crystal driving circuits are reset and initialized to eliminate the synchronization deviation. When all the column-side liquid crystal drive circuits are initialized, the display off output is activated to prevent flickering of the liquid crystal display during the initialization time of the display RAM and control circuit, and the liquid crystal display is reset to the normal system reset. There is a problem that blackout occurs momentarily even though there is no input, which is annoying and may be erroneously determined to be a display failure.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. Synchronous deviation occurs between the master and slave gradation level signals, and the liquid crystal display blacks out while the synchronous deviation is eliminated. It is an object of the present invention to provide a liquid crystal driving circuit having no circuit and a control method thereof.

[0015]

A method of controlling a liquid crystal drive circuit according to the present invention is a column side liquid crystal drive circuit having a control circuit having a built-in gradation level signal generator. A plurality of slave mode liquid crystal driving circuits are formed, and the master mode liquid crystal driving circuit generates a liquid crystal driving timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14. In addition to outputting a liquid crystal drive output, the liquid crystal drive timing signal STB and the frame signal FRMB are sent to the slave mode liquid crystal drive circuit, and the control circuit 14 outputs gradation level signals L1 and L2 to output the slave mode liquid crystal. Sent to the drive circuit, the slave mode liquid crystal drive circuit , The liquid crystal drive timing signal S
The TB and the frame signal FRMB are input to its own control circuit 24 to output a liquid crystal drive output, and the control circuit 24 outputs the gradation level signal L1 ',
L2 'is output and input to the self-diagnosis circuit 28, and the gradation level signals L1, L
2 and whether or not L1 = L1 ′ and L2 = L2 ′. If they do not match, it is determined that a synchronization shift has occurred, and the logic of the signal REFRHB from the self-diagnosis circuit 28 is inverted during the mismatch. In the method of controlling a liquid crystal driving circuit for eliminating a synchronization shift by inverting the logic of the signal REFRHB, a frame input from the master mode liquid crystal driving circuit to the control circuit 24 while the logic of the signal REFRHB is inverted. "L" of signal FRMB
It is characterized in that the "H" pulse is inserted during the period to eliminate the synchronization deviation. Therefore, the synchronization deviation can be eliminated without having to reset the entire system, and the liquid crystal display is not blacked out.

Also, while the logic of the signal REFRHB is inverted, the frame signal FR inputted from the master mode liquid crystal drive circuit to the control circuit 24.
The input of the MB and the liquid crystal drive timing signal STB is stopped to eliminate the synchronization deviation. Therefore, the synchronization deviation can be eliminated without having to reset the entire system, and the liquid crystal display is not blacked out.

Further, the signal REFRHB is input to the timing generators and control circuits of all the column-side liquid crystal driving circuits, and the timing generator and the gradation level signal generator built in the control circuit are reset. In this manner, the synchronization deviation is eliminated. Therefore, the synchronization deviation can be eliminated without having to reset the entire system, and the liquid crystal display is not blacked out.

The liquid crystal driving circuit according to the present invention is a column-side liquid crystal driving circuit having a control circuit having a built-in gradation level signal generator, and includes a master mode liquid crystal driving circuit, a single or plural slave mode liquid crystal driving circuits. The master mode liquid crystal drive circuit generates a liquid crystal drive timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14 to output a liquid crystal drive output. Means for transmitting the liquid crystal drive timing signal STB and the frame signal FRMB to the slave mode liquid crystal drive circuit, outputting gray level signals L1 and L2 from its own control circuit 14 and transmitting the signals to the slave mode liquid crystal drive circuit. And the slave mode liquid crystal drive circuit The drive timing signal STB and the frame signal FRMB are input to the own control circuit 24 to output a liquid crystal drive output, and the control circuit 24 outputs the gradation level signals L1 'and L2' to the self-diagnosis circuit 28. The self-diagnosis circuit 28
And the gray level signals L1 and L2 input to the
A comparison is made as to whether L1 'and L2 = L2'. If they do not match, it is determined that a synchronization shift has occurred, and the logic of the signal REFRHB from the self-diagnosis circuit 28 is inverted during a mismatch. In a liquid crystal drive circuit provided with means for eliminating a synchronization shift by inversion of logic,
The signal REFR is supplied to the slave mode liquid crystal driving circuit.
While the logic of HB is inverted, the "H" pulse is inserted during the "L" period of the frame signal FRMB input from the master mode liquid crystal drive circuit to the control circuit 24 to eliminate the synchronization deviation. The correction circuit is provided. Therefore, the synchronization deviation can be eliminated without having to reset the entire system, and the liquid crystal display is not blacked out.

Further, while the logic of the signal REFRHB is inverted in the slave mode liquid crystal drive circuit, the frame signal FRMB and the liquid crystal drive timing input from the master mode liquid crystal drive circuit to the control circuit 24 are provided. A correction circuit is provided for stopping the input of the signal STB and eliminating the synchronization deviation. Therefore, the synchronization deviation can be eliminated without having to reset the entire system, and the liquid crystal display is not blacked out.

The self-diagnosis circuit 28 has an inverter at the last stage. Therefore, the current consumption can be further reduced.

Further, the signal REFRHB is input to the timing generators and control circuits of all the column side liquid crystal driving circuits, and the timing generator and the gradation level signal generator built in the control circuits are reset. And means for eliminating the synchronization deviation. Therefore, with a simple circuit configuration, the synchronization deviation can be eliminated without resetting the entire system, and the liquid crystal display is not blacked out.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating an example of a device configuration of a liquid crystal display device to which the first embodiment of the present invention is applied. In FIG. 1, 1 is a liquid crystal display, 2 is a column side liquid crystal drive circuit IC (master mode), 3 and 4 are column side liquid crystal drive circuit ICs (slave mode),
5 is a row side liquid crystal drive circuit IC, 6 is a system reset signal, and 7 is a CPU interface signal.

The 480 × 240 size liquid crystal display 1 is provided with three column side liquid crystal driving circuits IC2 to IC4,
In the configuration in which one row-side liquid crystal drive circuit IC5 is provided, of the column-side liquid crystal drive circuits 2 to 4, the liquid crystal drive circuit 2 is in the master mode and the other column-side liquid crystal drive circuits 3 to 4
Is set to the slave mode, the liquid crystal drive circuit 2 in the master mode connects the external resistor R1 for oscillation, operates the internal oscillator, and operates the liquid crystal drive timing signal STB, the frame signal FRMB, and the gradation level signals L1 and L2. Is supplied to the column-side slave mode liquid crystal drive circuits 3 to 4 and the row-side liquid crystal drive circuit 5, and the CPU interface signal 7 and the system reset signal 6 are externally input. .

Next, referring to FIG. 2, the configuration and connection relationship between the master mode 2 and the slave mode 3 in the column-side liquid crystal drive circuit will be described. In both the master mode 2 and the slave mode 3, the oscillators 13 and 23, the timing generators 12 and 22, the self-diagnosis circuits 18 and 28, the control circuits 14 and 24, the display rams 15 and 25, the pulse correction circuits 19 and 29, and the OR circuit or11. , Or12.

Actually, the self-diagnosis circuit 18, the pulse correction circuit 19, and the OR circuit or11 are unnecessary in the column-side liquid crystal driving circuit designated in the master mode, and in the column-side liquid crystal driving circuit designated in the slave mode. , The oscillator 23 and the timing generator 22 are unnecessary, but since the same liquid crystal driving circuit is used, the switches SW1 to SW
These are switched by W8 or the like. In the master mode 2, when the switches SW1 to SW4 are turned on, the oscillator 13 to which the oscillator external resistor R1 is attached operates, and the timing generator 12 outputs the liquid crystal drive timing signal STB and the frame signal FRMB. The signal is input to its own control circuit 14 and the display RAM 1
5 and the output circuit 16 operate, and liquid crystal drive output is performed. These signals are also supplied to the slave mode 3 and the row-side liquid crystal drive circuit 5 shown in FIG. Further, the control circuit 14 outputs gradation level signals L1 and L2, and these signals are supplied to the slave modes 3 and 4 and the row-side liquid crystal drive circuit 5.

In the slave mode liquid crystal driving circuit 3, since the switches SW5 to SW8 are turned off and the oscillator 23 and the timing generator 22 are stopped, the STB and FRMB signals to the control circuit 24 are transmitted from the master mode 2 to the STB and FRMB signals. A signal is input, the display RAM 25 and the output circuit 26 are operated to perform liquid crystal driving output.
The RMB is branched into three, one of which is input to one input terminal of the pulse correction circuit 29, and the other is input to one input terminal of the OR circuit or21.
The output of the pulse correction circuit 29 input to the other input terminal of r21 is ORed and input to the control circuit 24, and the other one is input to the self-diagnosis circuit 28. Further, the control circuit 24 outputs the gradation level signals L1 and L2,
8 are input as signals L1 'and L2'. As described above, the signals L1 and L2 are input from the control circuit 14 in the master mode 2 to the self-diagnosis circuit 28, and the signals L1 and L2 are compared with L1 'and L2'. An output REFRHB is generated and input to one terminal of the pulse correction circuit 29.

Next, the configuration and operation of the self-diagnosis circuit 28 of the present embodiment will be described with reference to FIG. When the set signal S is "H", "H" is set in the self-diagnosis circuit output REFRHB, and the signals L1 and L1 'and L2 and L
2 ′ is performed by XOR1 and XOR2 and NOR1. If any one of them does not match, an “L” level is input to the data D of the flip-flop FF1, and when the frame signal FRMB rises in that state, the output Q of the FF1 is output. Changes from “H” to “L”, and its signal is changed to a delay circuit D1, an inverter circuit INV1, a NOR circuit NOR2, and an inverter circuit I.
The self-diagnosis circuit output RE
FRHB is configured to be “L” for the delay time of the delay circuit D1. That is, instead of the Nch transistor of the conventional self-diagnosis circuit shown in FIG.
NV2 is used. This is because it is not necessary to initialize all the column side liquid crystal driving circuits as described later.

Next, the configuration and operation of the pulse correction circuit 29 of this embodiment will be described with reference to FIG. Initialized by the reset signal RB, the correction circuit output FRPW is “L”
Is set, and when the frame signal FRMB rises, FIG.
The self-diagnosis circuit output REFRHB is input, and the Q output of the FF 10 becomes “L” at the falling of the next frame signal FRMB.
To "H", the delay circuits D20 and D3
0, inverter circuit INV10, AND circuit AND10
Accordingly, after the delay time Dy1 of the delay circuit D20, the “H” pulse signal (PW1) for the delay time of the delay circuit D30
Is output from the correction output FRPW.

Next, with reference to FIG. 5, a description will be given of the operation from the occurrence of a synchronization shift in the liquid crystal drive circuit of this embodiment to the recovery of the shift. First, regarding the operation cycle of the gradation level signals L1 and L2 output in the master mode 2,
This will be described with reference to FIG. In one cycle, the frame signal FRMB is one cycle when four low pulse signals F1 to F4 are input, and the liquid crystal drive timing signal STB includes the “L” pulse of the frame signal FRMB and the next “L” pulse. During this time, 121 rising signals are input.

When an "L" pulse is input at the timing of F1 of the first frame signal FRMB, the first rising signal of the liquid crystal drive timing signal STB is set to L1 =
“H”, L2 = “H” is output, and the rising signal of the STB signal until the next “L” pulse of F2 is input.
The level of 2 is inverted. Hereinafter, when F2, L1 =
“H”, L2 = “L”, and when F3, L1 = “L”, L2
= "L", F4, L1 = "L", L2 = "H", the level of L2 is inverted at the first rising of STB.

Next, in FIG. 5A, the frame signal F
The case where the noise (N1) is on the RMB will be described. First, the system reset signal RESETB is input,
During one cycle S1 of L1 and L2, the initialization time of the liquid crystal drive circuit is reached. In order to prevent flickering of the liquid crystal display display, the Y output is turned off (blackout). After S2, the Y output is turned on. When one pulse of the noise N1 is included in the frame signal FRMB in the ON output of S2, a synchronization shift occurs at the next rise of 3 of the liquid crystal drive timing signal STB,
K6 of detection timings K1 to K10 of the self-diagnosis circuit 28
L1ＬL1 ′, and the output RE of the self-diagnosis circuit 28
An "L" pulse signal is generated in FRHB and input to one of its own pulse correction circuits 29.
As shown in (PW1) of FIG. 4B, at the falling edge of the frame signal FRMB input to the other one, the "H" pulse signal corresponding to the delay time of the delay circuit D30 is output to the pulse correction circuit output FRPW. This "H" pulse is input to the OR circuit or21 with the frame signal FRMB, and the "H" pulse is added to the frame signal FRMB input to the control circuit 24 which is the output of the OR circuit or21.
In addition, the state of the cycle of the gradation level signal of the control circuit 24 of its own advances by +1 from the state of the cycle of the gradation level signal of the master mode 2, and the signals L1 ′ and L2 ′.
Are "L" and "L", but the synchronization is still out of synchronization with L1 @ L1 'and L2 @ L2' at the next K7 timing, so that the pulse correction circuit is activated at the falling edge of F4 of the frame signal FRMB. 29, an “H” pulse is added again by +1 (PW
2) In this way, the “H” pulse is added by +1 from the pulse correction circuit 29 (PW3) until synchronization is achieved at the timing of K9, and synchronization is performed. Therefore, without resetting any of the column-side liquid crystal drive circuits 2 to 4, the synchronization deviation can be eliminated, and the Y output remains a display-on output even before synchronization, so that blackout can be avoided. Has become.

Next, a second embodiment of the present invention will be described with reference to the drawings. The liquid crystal display device to which the liquid crystal drive circuit according to the second embodiment is applied is the same as the liquid crystal display device shown in FIG. 1, and a description thereof will be omitted. FIG. 6 shows this second
Mode 2 and slave mode 3 in the embodiment of FIG.
FIG. 8 is a diagram showing the configuration and connection relationship between the pulse correction circuit 29 and the OR circuit or2, as will be described later with reference to FIG.
1 and or22, the liquid crystal drive timing signal STB and the frame signal FRM input from the master mode 2
The configuration is the same as that of the first embodiment shown in FIG. 2 except that B is ORed with the output MASK of the pulse correction circuit 29 and input to the control circuit 24. In addition, the configuration and operation of the self-diagnosis circuit 28 are the same as those of the first embodiment shown in FIG. 3, and a description thereof will be omitted.

Next, the configuration and operation of the pulse correction circuit according to this embodiment will be described with reference to FIG. Initialized by the reset signal RB, the pulse correction circuit output MASK is in the “L” state, and the self-diagnosis circuit output REFRH
At "L" of B, the pulse correction circuit output MASK becomes "H", and at the next rising edge of the frame signal FRMB, the pulse correction circuit output MASK changes from "H" to "L".

Next, with reference to FIG. 8, a description will be given of the operation from the occurrence of a synchronization shift in the liquid crystal drive circuit of the second embodiment to the recovery of the shift. Note that the gradation level signals L1 and L output in the master mode 2 shown in FIG.
The operation cycle 2 is the same as that of the first embodiment shown in FIG. Next, in FIG. 8A, noise (N
The case in which 1) is riding will be described. First, a system reset signal RESETB is input, and during one cycle S1 of L1 and L2, the initialization time of the liquid crystal driving circuit is set. In order to prevent flickering of the liquid crystal display display, Y is set.
The output is off (blackout), and the Y output is on from the next cycle S2. If one pulse of the noise N1 is included in the frame signal FRMB in the ON output of S2, a synchronization shift occurs at the rise of the next liquid crystal drive timing signal STB3, and the detection timings K1 to K10 of the self-diagnosis circuit 28 are generated. L1 ≠ L1 ′ at K6, an “L” pulse signal is generated at the output REFRHB of the self-diagnosis circuit 28, and is input to one of its own pulse correction circuits 29. The output MSAK of the pulse correction circuit 29 is set to “H”. And the respective OR circuits or21 and or22
Becomes “H”, and the liquid crystal drive timing signal STB and the frame signal FRMB input from the master mode 2 are output.
Is not input to the control circuit 24.
Thereafter, synchronization is established at the timing of K7, and the self-diagnosis circuit 28
Is high, the output MSAK of the pulse correction circuit 29 is low, and the control circuit 24 receives the liquid crystal drive timing signal S from the master mode.
The clock of TB and the frame signal FRMB is input, and the operation returns to the normal operation. Therefore, the synchronization deviation can be eliminated without resetting any of the column side liquid crystal driving circuits 2 to 4, so that the Y output is a display-on output even before the synchronization, and blackout can be avoided. Become.

Next, a third embodiment of the present invention will be described with reference to the drawings. The liquid crystal display device to which the third embodiment is applied is the same as that of FIG. 12 described as the related art, and the description is omitted. FIG. 9 is a diagram showing a configuration and a connection relationship between the master mode 2 and the slave mode 3 in the third embodiment. The configuration is such that the output of the self-diagnosis circuit REFRHB and the system reset signal are not passed through the AND circuit. The configuration is the same as that of the prior art shown in FIG. 13 except that the input to the control circuit 24 and the output REFRHB of the self-diagnosis circuit are input to the respective timing generators 12.

FIG. 10 shows a gradation level signal generator 3 built in the control circuit 24 of the third embodiment.
FIG. 2 is a diagram illustrating a connection relationship of FIG. Gray level signal generator 3
Reference numeral 1 denotes a circuit for generating a cycle of the operation of L1 and L2 in FIG. 11B, which is initialized by the AND logic of the system reset signal and the output REFRHB of the self-diagnosis circuit, and the next rise of the liquid crystal drive timing signal STB. And the signal L1 =
“H”, L2 = “H” state (F in FIG. 11B)
1).

Next, the case where noise (N1) is superimposed on the frame signal FRMB will be described with reference to FIG. First, the system reset signal RESETB is input,
During one cycle S1 of L1 and L2, the initialization time of the liquid crystal drive circuit is reached. In order to prevent flickering of the liquid crystal display display, the Y output is turned off (blackout). After S2, the Y output is turned on. When one pulse of the noise N1 is included in the frame signal FRMB in the ON output of S2, a synchronization shift occurs at the next rise of 3 of the liquid crystal drive timing signal STB,
K6 of the detection timings K1 to K11 of the self-diagnosis circuit 28
L1ＬL1 ′, and the output RE of the self-diagnosis circuit 28
An "L" pulse signal is generated in FRHB, and the self-diagnosis output REFRHB is input to its own control circuit 24 and timing generator 22, and is also input to all other column-side liquid crystal driving circuits to generate respective timings. The gradation level signal generator 31 built in the control circuit and the control circuit is reset, but the "H" of the system reset signal is continuously maintained to the other control circuits of each control circuit. The display operation of the column-side liquid crystal drive circuits 2 to 4 can be canceled without resetting, and the Y output remains a display-on output even before synchronization, so that blackout can be avoided. Become.

[0038]

The liquid crystal driving circuit and the control method thereof according to the present invention have the following effects by being configured and operated as described above. When a synchronization shift occurs and the synchronization shift is eliminated, synchronization is performed without using the system reset function, so that blackout of the liquid crystal display display can be eliminated. In the first embodiment and the second embodiment, the configuration is such that the synchronization is performed by the liquid crystal drive circuit itself in which the synchronization shift has occurred. Therefore, it is not necessary to initialize all the column liquid crystal drive circuits IC. Self-diagnosis circuit output REFR that connects between liquid crystal drive circuit ICs
The HB line can be omitted, and the liquid crystal display device can be simplified. Further, since the Nch open drain of the REFRHB terminal for initializing all the column liquid crystal driving circuits IC is not required, the current consumption can be further reduced (for example, when the VGA size is eight, the through current MAX5 mA during the reset time).
Can be reduced).

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a device configuration of a liquid crystal display device to which a first embodiment of the present invention is applied.

FIG. 2 is a diagram for explaining a first embodiment of the present invention.

FIG. 3 is a diagram for explaining the configuration and operation of a self-diagnosis circuit 28 of the present embodiment.

FIG. 4 is a pulse correction circuit 2 according to the first embodiment shown in FIG. 2;
9 is a diagram for describing the configuration and operation of No. 9; FIG.

FIG. 5 is a diagram for explaining a synchronization shift elimination operation in the first embodiment.

FIG. 6 is a diagram for explaining a second embodiment of the present invention.

7 is a pulse correction circuit 2 according to the second embodiment shown in FIG.
9 is a diagram for describing the configuration and operation of No. 9; FIG.

FIG. 8 is a diagram for explaining a synchronization shift elimination operation in the second embodiment.

FIG. 9 is a diagram for explaining a third embodiment of the present invention.

FIG. 10 is a diagram showing a connection relation of a gray level signal generator according to a third embodiment.

FIG. 11 is a diagram for explaining a synchronization shift elimination operation in the third embodiment.

FIG. 12 is a diagram illustrating an example of a liquid crystal display device to which a conventional liquid crystal driving circuit is applied.

FIG. 13 is a diagram for explaining a conventional liquid crystal drive circuit.

FIG. 14 is a diagram for explaining the configuration and operation of a self-diagnosis circuit 28 of a conventional liquid crystal drive circuit.

FIG. 15 is a diagram for explaining a synchronization shift elimination operation in a conventional liquid crystal drive circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Liquid crystal display 2 Column side liquid crystal drive circuit IC (master mode) 3-4 Column side liquid crystal drive circuit IC (slave mode) 5 Row side liquid crystal drive circuit IC 6 System reset signal 7 CPU interface signal 12,22 Timing generator 13, 23 Oscillator 14, 24 Control Circuit 15, 25 Display Ram 17, 27, AND10, AND20, AND30, A
ND40 AND circuit 18, 28 Self-diagnosis circuit 19, 29 Pulse correction circuit 31 Tone level signal generator or11, or12, or21, or22 OR circuit XOR1, XOR2 XOR circuit NOR1, NOR2 NOR circuit FF1, FF10, FF11, flip-flop INV1 , INV2, INV10 Inverter circuit D1, D10, D11, D20, D30 Delay circuit Nch N-type MOS transistor DOOFB 'Display output STB Liquid crystal drive timing signal FRMB Frame signal L1, L2 Master mode gradation level signal L1', L2 'Slave Mode gradation level signal REFRHB Self-diagnosis circuit output RESETB System reset signal FRPW, MASK Pulse correction circuit output N1 Noise S1-4 Operation cycle of L1, L2 K1 11 self detection timing PW1~3 pulse correction circuit output Y output liquid crystal drive output

Claims (7)

[Claims] 1. A master mode liquid crystal drive circuit and one or more slave mode liquid crystal drive circuits each comprising a column side liquid crystal drive circuit having a control circuit having a built-in gradation level signal generator. The liquid crystal drive circuit generates a liquid crystal drive timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14 to output a liquid crystal drive output.
TB and the frame signal FRMB are sent to the slave mode liquid crystal driving circuit, and the control circuit 14 outputs the gradation level signals L1 and L2 and sends them to the slave mode liquid crystal driving circuit. The liquid crystal drive timing signal STB and the frame signal FRMB are input to its own control circuit 24 to output a liquid crystal drive output, and its own control circuit 2
4 outputs the gradation level signals L1 'and L2' to the self-diagnosis circuit 28. The gradation level signals L1 and L2 input to the self-diagnosis circuit 28 and L1 = L1 'and L1
2 = L2 ′, and if they do not match, the self-diagnosis circuit 28 determines that a synchronization shift has occurred.
, The logic of the signal REFRHB is inverted during a mismatch, and the synchronization of the signal REFRHB is eliminated by reversing the logic of the signal REFRHB. From the drive circuit to the control circuit 24
A "H" pulse is inserted during an "L" period of a frame signal FRMB input to the LCD device to eliminate a synchronization shift. 2. A master mode liquid crystal drive circuit and one or a plurality of slave mode liquid crystal drive circuits each comprising a column side liquid crystal drive circuit having a control circuit having a built-in gradation level signal generator. The liquid crystal drive circuit generates a liquid crystal drive timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14 to output a liquid crystal drive output.
TB and the frame signal FRMB are sent to the slave mode liquid crystal driving circuit, and the control circuit 14 outputs the gradation level signals L1 and L2 and sends them to the slave mode liquid crystal driving circuit. The liquid crystal drive timing signal STB and the frame signal FRMB are input to its own control circuit 24 to output a liquid crystal drive output, and its own control circuit 2
4 outputs the gradation level signals L1 'and L2' to the self-diagnosis circuit 28. The gradation level signals L1 and L2 input to the self-diagnosis circuit 28 and L1 = L1 'and L1
It is determined whether or not 2 = L2 ′. If they do not match, it is determined that a synchronization shift has occurred. During the mismatch, the logic of the signal REFRHB from the self-diagnosis circuit 28 is inverted, and the logic of the signal REFRHB is inverted. In the control method of the liquid crystal drive circuit for eliminating the synchronization shift by the control mode, the master mode liquid crystal drive circuit transmits the control circuit 24 while the logic of the signal REFRHB is inverted.
Wherein the input of the frame signal FRMB and the liquid crystal drive timing signal STB input to the liquid crystal display is stopped to eliminate the synchronization deviation. 3. A master mode liquid crystal drive circuit and one or a plurality of slave mode liquid crystal drive circuits each comprising a column side liquid crystal drive circuit having a control circuit having a built-in gradation level signal generator. The liquid crystal drive circuit generates a liquid crystal drive timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14 to output a liquid crystal drive output.
TB and the frame signal FRMB are sent to the slave mode liquid crystal driving circuit, and the control circuit 14 outputs the gradation level signals L1 and L2 and sends them to the slave mode liquid crystal driving circuit. The liquid crystal drive timing signal STB and the frame signal FRMB are input to its own control circuit 24 to output a liquid crystal drive output, and its own control circuit 2
4 outputs the gradation level signals L1 'and L2' to the self-diagnosis circuit 28. The gradation level signals L1 and L2 input to the self-diagnosis circuit 28 and L1 = L1 'and L1
It is determined whether or not 2 = L2 ′. If they do not match, it is determined that a synchronization shift has occurred. During the mismatch, the logic of the signal REFRHB from the self-diagnosis circuit 28 is inverted, and the logic of the signal REFRHB is inverted. A method of controlling a liquid crystal drive circuit that eliminates synchronization deviation by inputting the signal REFRHB to the timing generators and control circuits of all the column-side liquid crystal drive circuits,
A method of controlling a liquid crystal driving circuit, wherein a synchronization deviation is eliminated by resetting the timing generator and the gradation level signal generator built in the control circuit. 4. A master mode liquid crystal drive circuit and one or a plurality of slave mode liquid crystal drive circuits each comprising a column side liquid crystal drive circuit including a control circuit having a built-in gradation level signal generator, The liquid crystal drive circuit generates a liquid crystal drive timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14 to output a liquid crystal drive output.
Means for sending a TB and a frame signal FRMB to the slave mode liquid crystal drive circuit, outputting gray level signals L1 and L2 from its own control circuit 14 and sending the signals to the slave mode liquid crystal drive circuit, The drive circuit inputs the liquid crystal drive timing signal STB and the frame signal FRMB to its own control circuit 24, outputs a liquid crystal drive output, and controls its own control circuit 2.
4 outputs the gradation level signals L1 'and L2' to the self-diagnosis circuit 28. The gradation level signals L1 and L2 input to the self-diagnosis circuit 28 and L1 = L1 'and L1
2 = L2 ′, and if they do not match, the self-diagnosis circuit 28 determines that a synchronization shift has occurred.
, The logic of the signal REFRHB is inverted during the mismatch, and the logic of the signal REFRHB is inverted in the slave mode liquid crystal drive circuit. While the master mode liquid crystal drive circuit is
A liquid crystal drive circuit comprising: a correction circuit that inserts an “H” pulse during an “L” period of a frame signal FRMB input to the LCD to eliminate a synchronization deviation. 5. A master mode liquid crystal drive circuit and one or a plurality of slave mode liquid crystal drive circuits each comprising a column side liquid crystal drive circuit having a control circuit having a built-in gradation level signal generator. The liquid crystal drive circuit generates a liquid crystal drive timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14 to output a liquid crystal drive output.
Means for sending a TB and a frame signal FRMB to the slave mode liquid crystal drive circuit, outputting gray level signals L1 and L2 from its own control circuit 14 and sending the signals to the slave mode liquid crystal drive circuit, The drive circuit inputs the liquid crystal drive timing signal STB and the frame signal FRMB to its own control circuit 24, outputs a liquid crystal drive output, and controls its own control circuit 2.
4 outputs the gradation level signals L1 'and L2' to the self-diagnosis circuit 28. The gradation level signals L1 and L2 input to the self-diagnosis circuit 28 and L1 = L1 'and L1
2 = L2 ′, and if they do not match, the self-diagnosis circuit 28 determines that a synchronization shift has occurred.
, The logic of the signal REFRHB is inverted during the mismatch, and the logic of the signal REFRHB is inverted in the slave mode liquid crystal drive circuit. While the master mode liquid crystal drive circuit is
A liquid crystal drive circuit comprising: a correction circuit for stopping input of the frame signal FRMB and the liquid crystal drive timing signal STB to be inputted to the liquid crystal display to eliminate a synchronization deviation. 6. The liquid crystal drive circuit according to claim 4, wherein the self-diagnosis circuit includes an inverter at the last stage. 7. A master mode liquid crystal drive circuit and one or a plurality of slave mode liquid crystal drive circuits each comprising a column side liquid crystal drive circuit having a control circuit having a built-in gradation level signal generator, The liquid crystal drive circuit generates a liquid crystal drive timing signal STB and a frame signal FRMB by an oscillator 13 and a timing generator 12 and inputs them to its own control circuit 14 to output a liquid crystal drive output.
Means for sending a TB and a frame signal FRMB to the slave mode liquid crystal drive circuit, outputting gray level signals L1 and L2 from its own control circuit 14 and sending the signals to the slave mode liquid crystal drive circuit, The drive circuit inputs the liquid crystal drive timing signal STB and the frame signal FRMB to its own control circuit 24, outputs a liquid crystal drive output, and controls its own control circuit 2.
4 outputs the gradation level signals L1 'and L2' to the self-diagnosis circuit 28. The gradation level signals L1 and L2 input to the self-diagnosis circuit 28 and L1 = L1 'and L1
2 = L2 ′, and if they do not match, the self-diagnosis circuit 28 determines that a synchronization shift has occurred.
And a means for inverting the logic of the signal REFRHB from the controller during the mismatch and eliminating the synchronization deviation by inverting the logic of the signal REFRHB. Input to the instrument and control circuit,
A liquid crystal drive circuit comprising: means for resetting the timing level generator and the gradation level signal generator incorporated in the control circuit to eliminate a synchronization deviation.