JP2006039517A - Organic el drive circuit and organic el display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an organic EL drive circuit and an organic EL display device which reduce luminance unevenness on a screen in a low tone region between driver ICs driven by currents in a current tone system. <P>SOLUTION: The organic EL drive circuit includes; a reset voltage generation circuit for generating a predetermined constant voltage for constant voltage resetting; reset switches which are provided between an output terminal of the reset voltage generation circuit and terminal pins and are turned on/off in response to reception of by one of a timing control signal, a reset control signal similar to the timing control signal, a reset pulse, other pulses generated in a reset period synchronously with these signals or pulse; and an output terminal for outputting the predetermined constant voltage to other ICs which have identical circuit constructions to that of the organic EL drive circuit and are arranged adjacently to the organic EL drive circuit, as a voltage for constant voltage resetting. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an organic EL driving circuit and an organic EL display device, and more particularly, in a column driver IC (including a data line driver) IC that drives current by a current gradation method, a screen in a low gradation region between the driver ICs. The present invention relates to an organic EL driving circuit and an organic EL display device that can reduce uneven luminance.

A drive circuit for a passive matrix type organic EL element in which an organic EL element arranged in a matrix is driven by current and the anode and cathode of the organic EL element are reset to ground is already known (Patent Document 1). .
On the other hand, in a liquid crystal display device, a drive circuit is known in which a D / A for converting a digital signal into an analog signal is provided and a data line is driven by this D / A. When this is applied to a pixel circuit in an active matrix type organic EL display panel and it is attempted to be incorporated in the display panel, there is a problem that it is difficult to reduce the size of the display panel. This point has already been described in a known patent publication. (Patent Document 2).
Japanese Patent Application Laid-Open No. 9-232074 JP 2000-276108 A

  However, if an organic EL driving circuit for driving the active matrix organic EL display panel is provided as an external circuit of the display panel, the organic EL display panel can be reduced in size accordingly. In this case, the drive current value is normally written by charging a capacitor of a pixel circuit of several hundred pF with a current of about 0.1 μA to 10 μA. However, when the display luminance of the active matrix organic EL display panel is controlled in gradation, a highly accurate current value is required such that the minimum current of the drive current is about 1 nA to 30 nA. There are two types of current directions, a sink type and a source type, and the power supply voltage + Vcc is about 10V to 20V at present in both the active matrix type organic EL display panel and the passive matrix type organic EL panel.

By the way, luminance unevenness in a low gradation region tends to be conspicuous in relation to human visual sensitivity. In the low gradation region, the drive current value becomes small, and when driving a capacitive load such as a capacitor or an organic EL element, a part of the current is consumed by initial charging that does not contribute to light emission. The light emission according to the difference is not sufficiently obtained. Therefore, brightness unevenness is likely to occur. Therefore, a method has been proposed in which the low gradation region is not voltage driven but voltage driven.
However, when a voltage driving circuit is provided in a current gray scale driving circuit, there is a problem that the circuit scale of the driving circuit increases accordingly. In addition, in the current sink type, the voltage for resetting the capacitor of the pixel circuit becomes a high voltage value close to the power supply voltage + Vcc, so that the reset voltage is likely to vary among the driver ICs. Luminance unevenness with conspicuous luminance difference at the boundary between driver ICs is likely to occur.
An object of the present invention is to solve such a problem of the prior art, and can reduce luminance unevenness on a screen in a low gradation region between driver ICs that are driven by a current gradation method. An organic EL driving circuit and an organic EL display device are provided.

In order to achieve such an object, the organic EL drive circuit or the organic EL display device of the present invention has a display period corresponding to a horizontal one-line scanning period and a reset period corresponding to a horizontal scanning blanking period. In an organic EL driving circuit formed as an IC that constant-voltage resets an organic EL element or a capacitor of a pixel circuit via a terminal pin of an organic EL panel during a reset period in a timing control signal of a predetermined frequency to be separated,
A reset voltage generation circuit for generating a predetermined constant voltage for resetting a constant voltage, the timing control signal provided between the output of the reset voltage generation circuit and the terminal pin, and a reset control signal similar to the timing control signal A reset switch that is turned on / off in response to any one of a reset pulse and these signals or other pulses generated in the reset period in synchronization with the pulse, and a circuit similar to the organic EL drive circuit. And an output terminal that outputs the predetermined constant voltage as a voltage for resetting to another IC adjacent to the IC.

In the present invention, since a reset voltage generation circuit is provided, a predetermined constant voltage for resetting a constant voltage can be transmitted from one driver IC to a driver IC adjacent thereto via an output terminal to another IC. The reset voltages among the plurality of driver ICs can be made substantially equal.
As a result, there is almost no difference in the reset voltage at the boundary position between adjacent ICs. Therefore, even if the adjacent terminal pins are driven from different driver ICs, the driver ICs at the low gradation region where the drive current is small It is possible to reduce unevenness in light emission luminance due to a difference in driving current.
As a result, even if the low gradation region is not driven by voltage, the luminance unevenness on the screen of the low gradation region between the driver ICs can be reduced even by the current gradation method.

In FIG. 1, reference numeral 10 denotes an active matrix type organic EL display device, and reference numerals 11, 12, and 13 denote driver ICs having an organic EL drive circuit.
The driver ICs 11 to 13 have organic EL drive circuits having the same circuit configuration, and are arranged adjacent to each other, and these three driver ICs are used for terminal pins in the column direction of the organic EL panel 9 for one horizontal line. Each is responsible for driving. Each of these three driver ICs is provided with a constant voltage reset circuit.
The constant voltage reset circuit includes a reset voltage generation circuit 1, an analog switch 2, a reset switch SW, and a precharge pulse PR output from the control circuit 8.

The central driver IC 11 is a master driver, and the driver ICs 12 and 13 on both sides thereof are slave drivers. The slave driver ICs 12 and 13 are supplied with a reset voltage for resetting the capacitor of the pixel circuit from the master driver IC 11, and the constant voltage is applied to the capacitor of the pixel circuit connected to the terminal pin that the slave driver ICs 12 and 13 are responsible for. Reset.
On the other hand, in the embodiment of FIG. 3 to be described later, the master driver IC 11 (hereinafter referred to as the driver IC 11) sends a constant voltage lower than the reset voltage to the slave driver ICs 12 and 13 (hereinafter referred to as the driver ICs 12 and 13). Each driver IC is generated from a constant voltage lower than the reset voltage.

In FIG. 1, driver ICs 11 to 13 include a reset voltage generation circuit 1, an analog switch 2, a reset voltage output line 3, a current source 4 provided for each terminal pin of the organic EL panel 9, and an output stage current source. And a D / A conversion circuit (D / A) 5.
Each D / A 5 receives a reference current Iref distributed by a reference current distribution circuit (only the current source 4 is shown) from the current source 4 and outputs a drive current i that sinks corresponding to each terminal pin.
The reference current distribution circuit receives the reference current Iref generated by a reference current generation circuit (not shown) and distributes the reference current Iref to each D / A 5. The current source 4 corresponds to an output circuit that outputs the reference current Iref distributed by the reference current distribution circuit to the corresponding D / A 5.

Each D / A 5 is a current switching type D / A composed of a current mirror circuit, and receives the reference current Iref and the display data DAT via the display data register 6 to display the reference current Iref as a display data value. Amplification is performed to generate a drive current (sink current) i corresponding to the display brightness at that time.
The output current of each D / A 5 is sent to the pixel circuit 9a of the active matrix type organic EL panel 9 via the respective drive terminals on the column (data line) side output terminals P1,... Pi,. Sent out. Thereby, the capacitors C built in each pixel circuit 9a are charged respectively. As a result, the organic EL element 9b of each pixel circuit 9a is driven by the drive current i corresponding to the charging voltage of the capacitor C.
In addition, 7 is MPU7 and 8 is a control circuit. The display data DAT in the display data register 6 is set by the MPU 7. Xa... Xi... Xn, X2a... X2i... X2n, X3a... X3i. Column terminal).
By the way, in the color display by the R, G, and B display colors, the current source 4 and the D / A 5 are provided corresponding to the terminal pins corresponding to R, G, and B, respectively. Below, since it is not directly related to invention, it demonstrates without distinguishing R, G, and B, respectively.

Reference numerals 11a and 11b denote I / O terminals (input / output terminals) of the driver IC 11, respectively. These I / O terminals 11a and 11b are provided on both sides on the corresponding side of one driver IC 11 so as to correspond to one side of the adjacent driver ICs 12 and 13, respectively.
Corresponding to these I / O terminals 11a and 11b, the driver IC 12 is provided with I / O terminals 12a and 12b, and the driver IC 13 is provided with I / O terminals 13a and 13b. These I / O terminals 11a to 13a and 11b to 13b are substantially in the sides adjacent to each other when the ICs of the terminal pins of the driver ICs arranged on the sides of the rectangular IC are arranged adjacent to each other. Each I / O terminal at a corresponding position is selected.
The I / O terminals 11a to 13a and 11b to 13b are connected to each other by the reset voltage output line 3 inside the driver ICs 11 to 13, respectively.
Further, the I / O terminal 11b of the driver IC 11 and the I / O terminal 12a of the driver IC 12 provided adjacent to each other are connected by an external wiring line 14, and the I / O of the driver IC 12 provided adjacent to each other is connected. The terminal 12 b and the I / O terminal 13 a of the driver IC 13 are also connected by an external wiring line 15.
The output terminals of the reset voltage generation circuit 1 of each of the driver ICs 11 to 13 are respectively connected to the reset voltage output line 3 via the analog switch 2. In addition, each reset switch SW (analog switch) provided corresponding to each output terminal P1,... Pi,... Pn has one end connected to each output terminal P1,. Are commonly connected to the reset voltage output line 3.

The reset voltage generation circuit 1 includes an operational amplifier (OP) 1a, a D / A conversion circuit (D / A) 1b, and a data register 1c.
OP1a is a non-inverting amplifier that operates by receiving power supply from the power supply line + Vcc, receives the output voltage of D / A1b at the (+) input, amplifies it with a predetermined amplification factor, and resets the constant voltage. Is output to the reset voltage output line 3. The output is generated at a connection point substantially at the center of the reset voltage output line 3 (see FIG. 1). The (−) input of OP1a is connected to the power supply line + Vcc through a reference resistor. The voltage of the power supply line + Vcc is about 5 V to 20 V, and the reset voltage VRS at this time is a voltage that is slightly or several V lower than the voltage of the power supply line + Vcc.
D / A 1b is a ladder-type D / A conversion circuit based on resistance division. The D / A 1b receives data set in the data register 1c from the MPU 7 and D / A converts it to generate a reset voltage VRS. Therefore, the reset voltage VRS can be adjusted in a programmable manner according to the data set in the data register 1c.
The MPU 7 sets data for generating a reset voltage in the data register 1c when the power is turned on. This data is stored in a nonvolatile memory inside the MPU 7.

Each reset switch SW of each of the driver ICs 11 to 13 receives a precharge pulse PR (see FIG. 2C) supplied to each driver IC via the input terminal 11c, the input terminal 12c, and the input terminal 13c. Each is turned ON during a period of H ″ (precharge period). As shown in FIG. 2C, OP1a of the driver IC 11 is held in a steady operation state to generate the reset voltage VRS during a period when the precharge pulse PR is “H” (precharge period). . The OP1a of the driver IC 11 is held in an idling state during a period (precharge period) in which the precharge pulse PR is “L”.
Further, the precharge pulse PR is applied to the input terminal 11d of the driver IC 11 as a master, and the analog switch 2 is turned ON during a period (precharge period) in which the precharge pulse PR is “H”. The precharge pulse PR is not applied to the input terminals 12d and 13d of the driver ICs 12 and 13 which are slaves. Therefore, the analog switches 2 of these driver ICs remain OFF.
Note that the precharge pulse PR is an original reset pulse generated in the reset period RT in the active matrix type organic EL panel. Further, during the precharge period or reset period RT (see FIG. 2A), the cathode side of the organic EL elements 9b for one horizontal line to be subjected to constant voltage reset is connected to the ground GND.

The analog switch 2 of the driver IC 11 is turned ON while the precharge pulse PR is “H”, and sets the reset voltage output line 3 to the reset voltage VRS. As a result, the reset voltage VRS is output to the output terminals P1,... Pi, Pn of the driver IC 11 via the reset switches SW that are ON during the period when the precharge pulse PR is “H”. Further, the reset voltage VRS is also sent to the reset voltage output line 3 of the driver ICs 12 and 13 via the I / O terminals 11 a and 11 b and the wiring lines 14 and 15.
As a result, the same reset voltage VRS is also output to the output terminals P1,. As a result, the terminal pins of the organic EL panel 9 for one horizontal line are simultaneously set to the reset voltage VRS, and the capacitors C of the pixel circuits 9a for one horizontal line are simultaneously reset with this voltage.
At this time, the analog switches 2 of the driver ICs 12 and 13 are OFF, and the reset voltage generation circuit 1 provided therein does not participate in the reset operation.
In the driving of the active matrix type organic EL panel, the precharge pulse PR rises simultaneously with the reset control pulse RS (see FIG. 2A) as shown in FIG. 2C, and is generated for a slightly shorter period. . In the reset period RT, a write start pulse (or write pulse) WR (see FIG. 2 (d)) for writing a drive current value into the capacitor C of the pixel circuit 9a is thereafter generated. The drive current value i (see FIG. 2E) is written as a voltage value to the capacitor C of each pixel circuit 9a by this write start pulse WR, and the reset period RT ends at the end of this write.

The reset control pulse RS in FIG. 2A is a timing control signal having a predetermined frequency that separates a display period D corresponding to a scanning period of one horizontal line and a reset period RT corresponding to a blanking period of horizontal scanning. Since the passive organic EL panel does not require a write start pulse, unlike the active matrix type, the reset control pulse RS is usually a reset pulse. In this case, the analog switch 2 and the reset switch SW of the driver IC 11 are turned on during the “H” period of the reset control pulse RS. In the passive organic EL panel, Xa ... Xi ... Xn, X2a ... X2i ... X2n, X3a ... X3i ... X3n in the organic EL panel 9 form a column line, and an organic EL element is directly connected thereto. This drive current value i is larger than that of the active matrix type organic EL panel 9. Except for these matters and the reset voltage value, there is no substantial difference from the active matrix type organic EL panel 9.
As a result, the output terminals P1,..., Pi,... Pn of the driver ICs 11 to 13 are simultaneously applied with the constant voltage VRS that is the output voltage of OP1a, the capacitor C of each pixel circuit 9a is reset to the constant voltage, and then driven. The current value is written.
In the passive organic EL panel, the organic EL elements for one horizontal line are directly reset to the constant voltage VRS via the column line. Therefore, when the drive current value i is discharged, the reset voltage VRS is a predetermined constant voltage equal to or lower than the voltage at which the organic EL element emits light with respect to the ground GND.

  In the embodiment of FIG. 1, the master driver IC 11 is an IC arranged at the center of the three of the driver ICs 12 and 13. Therefore, the characteristics of the reset voltage of the capacitor C of each pixel circuit 9a arranged in the column direction of one horizontal line are the connection points where the output voltage of OP1a is substantially at the center position of the set voltage output line 3 in this embodiment. Therefore, the central part is slightly higher than the horizontal one column pin, and both ends are slightly lower. However, the whole is substantially flat. As a result, even if there is a slight difference in the driving characteristics (driving current value of each output terminal) in the low gradation region where the driving current value is small between the driver ICs 11 to 13, the reset voltage at the boundary position of these ICs The difference is not noticeable. Therefore, even when adjacent terminal pins are driven from different driver ICs, the luminance unevenness at the boundary of the driver ICs in the low gradation region is reduced.

FIG. 3 is a block diagram of another embodiment of the present invention. The master driver IC 11 sends a constant voltage Vc for resetting lower than the reset voltage VRS to the slave driver ICs 12 and 13.
The reset voltage generation circuit 100 of the driver ICs 11, 12, and 13 in FIG. 3 is provided with a buffer amplifier (voltage follower by an operational amplifier) 1d between OP1a and D / A1b of the reset voltage generation circuit 1 in FIG. .
Further, in this embodiment, the reset voltage output line 3 in FIG. 1 is divided into a constant voltage output line 3a and a reset switch connection line 3b. The constant voltage output line 3a is connected to an I / O terminal that outputs a constant voltage Vc to an adjacent IC, similarly to the reset voltage output line 3 of FIG. The reset switch connection line 3b is a line that commonly connects the other end to one end of the reset switch SW connected to each of the output terminals P1,.
The buffer amplifier 1d has its output terminal connected to the constant voltage output line 3a via the analog switch 2, and its output is connected to its (−) input. This receives the output voltage of D / A 1b at the (+) input, amplifies it with a predetermined amplification factor, and outputs a constant voltage Vc for resetting to the constant voltage output line 3a. The constant voltage Vc at this time is lower than the reset voltage VRS in the embodiment of FIG. As a result, the voltage transmitted to other ICs is kept low, and the driving capability of the OP1a built in each driver IC is made lower than that of the embodiment of FIG.
OP1a is provided between the constant voltage output line 3a and the reset switch connection line 3b. That is, the output terminal of the buffer amplifier 1d and the (+) input of OP1a are connected to the constant voltage output line 3a, and the output of OP1a is connected to the reset switch connection line 3b.

Thereby, the constant voltage Vc by the buffer amplifier 1d of the driver IC 11 is sent to the constant voltage output line 3a of each driver IC 12, 13 via the constant voltage output line 3a and the I / O terminals 11a, 11b of the driver IC 11. . Then, OP1a of each of the driver ICs 11 to 13 is driven by the constant voltage Vc of the constant voltage output line 3a to generate the reset voltage VRS as its output voltage.
By adopting such a configuration, this embodiment does not need to transmit the high reset voltage VRS itself as in the reset voltage generation circuit 1 of FIG. 1, and the individual operation by the OP1a incorporated in each driver IC. The reset voltage VRS can be generated respectively. As a result, the driving capability of each OP 1a can be kept low accordingly.

As described above, the I / O terminals 11a to 13a and 11b to 13b in the embodiment correspond to one side of an adjacent IC when rectangular ICs similar to the IC are arranged adjacent to each other. Need only be provided on both sides of the rectangle, and need not necessarily be arranged in a corresponding positional relationship.
In the embodiment, the reset operation is performed when the precharge pulse PR becomes “H” in the reset period, but the reset operation is performed when this pulse becomes “L” in the reset period. May be. Further, although the precharge pulse PR is used as the reset pulse, the reset control pulse RS or the timing control pulse may be used as the reset pulse, and other pulses generated in the reset period RT in synchronization with these may be used. .

In the embodiment, an example in the case of resetting the capacitor of the pixel circuit in the active matrix type organic EL display panel is mainly described. However, as described in the embodiment, the present invention is a passive matrix type organic EL. Of course, the present invention can also be applied to the case where the terminal voltage of the OEL element of the display panel is reset at a constant voltage.
Further, in the embodiment, an example in which three driver ICs are provided in the organic EL display device is given. However, another slave driver IC is added in front of the driver IC 12, and the I / O terminal 12a of the driver IC 12 is provided. May be connected to the same I / O terminal of the added previous stage slave driver IC by external wiring. The added slave driver IC in the previous stage sends the reset voltage VRS of the master driver IC 11 via the reset voltage output line 3 (constant voltage output line 3a) of the driver IC 12. Similarly, it is the same when a slave driver IC is further added behind the driver IC 13.
Therefore, the present invention can be applied even when four or more driver ICs are provided on the column side of the organic EL display panel. Of course, the number of driver ICs may be two.
In the embodiment, a voltage for constant voltage reset is generated using an operational amplifier OP having a predetermined amplification factor, but OP may be a general amplifier.
Furthermore, in the embodiment, D / A is used as the output stage current source. However, a current source such as a current mirror circuit is further provided as an output stage, and this output stage current source is current-driven by the output current of D / A. You may make it do.
Further, the pixel circuit of the embodiment shows a circuit mainly composed of P-channel MOS transistors, but it goes without saying that it may be an N-channel MOS transistor or a circuit combining this with a P-channel MOS transistor. .

FIG. 1 is a block diagram of an organic EL display device according to an embodiment to which the organic EL drive circuit of the present invention is applied. FIG. 2 is a constant voltage reset timing chart. FIG. 3 is a block diagram of another embodiment of the present invention.

Explanation of symbols

1, 20 ... constant voltage reset circuit,
1a: operational amplifier (OP), 1b: D / A conversion circuit (D / A),
1c: Data register, 2 ... Analog switch,
3 ... I / O terminal connection line, 4 ... current source,
5 ... D / A conversion circuit (D / A), 6 ... register,
7 ... MPU, 8 ... Control circuit, 9 ... Organic EL panel,
9a: Pixel circuit (display cell),
10 ... Active matrix organic EL panel,
11-13 ... Driver IC,
11a, 11b, 12a, 12b, 13a, 13b ... I / O terminals,
11c, 11d, 12c, 12d, 13c, 13d ... input terminals,
14, 15 ... wiring lines.

Claims (19)

An organic EL element via a terminal pin of the organic EL panel during the reset period in a timing control signal having a predetermined frequency for separating a display period corresponding to a scanning period of one horizontal line and a reset period corresponding to a blanking period of horizontal scanning Alternatively, in the organic EL driving circuit formed as an IC that resets the capacitor of the pixel circuit to a constant voltage,
A reset voltage generating circuit for generating a predetermined constant voltage for the constant voltage reset;
The timing control signal provided between the output of the reset voltage generation circuit and the terminal pin, a reset control signal similar to the timing control signal, a reset pulse, and other signals generated during the reset period in synchronization with these signals or pulses A reset switch that is turned ON / OFF in response to any one of the pulses of
An organic EL driving circuit having an output terminal for outputting the predetermined constant voltage as a voltage for resetting to another IC adjacent to itself having a circuit similar to the organic EL driving circuit.   The organic EL panel has a large number of the terminal pins, the IC is rectangular, the output terminal is an input / output terminal, and the rectangular so as to correspond to one side of the adjacent other IC The reset voltage generation circuit includes an amplifier that generates the predetermined voltage, and the reset switch is provided corresponding to at least a plurality of the plurality of terminal pins. 2. The organic EL drive circuit according to claim 1, wherein the plurality of reset switches are simultaneously turned on in response to any one of the signals.   The input / output terminals provided on both sides of the IC are connected to each other by a wiring line inside the IC, and the output of the amplifier is connected to the wiring line through a switch circuit. 3. The organic EL drive circuit according to claim 2, wherein the one signal is a reset pulse, and the certain switch circuit is turned on together with the plurality of reset switches in response to the reset pulse.   The output terminal of the amplifier is connected at a substantially central position of the wiring line via the switch circuit, and the IC is connected to the predetermined voltage via the input / output terminal of the IC. The organic EL drive circuit according to claim 3, wherein the organic EL drive circuit becomes a master by outputting to an IC, and the other adjacent IC becomes a slave by receiving the predetermined voltage via its input / output terminal.   5. The organic EL drive according to claim 4, wherein the other adjacent IC and the IC have substantially the same circuit configuration, and the certain switch circuit of the other IC serving as the slave is maintained in an OFF state. circuit.   Further, an output stage current source is connected to each of the plurality of terminal pins, and the plurality of output stage current sources send drive currents to the capacitors of the organic EL element or the pixel circuit, respectively, and the amplifier 6. The organic EL drive circuit according to claim 5, wherein the organic EL drive circuit is an operational amplifier, wherein the reset pulse is a precharge pulse, and the predetermined voltage is a reset voltage. ,   The reset voltage generation circuit further includes a first D / A conversion circuit, the output stage current source includes a second D / A conversion circuit, and the first D / A conversion circuit includes a D / A conversion circuit. Data for A conversion is set, and the operational amplifier is connected to a power supply line + Vcc through a reference resistor, receives the voltage converted by the first D / A conversion circuit as an input voltage, and receives the reset voltage. 7. The organic EL driving circuit according to claim 6, wherein the second D / A conversion circuit receives display data and D / A converts the display data to generate the driving current.   The reset voltage generation circuit further includes a buffer amplifier between the first D / A conversion circuit and the operational amplifier, and the buffer amplifier converts the converted voltage of the first D / A conversion circuit. In response, the output of the converted voltage is applied to the wiring line and the operational amplifier via the switch circuit, and the operational amplifier receives the output of the converted voltage of the buffer amplifier and outputs the reset voltage. The organic EL drive circuit according to claim 7, which is generated.   The organic EL drive circuit according to claim 8, wherein the converted voltage is lower than the reset voltage.   The organic EL drive circuit according to claim 6, wherein the organic EL panel is of an active matrix type, and the reset voltage is for resetting a voltage of the capacitor of the pixel circuit. An organic EL element via a terminal pin of the organic EL panel during the reset period in a timing control signal having a predetermined frequency for separating a display period corresponding to a scanning period of one horizontal line and a reset period corresponding to a blanking period of horizontal scanning Alternatively, in an organic EL display device provided with a plurality of ICs having an organic EL drive circuit that performs constant voltage reset on a capacitor of a pixel circuit,
Each of the ICs includes a reset voltage generation circuit for generating a predetermined constant voltage for the constant voltage reset, and the timing control signal provided between the output of the reset voltage generation circuit and the terminal pin, the timing control signal A reset control signal, a reset pulse, and a reset switch that is turned ON / OFF in response to any one of these signals or other pulses generated in the reset period in synchronization with the pulses,
The plurality of ICs are arranged adjacent to each other, and at least one of the plurality of ICs resets the predetermined constant voltage to another one of the ICs adjacent to itself having a circuit similar to the organic EL driving circuit. An organic EL display having an output terminal that outputs the voltage as a constant voltage, and the other IC receives the predetermined voltage via the input terminal and uses the predetermined voltage as a voltage for the constant voltage reset. apparatus.   The plurality of ICs is at least two, and the input terminal of any one of the two ICs and the output terminal of any one of the other ICs are provided adjacent to each other. The organic EL display device according to claim 11, which is connected outside each IC.   The organic EL panel has a large number of terminal pins, each IC is rectangular, and the output terminal and the input terminal of each IC are input / output terminals, respectively. The reset voltage generation circuit of each of the ICs has an amplifier for generating the predetermined voltage, which is provided on each side of the rectangle so as to correspond to one side of the other adjacent IC. The reset switch of each IC is provided corresponding to at least a plurality of the plurality of terminal pins, and the plurality of reset switches are simultaneously turned on in response to any one of the signals. Item 13. An organic EL display device according to Item 12.   The input / output terminals provided on both sides of each IC are connected to each other by wiring lines inside each IC, and the output of the amplifier of each IC is a switch circuit provided in itself. The one of the signals is a reset pulse, and each of the certain switch circuits is turned on together with the plurality of reset switches in response to the reset pulse. Item 14. An organic EL display device according to Item 13.   The output terminal of the amplifier of at least one of the plurality of ICs is connected to the wiring line through a certain switch circuit at a position substantially at the center of the wiring line of the IC. By outputting a predetermined voltage to the adjacent IC via its own input / output terminal, it becomes a master, and the adjacent IC receives the predetermined voltage via its own input / output terminal. The organic EL display device according to claim 14, wherein the organic EL display device is a slave, and the certain switch circuit of the adjacent IC to be the slave is maintained in an OFF state.   The plurality of ICs are three, and the IC arranged in the center applies the predetermined voltage to the input / output terminals of the remaining two ICs through the input / output terminals of the IC. 16. The organic EL display device according to claim 15, wherein the organic EL display devices are sent to one.   The at least one IC is the IC arranged in the center, and the input / output terminal of the at least one IC is one of the input / output terminals of each of the remaining two ICs. The organic EL display device according to claim 16, wherein the organic EL display device is connected to each other through each wiring line provided outside the IC.   Further, an output stage current source is connected to each of the terminal pins to which the plurality of reset switches are connected, and each of the output stage current sources is connected to each of the organic EL elements or each of the terminal pins. 18. The organic device according to claim 17, wherein a driving current is sent to a capacitor of the pixel circuit, each amplifier of each IC is an operational amplifier, the reset pulse is a precharge pulse, and the predetermined voltage is a reset voltage. EL display device.   The organic EL display device according to claim 18, wherein the three ICs have the same circuit configuration.

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