JPH11150689A - Vertical transversal filter of special sequential scan video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a transversal filter which performs signal processing without once returning a digital video signal that is undergone compression coding to a sequential scan signal. SOLUTION: Data of 4:2:0P is inputted to an input IN. A signal processing circuit H1 which consists of an internal terminal i1, a register 11 that latches a signal of the terminal i1, a register 12 that latches its output, a coefficient multiplier M1 which weights a signal of the terminal i1 and coefficient multipliers M2 and M3 which weight outputs of the registers 11 and 12 and signal processing circuits H2 and H3 which have a similar configuration are connected on multi-stage through line memory 1 and 2. About an output of the coefficient multiplier on each stage, a total sum is calculated by a summing amplifier 4 and an output is acquired. Various filtering is performed by changing coefficients of the coefficient multipliers. Because adjacent pixel data of about one line of a target pixel by the memory 1 and 2 are acquired, processing is performed without restoring to 8:8:8 data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transversal filter used for waveform equalization and the like, and more particularly to a vertical transversal filter for a special progressive scanning video signal.

[0002]

2. Description of the Related Art Conventionally, digital data communication fields,
2. Description of the Related Art A transversal filter is used to remove various waveform distortions (transmission path distortions) generated when digital image data recorded on a storage medium is reproduced or the like.

[0003] Digitization of color television signals
Various encoding methods have been proposed for the purpose of minimizing transmission capacity and maintaining image quality. One of them is the Broadcasting Technology Development Association (BTA) T-1004 standard. This standard defines an encoding rule when transmitting video data of an HDTV signal or the like. In the case of encoding digital video data, parallel data Y obtained by converting a color video signal into an analog luminance signal (Y) into discrete values and analog color difference signals (Pb) and (Pr) into discrete values are used. The obtained parallel data Pb and Pr are decimated and encoded in accordance with human visual characteristics, and the receiving side performs operations such as complementation to reproduce the current image.

When a digital video signal is divided into three pieces of information of a luminance signal Y and color difference signals Pb and Pr, each pixel of all scanning lines has all three pieces of information on a screen of N rows × M columns. In this case, the data is expressed as 8: 8: 8 format data,
In the data in the 8: 8: 8 format of the BTA T-1004 standard, each of the luminance signal Y and the color difference signals Pb and Pr has 27 MHz sampling progressive scan data. That is, data in the 8: 8: 8 format can be said to be a format having all the information of the video data of the HDTV signal.

However, since the transmission capacity becomes excessively large in this case, there is an 8: 4: 4 format data standard in which the color difference signals are compressed and coded by thinning them one by one in the horizontal direction. In the case of data in the 8: 4: 4 format, the luminance signal Y has 27 MHz sampling progressive scanning data, and the color difference signals Pb and Pr each have 13.5 MHz sampling progressive scanning data.

The standard for thinning out the color difference signals for each scanning line in the vertical direction and compressing and encoding the data is 4: 2: 0P format data. In the case of 4: 2: 0P format data, the luminance signal Y has 27 MHz sampling sequential scanning data, and the color difference signals Pb and Pr are each 6.75.
It has the sequential scanning data of MHz sampling.

In general, data coding of 4: 2: 0P format is often used due to the trade-off between image quality and transmission capacity.

[0008] As described above, there are various formats for encoding a digital video signal. In any of these formats, the transmission quality of the transmission line, the quality of the storage medium, the deterioration in the signal processing system, and the noise are reduced. By superimposition of
The signal may be changed to a signal different from the original signal. In such a case, the transmission distortion of the digital signal is shaped,
A transversal filter is used to perform signal processing for providing a special effect (for example, increasing the sharpness of an image like an enhancer).

[0009]

However, when performing processing such as waveform equalization using a transversal filter, the video signal processing is performed after decoding the compression-coded signal and returning it to the form of a progressively scanned video signal. There was a problem that it was necessary and the circuit became complicated.

That is, taking the 420P signal as an example, 42
The 0P signal is restored to the original state, that is, an 8: 8: 8 format video signal, and then input to the Y, Pb, and Pr filters. To do this, a line converter was required, where an absolute delay of one or more lines occurred. Further, since it is necessary to perform line conversion, a plurality of line memories must be provided separately from the filter.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a transversal filter capable of performing signal processing without returning a compression-coded digital video signal to a sequential scanning signal.

[0012]

In order to achieve the first aspect of the present invention, a transversal filter according to the present invention comprises: an input terminal to which a digital video signal is input; and a digital video signal input to the input terminal. Register means for latching the digital video signal in synchronization with the synchronization signal; second register means for latching the output of the first register means in synchronization with the synchronization signal; First multiplying means for weighting; second multiplying means for weighting the output signal of the first register means;
A signal processing means including a third multiplying means for weighting an output signal of the second register means and a sum calculating means for summing outputs of the first, second, and third multiplying means; It is connected in multiple stages via delay means for delaying by an amount, so that the outputs of the sum calculation means at each stage are summed and output.

In this manner, since the one-line memory is used, the data of one line before and one line ahead of the pixel to be filtered can be used. The same processing as when performing the processing after returning can be performed.

At this time, the sum of the outputs of the first, second and third multiplication means can be calculated for each stage, but the sum of the outputs of the first, second and third multiplication means of each stage can be calculated. Is provided, the number of totalizers can be reduced.

For input of 4: 2: 0P digital coded data, if the above-mentioned signal processing means are connected in three stages, the same filtering as in the case of once returning to the 8: 8: 8 format is performed. Processing becomes possible.

When a signal of the interlaced scanning format is input, a coefficient of zero is given to the first, second, and third multiplying means in accordance with the odd or even number of the video signal line, so that the target scanning line can be obtained. Filtering can be performed by selecting a signal.

In order to achieve another aspect of the present invention, in the transversal filter of the present invention, an input terminal to which a digital video signal is input and a digital video signal input to the input terminal are synchronized with a synchronization signal. Signal processing means comprising: n register means for latching the input signal; and n + 1 multiplying means for weighting the input signal supplied to the input terminal and each output signal of the n register means. There is a summation means connected in multiple stages via delay means for delaying by a minute and taking the sum of outputs of the multiplication means at each stage.

Further, a second delay means having a delay time of one line before the signal processing means connected in multiple stages, a second multiplication for weighting an input signal to the second delay means. A delay means for delaying the input signal of the last stage of the signal processing means connected in multiple stages by one line, a third delay means, and a third means for weighting an output signal of the third delay means. Multiplication means, and the summation means together with the output of the multiplication means of each stage and the second
By calculating the sum of the output of the multiplication means and the output of the third multiplication means, it is possible to deal with a digitally encoded signal in the D1 format. D
When a digitally encoded signal of one format is input, a multiplying means for weighting an output of a delay means for delaying an input signal supplied to an input terminal of each stage, and a second,
By enabling only the third multiplying means, a transversal filter for a digitally encoded signal in the D1 format can be easily configured.

[0019]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a configuration of a transversal filter according to an embodiment of the present invention. The transversal filter shown in FIG. 1 shows the configuration of a 5-tap transversal filter for a special progressive scanning video signal (4: 2: 0P format data; hereinafter, abbreviated as "420P system"). Used to filter the vertical direction.

As in the case of a general transversal filter, various characteristics can be provided by changing the coefficient to be applied to each tap.

The transversal filter shown in FIG. 1 comprises a line memory 1, a line memory 2, a register 1
1, 12, 13, 14, 15, 16 and a coefficient multiplier M1,
, M9, the summation unit 3, and the control signal generator 4.

The transversal filter shown in FIG. 1 has signal processing circuits indicated by broken lines H1, H2, and H3 having the same circuit configuration and connected in multiple stages via line memories 1 and 2. The signal processing circuit H1 includes an input terminal i1, a register 11 for latching a signal input to the input terminal i1, a register 12 for latching an output of the register 11, a coefficient multiplier M1 for weighting an input signal of the input terminal i1, It comprises coefficient multipliers M2 and M3 for weighting the outputs of the registers 11 and 12, respectively. The signal processing circuits H2 and H3 have the same configuration. The outputs of the signal processing circuits H1, H2, and H3 are added by the sum calculator 3, and the sum is output to the output terminal OUT.
In this figure, the summation unit 3 is constituted by one. However, a summation unit for obtaining the sum of the outputs in the signal processing circuits is provided in each of the signal processing circuits H1, H2, H3, and furthermore, the summation of the whole is performed. May be provided.

FIG. 3 shows a time chart of the operation of each section. FIG. 4 shows the correspondence between the pixels of the progressively scanned video signal and the 420P signal.

A unit called a field is used as a unit representing one screen. The correspondence between pixel information and the arrangement of the 420P system will be described according to the state of pixels in a certain field.

According to FIG. 4, the signal of the 420P system has all the information of the luminance signal Y, the blue color difference signal Pb, and the red color difference signal Pr for the pixels indicated by ◎ in the odd video lines. The pixel next to the pixel indicated by is a pixel having information of only the luminance signal Y. Also, the even video lines
All pixels indicated by □ and Δ have information of only the luminance signal Y. In addition, in the case of a system in which a video signal is expressed by interlaced scanning, for example, in the case of the D1 system,
Since it is used as a video line representing the next screen, it does not appear in the current field (screen). Also,
The video signal of the 8: 8: 8 system is a system having all the information of Y, Pb, and Pr in each of the ◎ pixel, the 画素 pixel, the 画素 pixel, and the ◇ pixel.

The signal arrangement of the 420P system is such that each pixel information is arranged in the order of ◎, ◇, and is circulated in 6 words in order to arrange Y, Pb, and Pr. For reference, the signal arrangement of the D1 system is shown in the order of ○, and
It is a circular form of words.

For details of these signal formats, refer to the standards of BTA and SMPTE.

The operation of the present invention will be described with reference to FIGS.

A video signal of the 420P system is input from the input terminal IN, passes through the line memory 1, and is delayed by one line timing. The input signal is shown in FIG. 3 as L1D0. Here, “L1” of L1D0 indicates the first line, and similarly “D0” indicates the number of stages passing through the register. That is, the number following L indicates the number of lines,
The number following D is the number indicating how many steps have passed through the register. FIG. 3 shows the output signal of the line memory 1 as L2D0. The output signal of the line memory 1 is “L2D
Since it is "0", the signal does not pass through the register on the second line.

The output of the line memory 1 is input to the line memory 2 and further delayed by one line. This signal is shown in FIG. 3 as L3D0. Since the output signal of the line memory 2 is “L3D0”, it means that the signal does not pass through the register of the third line.

Each input and line memory output signal, L
As shown in FIG. 1, 1D0, L2D0, and L3D0 are supplied to registers 11 to 16, and are shifted by one word period, respectively, to signals L1D1, L2D1, L2D2, L3D1, and L3.
Output as D2.

The registers 11 to 16 are updated every word by a clock synchronized with the word.

The 5-tap filter operation on the Y signal is based on the L2D1 signal, so that the Y component (the information on the odd line) takes a signal indicated by ★ in FIG.
The control generated by the control signal generator 3 is such that the Y ′ component (the information of the even-numbered line) takes a signal indicated by 中 in the figure, and the Pb and Pr components take signals indicated by ▲ and △. Controlled by signals. In other words, the coefficient 0
A control signal is generated by the control signal generator 3 so that the control signal is applied.

In this example, a signal having a delay time of each line is selectively extracted by changing the coefficient of the coefficient multiplier. However, a switch is provided at the output terminal of the register, and a register is provided. Can be selectively connected to the summer, and the same result can be obtained by selecting a register for the early / late control based on the L2D1 signal.

As shown in FIG. 3, signals input from the input terminal IN as L1D0 are Pb1, Y1 (information of the odd-numbered line), Y'1 (information of the even-numbered line), Pr1,
Y2 (information of the odd-numbered line), Y'2 (information of the even-numbered line),..., And the signal L1D1 shifted by one word period in the register 11 is described in FIG. Have been. Similarly, L2D1 is shown in FIG. 3 as the timing of the register 12 being further shifted rightward by one word.

Although the output L2D0 of the line memory 1 and the output L3D0 of the line memory 2 are shifted by one line, they are output to the summer 4 at the same timing as that of L1D0 as shown in FIG.

If the control rule in the control signal generator 3 is as described above, in the word t2, the Pb1 of L1D1, L2D1, and L3D1 shown in FIG. Only M5 and M8 have a predetermined weight count, and the other coefficient multipliers M1, M3, M4 and M
6, M7 and M9 are multiplied by the count 0. The output of the summer 4 is L2 'which is Pb1 at the word t2.

Similarly, in the word t3, L1D1, L2 indicated by * in FIG.
Coefficient multipliers M2 and M to which Y1 of D1 and L3D1 are input
Only 5 and M8 have a predetermined weight count, and the other coefficient multipliers M1, M3, M4, M6, M7 and M9 multiply by 0. The output of summer 4 is L2 'is word t2
Is Y1.

Conventionally, the signal of the 420P system is in the original state,
That is, after the video signal is restored to the 8: 8: 8 format video signal, Y,
It was input to the Pb and Pr filters. This required a line converter, where an absolute delay of one or more lines occurred. Further, in order to perform the line conversion, a plurality of line memories must be provided separately from the filter.

However, according to the above-described embodiment of the present invention, not only the number of components is reduced, but also the absolute delay amount depends only on the number of taps, and coexistence with the D1 system is facilitated.

Next, another embodiment of the present invention is shown in FIG. FIG. 2 shows a configuration in a case where the interlaced scanning video signal is also used as a transversal filter for a component video signal called D1 format (hereinafter abbreviated as “D1 signal”). The difference from the embodiment of FIG. 1 is that after the input signal is first delayed by one line by the one-line memory 5, a signal processing circuit unit having the same configuration as the transversal filter shown in FIG. S), a one-line memory 6 for further delaying the input signal of the last stage of the signal processing unit, that is, the output of the line memory 2 by one line, a coefficient multiplier 7 for weighting,
8 is provided.

For the 420P signal, the output (tap) of each coefficient multiplier excluding the coefficient multipliers M0 and M10
When only the signal processing circuit section S is enabled, it is equivalent to the operation of only the signal processing circuit section S, and the same filtering as in the embodiment of FIG. 1 can be performed by multiplying the same coefficient as that of the transversal filter of FIG.

For the signal of the D1 system, a valid coefficient is multiplied only to the output signals of the line memories 1, 2, 5, and 6, and the outputs of the registers 11 to 16 are all multiplied by zero. For example, if only the outputs of M0, M1, M4, M7, and M10 are selected, four cascade-connected one-line memories and a coefficient multiplier are provided, and a 5-tap transversal filter can be easily configured.

Accordingly, in the embodiment of the present invention shown in FIG. 2, filtering of both signals of the 420P system and the signal of the D1 system can be dealt with only by changing the coefficient of the coefficient multiplier.

In the above description, the coefficients of the respective coefficient multipliers are not specifically described. However, the fact that various coefficients can be used according to the filter characteristics is similar to that of a general transversal filter. It is.

Although the number of coefficient multipliers is two in each stage in the first and second embodiments, more coefficient multipliers may be used in accordance with the filter characteristics. ,
How to select the number of taps in a general transversal filter is a design matter in the same manner as changing according to the filter characteristics.

[0047]

As described above, according to the present invention, it is possible to provide a transversal filter capable of performing signal processing without returning a compression-coded digital video signal to a scanning signal once.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a transversal filter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a transversal filter according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing the same sum of the transversal filter according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram showing correspondence between pixels of a progressively scanned video signal and a 420P signal.

[Explanation of symbols]

 1, 2: line memory 3: control signal generator 4: summer 5, 6: line memory 11 to 16: register M1 to M9: coefficient multiplier H1 to H3: signal processing circuit

Claims (8)

[Claims] An input terminal to which a digital video signal is input; first register means for latching the digital video signal input to the input terminal in synchronization with a synchronization signal; Second register means for latching an output in synchronization with a synchronization signal; first multiplication means for weighting the digital video signal input to the input terminal; and weighting the output signal of the first register means. A second multiplier for weighting the output signal of the second register, and a sum calculator for calculating the sum of the outputs of the first, second and third multipliers. And a signal processing means having a multi-stage connection through delay means for delaying one line, and summing and outputting the outputs of the sum calculation means at each stage. Hanging Direct transversal filter. 2. The special progressive scanning image according to claim 1, further comprising a sum calculating means for summing the sum of outputs of said first, second and third multiplying means of each stage. Vertical transversal filter for signals. 3. The vertical transversal filter of a special progressive scanning video signal according to claim 1, wherein said signal processing means is connected in three stages. 4. The apparatus according to claim 1, wherein said first, second, and third multiplying means include control signal generating means for performing filtering by multiplying a coefficient of zero according to an odd or even number of lines of the video signal. Item 4. A vertical transversal filter for a special progressive scanning video signal according to any one of Items 1 to 3. 5. An input terminal to which a digital video signal is input, first register means for latching the digital video signal input to the input terminal in synchronization with a synchronization signal, and Second register means for latching an output in synchronization with a synchronization signal; first multiplication means for weighting the digital video signal input to the input terminal; and weighting the output signal of the first register means. A second multiplier for weighting the output signal of the second register, and a first delay for delaying the digital video signal input to the input terminal by one line. Means, third register means for latching the output of the first delay means in synchronization with a synchronization signal, and latching the output of the third register means in synchronization with the synchronization signal. Fourth register means; fourth multiplying means for weighting the output signal of the first delay means; fifth multiplying means for weighting the output signal of the third register means; A sixth multiplying means for weighting the output signal of the register means, a second delay means for further delaying the digital video signal delayed by one line by the first delay means by one line, Fifth register means for latching the output of the second delay means in synchronization with the synchronization signal; sixth register means for latching the output of the fifth register means in synchronization with the synchronization signal; A seventh multiplying means for weighting the output signal of the delay means, an eighth multiplying means for weighting the output signal of the fifth register means, and a seventh multiplying means for weighting the output signal of the sixth register means. 9th power Means and the vertical transversal filter of the special sequential scanning video signal comprising the summation means from the first summing outputs of the multiplication means to the ninth. 6. An input terminal to which a digital video signal is input; n register means for latching the digital video signal input to the input terminal in synchronization with a synchronization signal; Signal processing means comprising an input signal and (n + 1) multiplication means for weighting each output signal of the n register means are connected in multiple stages via delay means for delaying one line, A vertical transversal filter for a special progressive scanning video signal, comprising summation means for calculating the sum of outputs of the multiplication means. 7. A second delay means having a delay time of one line before a signal processing means connected in multiple stages, a second weighting means for weighting an input signal to the second delay means. Multiplying means, delay means for delaying an input signal of the last stage of the multi-stage signal processing means by one line, third delay means, and weighting the output signal of the third delay means. A third multiplying means for performing the output of the second multiplying means and the output of the third multiplying means together with the output of the multiplying means of each stage by the sum calculating means.
7. The vertical transversal filter for a special progressive scanning video signal according to claim 6, wherein a sum of outputs of the multiplication means is obtained. 8. A multiplying means for weighting an output of a delay means for delaying an input signal supplied to the input terminal of each stage when a digitally encoded signal of a D1 format is inputted, 8. The vertical transversal filter of a special progressive scanning video signal according to claim 7, wherein only the multiplication means of 3 is effective.