JPH11150276A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease leaking current between a gate electrode and a source/ drain region or between channels by providing a lower gate electrode having a shape on a substrate, wherein both ends become the same as positions of the ends of a channel forming region or the outsides of the ends. SOLUTION: At the upper part of a channel forming region 4, a gate oxide film is formed as an upper insulating layer 6. An upper gate electrode 7 comprising P<+> -type single-crystal silicon is provided on the layer 6. Both ends of the upper gate electrode 7 are arranged, so that both the ends are located at the inner sides of the channel forming region 4 respectively from both ends of a source/drain region. A channel can be formed readily in the lower gate electrode, and the upper gate electrode has action to suppress channel formation. Then, when a signal higher than the threshold voltage is applied on the upper gate electrode, the channel is formed in the channel forming region, and transistor operation is conducted. Furthermore, an insulating film such as a silicon oxide film has a band gap larger that of a semiconductor. Expansion of holes and electrons is suppressed by a barrier through the upper insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a field effect transistor, and more particularly, to an SOI (Semiconductor on I / O) formed on a semiconductor on an insulating layer.
nsulator)-MOSFET or TFT (Thin)
Film Transistor).

[0002]

2. Description of the Related Art A conventional field effect transistor (FE)
FIG. 16 shows the shape of T), taking an n-channel transistor as an example. As in this figure, p ^- -type substrate 101
An n ⁺ -type gate electrode 10 is formed thereon via a gate oxide film 102.
3 are provided. The p ⁻ type substrate 101 immediately below the gate electrode 103 is a channel forming region 104. Two source / drain regions 105 composed of n ⁺ -type regions are arranged with the channel forming region 104 interposed therebetween. A part of the source / drain region 105 is located below the gate electrode 103, and the source / drain region excluding that part is covered with the oxide film 106. When a voltage higher than the threshold voltage is applied to the gate electrode 103, a layer having a high electron concentration (inversion layer) is induced on the surface of the channel formation region 104 on the gate oxide film side, which participates in current conduction. Channel.

In the FET device having such a structure, there is a first problem that a leakage current flows through an oxide film between a gate electrode and a source / drain region. As shown in FIG. 19, at a position where the gate electrode overlaps with the source / drain region, a leak current indicated by an arrow A in the figure flows between the gate electrode and the source / drain region. Even when the end of the gate electrode coincides with the end of the channel formation region as shown in FIG. 20, the leakage current indicated by the arrow B in the figure between the gate electrode and each corner of the source / drain region. Flows. The first issue (gate electrode and source /
The leakage current between the drain regions is suppressed when the gate electrode 103 and the source / drain region 105 are separated in the horizontal direction as shown in FIG. However, in the structure of FIG. 21, the offset region 10 between the gate electrode and the source / drain region
7 is formed. Since a channel cannot be induced in the offset region by the gate electrode, the resistance of this portion increases. That is, the parasitic resistance 130 is provided. For this reason, the second problem that the current value of the transistor deteriorates occurs.

Further, in the ON state, when carriers are induced in the channel formation region to form a channel, there is a third problem that a leakage current flows through an oxide film between the channel and the gate. FIG. 26 shows a band diagram in a case where a high potential is applied to a gate electrode and a channel is formed in an n-channel transistor. The energy of electrons forming the channel corresponds to the conduction band of the gate electrode. Since the conduction band has a high density of states (the number of states into which electrons can enter per certain energy), electrons in the channel can easily pass through the oxide film and reach the gate electrode.

[0005] The leak current in the first and third problems is:
It is caused by carriers such as electrons and holes flowing through the oxide film due to quantum mechanical tunneling and conduction through defects, and is particularly remarkable when the oxide film is thin.

In order to suppress a short channel effect (a problem that a threshold voltage fluctuates or a subthreshold characteristic deteriorates when a channel formation region is shortened by miniaturization of an element, that is, when a gate length is shortened). In this case, the gate oxide film needs to be thinned, so that the first and third problems become remarkable with miniaturization of the element.

FIG. 17 shows a structure capable of suppressing such a leakage current between the gate electrode and the source / drain region. This is a transistor called a body drive type SOI-MOSFET mainly for preventing a problem that an excess carrier accumulates in an SOI-MOSFET formed on an SOI substrate and fluctuates a potential. Spring Conference on Applied Physics, Spring Conference, 2nd Volume, 679
Is shown on the page.

[0008] As shown in FIG.
A p ⁺ -type upper gate electrode 113 is provided in contact with the layer 111, and a source-drain region 105 made of an n ⁺ -type region is provided at a position shifted outward from the upper gate electrode 113 by a certain distance in the horizontal direction. It is formed in the SOI layer 111. A buried oxide pattern 1 is formed below the SOI layer 111.
A lower gate 117 is provided via 16. A fixed positive voltage is applied to the lower gate electrode 117, and an input signal is applied to the upper gate electrode 113.

In the transistor of FIG. 17, holes accumulated in the SOI layer can be discharged through the upper gate, so that the problem of excess carriers accumulating in the SOI layer can be prevented.

In the structure shown in FIG. 17, the first problem (leakage current) is suppressed by shifting the end of the upper gate 113 from the end of the source / drain region 105. Also,
Also in the offset portion, since a channel is formed by the lower gate 117, the second problem (deterioration of characteristics due to parasitic resistance) can be suppressed.

In the structure of FIG. 17, since the upper gate electrode is made of p ⁺ silicon, the energy of the electrons in the channel corresponds to the forbidden band of the gate electrode as shown in FIG. Since there is no density of states in the forbidden band, it is impossible to tunnel here, so that the leakage current between the gate and the channel is suppressed, and the third problem is suppressed.

However, when the SOI layer is extremely thin, the inversion layer forming the channel and the upper gate electrode come very close to each other. Then, due to the spatial spread (leaching) of the electrons in the inversion layer and the holes in the upper gate electrode, spatial overlap occurs at each position, and as shown in FIG. Recombination or recombination via a defect level. Recombination results in the transfer of charge, which eventually results in current flow between the gate and the channel. As described above, the conventional structure shown in FIG. 17 has a problem that the leak current increases when the SOI layer is extremely thin, and the effect of suppressing the third problem is insufficient.

Also, Tanaka, 1994 VLSI Technology Symposium (1994 Symp. On VLSI)
Tech. Digest of technical
papers), page 11, reports a transistor having two gates of different conductivity types above and below an SOI layer. This is because, as shown in FIG.
An n ⁺ -type gate electrode 118 is provided above and below a gate oxide film 112, and a p ⁺ -type gate electrode 119 is provided below.

By applying the same input signal to the upper and lower gate electrodes, the flow of carriers in the channel forming region 104 is controlled. In the case where gate electrodes are provided on both the upper and lower sides of the SOI layer, the threshold voltage is too low if the upper and lower gate electrodes are both n-type, and the threshold voltage is too high if both gate electrodes are p-type. By changing the conductivity type of the electrode, the threshold voltage is set between these. This element (element of FIG. 18)
Also has the first and third problems as in the element of FIG.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and has been made in view of the above-mentioned circumstances. A main object is to provide an effect transistor.

[0016]

According to the present invention, there is provided a lower insulating layer, a semiconductor layer provided on the insulating layer, and a channel forming region of the first conductivity type provided in the semiconductor layer and having a low impurity concentration. And a source / drain region of a first conductivity type having a high impurity concentration provided on both sides of the channel formation region, and located above the channel formation region and below the channel formation region in the lower insulating layer. An upper gate electrode provided with an upper insulating layer thinner than the portion and having both ends inside the end of the channel forming region; and an upper gate electrode having both ends below the channel forming region via the lower insulating layer. Is a field-effect transistor having, on a substrate, a lower gate electrode having the same or outer shape as an end position of a channel formation region.

In one embodiment of the present invention, the channel formation region is made of an n-type semiconductor or an intrinsic semiconductor having a low impurity concentration, the source / drain regions are made of an n-type semiconductor having a high impurity concentration, and the upper gate electrode is It is made of a material having a higher work function than both the source / drain region and the lower gate.

In one embodiment of the present invention, the channel formation region is made of a low impurity concentration p-type semiconductor or an intrinsic semiconductor, the source / drain regions are made of a high impurity concentration p-type semiconductor, and the upper gate electrode is It is made of a material having a lower work function than either of the source / drain region and the lower gate.

In one embodiment of the present invention, the lower gate is made of an n-type semiconductor, the channel formation region is made of an n-type semiconductor or an intrinsic semiconductor having a low impurity concentration, and the source / drain region is made of an n-type semiconductor having a high impurity concentration. And the upper gate electrode is made of a p-type semiconductor.

In one embodiment of the present invention, the lower gate is made of a p-type semiconductor, the channel formation region is made of a p-type semiconductor or an intrinsic semiconductor having a low impurity concentration, and the source / drain region is made of a p-type semiconductor having a high impurity concentration. And the upper gate electrode is made of an n-type semiconductor.

In one embodiment of the present invention, the upper gate electrode is made of a single crystal semiconductor.

In one embodiment of the present invention, the semiconductor layer is made of a single crystal semiconductor.

In one embodiment of the present invention, means for inputting an input signal to the upper gate electrode, and means for applying a fixed voltage or a voltage that changes at a longer cycle than the input signal to the lower gate electrode include: Have more.

In one embodiment of the present invention, the channel formation region is made of a low impurity concentration n-type semiconductor or an intrinsic semiconductor, the source / drain regions are made of a high impurity concentration n-type semiconductor, and the upper gate electrode is A voltage applying means made of a material having a larger work function than any of the source / drain regions and the lower gate, wherein a potential of the lower gate electrode is higher than a maximum potential provided to the upper gate electrode by an input signal. Have.

In one embodiment of the present invention, the channel formation region is made of a low impurity concentration p-type semiconductor or an intrinsic semiconductor, the source / drain regions are made of a high impurity concentration p-type semiconductor, and the upper gate electrode is A voltage applying means made of a material having a smaller work function than any of the source / drain regions and the lower gate, such that the potential of the lower gate electrode is lower than the lowest potential provided to the upper gate electrode by an input signal. Have.

In one embodiment of the present invention, the lower gate is made of an n-type semiconductor, the channel forming region is made of an n-type semiconductor or an intrinsic semiconductor having a low impurity concentration, and the source / drain region is made of an n-type semiconductor having a high impurity concentration. The upper gate electrode is made of a p-type semiconductor,
Voltage applying means is provided so that the potential of the lower gate electrode is higher than the maximum potential provided to the upper gate electrode by an input signal.

In one embodiment of the present invention, the lower gate is made of a p-type semiconductor, the channel formation region is made of a p-type semiconductor or an intrinsic semiconductor having a low impurity concentration, and the source / drain region is made of a p-type semiconductor having a high impurity concentration. The upper gate electrode is made of an n-type semiconductor,
Voltage applying means is provided so that the potential of the lower gate electrode is lower than the lowest potential provided to the upper gate electrode by an input signal.

Another aspect is that a lower insulating layer, a semiconductor layer provided on the insulating layer, a channel formation region provided with an n-type impurity provided in the semiconductor layer, and a channel formation region are provided. An n-type source / drain region having a high impurity concentration provided on both sides with the interposition therebetween, and an upper portion having a lower film thickness than a portion of the lower insulating layer located below the channel formation region on the channel formation region An upper gate electrode provided with an insulating layer interposed therebetween and having both ends inside the end of the channel forming region, wherein the upper gate electrode is made of a material having a larger work function than the source / drain regions. On a substrate.

In still another aspect, a lower insulating layer, a semiconductor layer provided on the insulating layer, a channel forming region provided in the semiconductor layer and doped with a p-type impurity, and a channel forming region A p-type source / drain region having a high impurity concentration provided on both sides of the channel formation region, and a film thickness lower than a portion of the lower insulating layer located below the channel formation region on the channel formation region An upper gate electrode that is provided with an upper insulating layer interposed therebetween, and has a shape in which both ends enter the inside of the end of the channel formation region;
The substrate has a structure in which the upper gate electrode is made of a material having a lower work function than the source / drain regions.

In still another aspect, a lower insulating layer, a semiconductor layer provided on the insulating layer, two source / drain regions having a high impurity concentration provided in the semiconductor layer, A channel forming region sandwiched between the drain regions and having a narrower band gap than the source / drain regions; and a portion of the lower insulating layer over the channel forming region, the portion being located below the channel forming region. An upper gate electrode which is provided with a thin upper insulating layer interposed therebetween and has a shape in which both ends enter inside the end of the channel formation region is provided on the substrate.

In still another embodiment, the semiconductor layer includes:
A lower insulating layer having a charge embedded near the interface with the semiconductor layer below the semiconductor layer, and a channel forming region having a low impurity concentration or a channel formed of an intrinsic semiconductor provided in the semiconductor layer; A region, a source / drain region of a first conductivity type having a high impurity concentration provided on both sides of the channel formation region, and a lower portion of the lower insulating layer below the channel formation region on the channel formation region. This is a field-effect transistor including an upper gate electrode which is provided with an upper insulating layer having a smaller thickness than a portion to be located and has a shape in which both ends enter the inside of a channel formation region over a substrate.

In still another embodiment, the semiconductor layer includes:
A lower insulating layer at least partially formed of a ferroelectric substance below the semiconductor layer; a lower electrode provided below the lower insulating layer; and a channel having a low impurity concentration provided in the semiconductor layer. A formation region or a channel formation region made of an intrinsic semiconductor, source / drain regions of a first conductivity type having a high impurity concentration provided on both sides of the channel formation region, and the lower insulating layer on the channel formation region A field effect type having, on a substrate, an upper gate electrode provided with an upper insulating layer thinner than a portion located below the channel formation region and having both ends inside the channel formation region. It is a transistor.

According to the method of manufacturing a field-effect transistor of the present invention, a step of forming a gate insulating layer on a single crystal semiconductor, an opening in the gate insulating layer, and selective epitaxial growth from the opening are performed on the single crystal semiconductor. Growing the gate electrode in the lateral direction on the gate insulating layer; patterning the grown single crystal semiconductor to form a gate electrode made of the single crystal semiconductor at a position away from the opening; and obtaining the obtained gate electrode. Forming a source / drain region by ion-implanting or diffusing an impurity at a source / drain electrode formation position using the mask as a mask.

A different aspect of the method for manufacturing a field-effect transistor of the present invention is a step of forming a gate insulating layer on a single crystal semiconductor, providing an opening in the gate insulating layer, and performing selective epitaxial growth from the opening. A step of growing a crystalline semiconductor in a lateral direction on a gate insulating layer; a step of patterning the grown single crystal semiconductor to form a gate electrode made of the single crystal semiconductor at a position away from the opening; By depositing a film and etching it back, a step of providing a sidewall made of an insulating film on the side surface of the gate electrode, and using the obtained gate electrode and the side wall as a mask, ion-implanting or diffusing impurities, Or forming a source / drain region by epitaxially growing or depositing a semiconductor layer containing impurities. .

Still another aspect of the method for manufacturing a field effect transistor of the present invention is a step of forming a gate insulating layer on a single crystal semiconductor, a step of providing an opening in the gate insulating layer, and a step of forming an opening in the gate insulating layer. An amorphous semiconductor is deposited, a single crystal semiconductor is laterally grown by solid phase epitaxial growth from an opening, and the grown single crystal semiconductor is patterned to form a gate electrode made of the single crystal semiconductor at a position away from the opening. And forming a source / drain region by ion-implanting or diffusing an impurity or epitaxially growing or depositing a semiconductor layer containing the impurity.

In still another aspect of the method for manufacturing a field effect transistor according to the present invention, a step of forming a gate insulating layer on a single crystal semiconductor and a step of depositing an amorphous semiconductor on the gate insulating film are performed. And providing an opening in the amorphous semiconductor; and
A step of filling by depositing a second amorphous semiconductor, a step of laterally growing a single-crystal semiconductor by solid-phase epitaxial growth from this opening, and patterning the grown single-crystal silicon to leave the opening from the opening. A step of forming a gate electrode made of a single crystal semiconductor at a position, and a step of forming source / drain regions by ion-implanting and diffusing impurities or epitaxially growing or depositing a semiconductor layer containing impurities. Have.

A further different aspect of the method for manufacturing a field effect transistor according to the present invention is a method for manufacturing a semiconductor substrate or a lower gate electrode having a predetermined shape formed on a semiconductor substrate and an insulating film formed on the lower gate electrode. Forming an upper gate insulating layer on an SOI layer made of a lower insulating layer and a single crystal semiconductor formed on the lower insulating layer, and growing a single crystal semiconductor in a lateral direction on the upper gate insulating film Patterning the grown single-crystal silicon to form an upper gate electrode made of a single-crystal semiconductor at a position away from the opening; and ion-implanting or diffusing impurities, or forming a semiconductor layer containing impurities. Forming source / drain regions by epitaxial growth or deposition.

The FET structure according to the present invention will be described with reference to an example shown in FIG.

In this structure, a semiconductor layer 3 (SOI layer) made of a single crystal semiconductor is formed on a lower insulating layer 2.
A channel formation region 4 having a low impurity concentration is formed in the SOI layer, and source / drain regions 5 having a high impurity concentration are formed on both sides of the SOI layer. On this channel formation region, a p-type upper gate electrode 7 is provided via an upper insulating layer 6.

As shown in FIG. 1, the upper gate electrode 7
It is formed inside the end of the channel forming region 4 and separated from the source / drain region. Also, the upper insulating layer 6
Is thinner than the lower insulating layer. Lower gate electrode 1
Is formed below the lower insulating layer 2. In the example shown in FIG. 1, an n-type impurity is introduced into a support substrate of an SOI semiconductor substrate, and is used as a lower electrode 1.

[0041] Then as shown in FIG. 2, the input signal V _in is applied to the upper gate 7, a fixed positive voltage V _bg is applied to the lower gate electrode 1. The channel is formed by inducing electrons below the semiconductor layer by a high voltage of the lower gate electrode. Further, a signal input to the upper gate electrode has an action of controlling the amount of electrons induced by the lower gate electrode.

The structure of FIG. 1 is different from the structure of FIG. 17 in that a thin insulating film such as a silicon oxide film is provided below the upper gate electrode. In this structure, as shown in the band diagram of FIG. 22, since the upper insulating layer such as a silicon oxide film has a larger bandgap than the semiconductor, the spread of holes and electrons due to the quantum mechanical effect is suppressed by the barrier of the upper insulating layer. Is done. Therefore, the above-described direct or indirect recombination via a defect level shown in FIG. 25 is suppressed, and the leak current between the gate and the channel is reduced. Channel electrons cannot tunnel to gate (Fig. 22C)
The points are the same as the structure of FIG.

In the present invention, it is preferable that at least one, preferably both of the semiconductor layer and the upper gate electrode are formed of a single crystal semiconductor. FIG. 23 shows an example in which a defect level appears at the interface between the upper gate electrode and the upper insulating layer; however, by using a single crystal semiconductor, the density of defect states existing at the interface can be reduced. .
When the defect level at the interface decreases, tunneling through the defect level is suppressed, so that the leak current is further reduced. In addition, a single-crystal gate has an advantage that a gate resistance component can be reduced as compared with a polycrystalline gate.

The conventional example of FIG. 17 has a function of eliminating extra holes in the SOI layer in the channel formation region as shown in FIG. 24. However, as in the present invention, a thin insulating film is provided between the channel and the gate. Even if the upper insulating layer formed by the above is provided, the holes in the SOI layer can pass through the thin insulating film (D in FIG. 22) and tunnel to the upper gate electrode as shown in FIG. This is because the energy of holes in the SOI layer corresponds to the valence band of the upper gate, so that the density of states (the number of states into which holes of a certain energy can enter) due to tunneling is large. This is because movement is likely to occur.

Therefore, electron tunneling from the channel to the upper gate, which causes a leakage current, is suppressed by the energy of the channel electrons corresponding to the upper gate electrode forbidden band, and recombination is suppressed by the thin insulating film. And the distribution of holes is suppressed. However, tunneling of excess holes is easy.

When it is more important to suppress the leakage current between the gate and the channel, a thin insulating film is set to be thick. In this case, when the insulating film is thick, tunneling via the interface state is suppressed, so that tunneling through the insulating film is further suppressed, and leakage current is reduced. On the other hand, when the insulating film is thick, tunneling of holes is reduced, so that the ability to eliminate excess holes is reduced. This is because, for example, it is necessary to strongly suppress the leakage current in order to extend the life of the battery that supplies power in a device that constitutes a circuit with this element, while generating holes due to α-ray irradiation and the like. It is effective to apply when the influence is small.

Further, in the present invention, since the upper gate electrode is disposed on the inner side by the source / drain region, a tunnel current between the source, the drain and the gate seen in a normal FET (arrows A and B in FIGS. 19 and 20). ) Does not flow.

When the upper gate electrode is usually disposed inside the channel formation region rather than the source / drain regions, the channel formation region (offset region 127) where the upper gate electrode does not overlap is indicated by 130 in FIG. Although parasitic resistance is added, in the present invention, a channel can be formed also in the offset region by the electric field of the lower gate electrode, so that the problem of the parasitic resistance does not occur.

When electric charges (positive for an n-channel transistor, negative for a p-channel transistor) are introduced into the lower insulating film, an electric field for inducing a channel can be formed instead of the lower gate, so that the lower gate can be omitted. Alternatively, the voltage applied to the lower gate can be reduced. The same applies to the case where the ferroelectric layer is provided in the lower insulating layer, and polarization charges are generated at the interface of the ferroelectric layer on the semiconductor layer side, thereby generating the charges.

When an n-type transistor in an n-channel transistor and a p-type impurity in a p-channel transistor are introduced into a channel formation region, an electric field between these impurities and a gate electrode causes a lower portion of a semiconductor layer in an n-channel transistor to be formed. Since an electric field is induced in the p-channel transistor that is higher than the upper part and lower in the semiconductor layer in the upper part than in the lower part, an electric field similar to that formed by the lower gate is formed. Thereby, the lower gate can be omitted. Alternatively, the voltage applied to the lower gate can be reduced.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described more specifically.

Embodiment 1 An embodiment of the present invention will be described with reference to FIG. 1 using an n-channel transistor as an example. In this embodiment, an n ⁺ type silicon substrate is used as the lower gate electrode 1, a buried oxide film is provided thereon as the lower insulating layer 2, and an SOI layer made of single crystal silicon is provided thereon as the semiconductor layer 3. The thickness of the buried oxide film is, for example, 25 to 30 nm. The thickness of the SOI layer is, for example, 10 nm.

The central portion of the semiconductor layer 3 (SOI layer) is an n ⁻ -type channel forming region 4 having a low phosphorus concentration and has a width of 0.15 μm in the horizontal direction in the cross section of FIG. The concentration of phosphorus is usually 10 ¹⁹ cm ^-3 or less, for example, 1 × 10
¹⁸ cm ^-3 . On both sides, n ⁺ -type source / drain regions 5 into which phosphorus is introduced at a high concentration are formed. Source/
The concentration of phosphorus in the drain region 5 is usually 5 × 10 ¹⁸ c
m ⁻³ or more, for example, 5 × 10 ¹⁹ cm ⁻³ . A gate oxide film is provided as an upper insulating layer 6 above the channel forming region 4, and an upper gate electrode 7 made of p ⁺ -type single crystal silicon is provided thereon. The thickness of the upper insulating layer 6 is smaller than the thickness of the lower insulating layer 2, for example, 1.5 nm in thickness.
Formed. Both ends of the upper gate electrode 7 are arranged so as to be located inside the channel forming region 4 by, for example, 20 nm from both ends of the source / drain regions.

In order to operate this FET, as shown in FIG. 2, an input signal is input to the upper gate electrode, and a positive fixed voltage is applied to the lower gate electrode. For example, a fixed voltage of 5 V (V _{bg in} FIG. 2) is applied to the lower gate electrode, and an input signal is applied to the upper gate electrode (V _{in in} FIG. 2). The amplitude of the input signal is, for example, from 0V to 0.5V. The threshold voltage is determined depending on the lower gate voltage or the impurity concentration of the channel formation region, etc., but the lower gate voltage or the impurity concentration of the channel formation region is adjusted so that the threshold voltage is within the range of the amplitude of the input signal. Should be adjusted.

In this device, the potential of the lower gate electrode is higher than the inversion potential in the semiconductor layer (the potential at which an inversion layer serving as a channel through which electrons flow is formed), and the potential of the upper gate electrode is higher than the inversion potential. The transistor operation is performed by being set to be lower (the potential of the lower gate electrode is higher than the potential of the upper gate electrode. Even when the highest voltage is applied to the upper gate, the potential of the upper gate electrode is changed). Thus, the potential of the lower gate electrode is set to be higher, where the potential of the electrode is a value obtained by subtracting the work function difference between the electrode and the reference electrode from the applied voltage.) . The inversion potential is typically equal to or lower than the source potential in an n-channel transistor, and the difference is within 0.2 V. The lower gate electrode has a function of easily forming a channel, and the upper gate electrode has a function of suppressing the formation. Then, when a signal having a voltage higher than the threshold voltage is applied to the upper gate electrode, a channel including electrons is formed in the channel formation region, and the transistor operates.

In this structure, as shown in the band structure of FIG. 22, since the insulating film such as the silicon oxide film has a larger band gap than the semiconductor, the spread due to the quantum mechanical effect of holes and electrons is increased by the barrier formed by the upper insulating layer. Is suppressed by In addition, by using a single crystal semiconductor for the upper gate electrode, the density of defect states existing at the interface is reduced,
Reduce leakage current.

If the material forming the upper gate electrode is made of a material having a higher work function than the semiconductor having a high impurity concentration forming the source / drain regions, even if a signal having a negative voltage is not applied to the upper gate electrode, The potential can be lower than the inversion potential. When the source electrode is n-type silicon, p-type silicon, p-type polysilicon, p-type germanium, p-type silicon-germanium mixed crystal, or a metal such as TiN, Ta, W, tungsten silicide, Metal compounds satisfy this condition.

Also, the lower gate electrode is referred to as the upper gate electrode.
When the gate electrode is formed of a material with a low work function,
It becomes easier to obtain a higher potential than the pole. For example, the upper gate
Is p ⁺Type silicon with lower gate n⁺Mold silicon, n⁺
Polysilicon, p-type or n-type germanium, p-type
Or n-type silicon-germanium mixed crystal, TiN, T
a, W, or a metal such as tungsten silicide,
This condition is satisfied when the compound is a metal compound.

Also, the positive potential of the lower gate electrode,
Since both n-type impurities introduced into the channel formation region have a function of easily forming a channel, increasing the positive voltage of the lower gate electrode reduces or eliminates n-type impurities introduced into the channel formation region. it can. Conversely, when the concentration of the n-type impurity introduced into the channel formation region is increased, the positive voltage of the lower gate electrode can be reduced or omitted.

The voltage applied to the lower gate electrode is
In a state where the transistor is turned on, it is only necessary that the voltage is higher than the upper gate electrode. Therefore, the voltage applied to the lower gate electrode may change with time. For example, the lower gate electrode voltage is kept at +5 V during a state in which the circuit is in operation, for example, a certain number of continuous switching operations, and then the lower gate voltage is reduced to 0 V during a period during which the circuit does not perform a switching operation. You can also. When the lower gate voltage (the voltage of the lower gate electrode) is lowered, the threshold voltage is increased, and the leakage current is reduced. Therefore, power consumption during a period when the circuit is not operated can be reduced.

Alternatively, the voltage applied to the lower gate electrode may be changed in synchronization with the voltage applied to the upper gate electrode. For example, when 0 V is applied to the upper gate electrode, 4.5 V is applied to the lower gate electrode, and when 0.5 V is applied to the upper gate electrode, 5 V is applied to the lower gate electrode.

In the above description, a case has been described where a silicon single crystal is used as the upper gate electrode. However, the upper gate electrode may be formed of a polycrystalline semiconductor such as p ⁺ polysilicon. In the case of using a polycrystalline semiconductor, leakage current may be increased due to the influence of a defect level as compared with the case of using a single crystal, but this is preferable in that the manufacturing process is simplified. Even if the leakage current slightly increases due to the effect of tunneling via a defect level, the leakage current is smaller than that of the conventional structure (FIG. 17) by the amount by which the upper insulating layer 6 suppresses recombination of electrons and holes. Is suppressed.

Further, an intrinsic semiconductor can be used without introducing impurities into the channel formation region. This is preferable in that the step of introducing impurities into the channel formation region can be omitted, which simplifies the manufacturing process. Further, since a decrease in current due to impurity scattering can be suppressed as compared with the case where impurities are introduced, it is preferable in that the current can be increased.

Further, in the present invention, the semiconductor layer 3 can be formed of polysilicon. In this case, similarly to the case where a single crystal is used, the leak current increases due to the influence of the defect level, and the resistance component increases due to the influence of the grain boundary existing in the polycrystal, as described above. However, it is preferable in that the manufacturing process is simplified. Even if the leakage current slightly increases due to the effect of tunneling via a defect level, the leakage current is smaller than that of the conventional structure (FIG. 17) by the amount by which the upper insulating layer 6 suppresses recombination of electrons and holes. Is suppressed.

The thickness of the semiconductor layer 3 is typically set to 50 nm or less in order to suppress the short channel effect. However, when the short channel effect is suppressed by using a thin upper insulating layer or the like, or when the channel length is reduced. For example, when the length is long and the short channel effect is hard to occur, the thickness may be thicker.

Further, in the present invention, the semiconductor layer 3 has a thickness of 5 nm.
The following thinning is also effective in the characteristics of the transistor. That is, in the transistor of the present invention, the channel is formed on the back side (the lower insulating layer side) of the semiconductor layer 3. However, when the semiconductor layer 3 is thinned to the same thickness as the inversion layer serving as the channel, the position where the channel is formed Is substantially no different from when it is formed on a surface. When the channel is formed on the surface, the characteristics of the transistor are better than when the channel is formed on the back side. However, the characteristics can be improved by creating a situation in which the channel is formed substantially on the surface. Further, since the thickness of the inversion layer is considered to be about several nm to about 10 nm, the same effect can be obtained to some extent by reducing the thickness of the semiconductor layer 3 to about 15 nm or less.

The lower insulating layer only needs to be thicker than the upper insulating layer, and the thickness of each layer is not limited to the above. For example, SIM
A lower insulating layer thickness of about 80 nm to 400 nm as obtained with an OX substrate may be used. Also, for example, 5n
A thin film having a thickness of m to 25 nm may be used. When the lower insulating layer is thick, the lower gate voltage is set high, and when the lower insulating layer is thin, the lower gate voltage is set low. The upper insulating layer may be thinner than the lower insulating layer.
A thickness of 0 nm may be used. The shift between both ends of the upper gate electrode 7 and both ends of the source / drain region may be set to such an extent that the leak current can be suppressed.
A value in the range of 50 nm may be used.

It is sufficient that the equivalent oxide thickness of the upper insulating layer is smaller than the equivalent oxide thickness of the lower insulating layer. This is based on the fact that the gate capacitance of a normal FET is larger than the capacitance between the channel and the substrate, the upper insulating layer capacitance corresponds to the gate capacitance of the normal FET, and the lower insulating layer capacitance corresponds to the substrate capacitance. Note that the equivalent oxide film thickness refers to a film thickness of SiO ₂ that can provide the same capacity as a material other than an oxide film (such as Si ₃ N ₄ or Ta ₂ O ₅ ) when used as an insulating film.
In order to eliminate excess holes by tunneling, it is necessary to reduce the thickness of the upper insulating layer. Typically 3n
In the case of a SiO ₂ film having a thickness of ₂ m or less, the tunneling becomes large, so that it is preferable.
Conversely, when the tunneling of excess holes is not important for the application, the SiO ₂ film is formed to a thickness of 3 nm or more, for example,
It may be about nm.

[Embodiment 2] In the present invention, as shown in FIG. 3, the lower gate electrode 1 may be formed so as not to reach the entire lower portion of the source / drain region 5. By doing so, the parasitic capacitance between the source / drain region 5 and the lower gate electrode 1 can be reduced. Such a structure can be formed of the same material as that described in the first embodiment.

FIG. 3 shows a structure in which the lower gate electrode 1 is buried in the lower insulating layer 2. However, such a structure is not always necessary, and the channel forming region 4 on the substrate 8 as shown in FIG. The substrate may be protruded upward at the lower portion and used as a lower gate electrode. In this case, the lower gate electrode 1 is, for example, an n ⁺ type in which phosphorus is introduced at a high concentration. The substrate 8 excluding the region of the lower gate electrode 1 is, for example, n
⁺ Type and p ^- type. Further, p n ⁺ -type region is provided ^- in the mold of the substrate 8, to a position in contact with the interface between only n ⁺ -type region is a buried oxide film in a channel formation region 4 lower, protruding on the upper side, embedded in other regions The lower gate electrode 1 may be located at a position distant from the interface with the oxide film and projecting upward.

[Embodiment 3] In Embodiment 1 or 2, n
Although a channel-type FET has been described, a p-channel FET can be formed in a similar manner. That is,
In the structure of FIG. 1, a p ⁺ -type substrate is used as the lower gate electrode 1 instead of the n ⁺ -type substrate used in the first embodiment, and boron is used as the channel formation region 4 in the center of the semiconductor layer 3 (SOI layer). ^Is made into ap ⁻ region in which a low concentration (for example, 1 × 10 ¹⁸ cm ⁻³ ) is introduced, and the source / drain region 5 is made into a p ⁺ type in which boron is introduced into a high concentration (for example, 5 × 10 ¹⁹ cm ⁻³ ). The gate electrode 7 is an n ⁺ type.

Then, a negative fixed voltage, for example, a voltage of −5 V to the source is applied to the lower gate electrode, and the amplitude of the input signal is changed from 0 V to −0.5 V to the source. Then, the transistor operation can be performed as in the first embodiment. In the second embodiment, the n-type and the p-type are replaced, a negative fixed voltage, for example, −5 V is applied to the lower gate electrode, and the amplitude of the input signal becomes 0 to −0.5 V with respect to the source. By doing so,
A p-channel FET having the same shape as that of the second embodiment can be obtained.

In a p-channel transistor, the potential of the lower gate electrode is lower than the inversion potential in the semiconductor layer (the potential at which an inversion layer serving as a channel through which holes flow) is formed, and the potential of the upper gate electrode is lower than the inversion potential. (The potential of the lower gate is lower than the potential of the upper gate). The inversion potential is typically equal to or higher than the source potential in a p-channel transistor, and the difference is within 0.2 V. When a signal having a voltage lower than the threshold voltage is applied to the upper gate electrode, a channel including holes is formed in the channel formation region, and the transistor operates.

Further, regarding the operation principle and the function and effect, n
Same as the channel transistor except that the polarity is reversed.

The material constituting the upper gate electrode is as follows:
If a material having a lower work function than that of the semiconductor having a high impurity concentration constituting the source / drain regions is used, the potential can be reduced without applying a signal having a positive voltage to the upper gate electrode.
It can be higher than the inversion potential. When the source electrode is p-type silicon, n-type silicon,
n-type polysilicon, p-type germanium, p-type silicon
A germanium mixed crystal, or a metal or metal compound such as TiN, Ta, W, or tungsten silicide satisfies this condition.

When the lower gate electrode is formed of a material having a smaller work function than the upper gate electrode, it is easier to obtain a higher potential than the upper gate electrode.

Embodiment 4 Another embodiment of the present invention will be described.

In the n-channel transistor described in the first and second embodiments, when an electric field is formed such that the lower part of the SOI layer is higher than the surface, a channel is formed in the channel forming region by the electric field. Therefore, the lower gate electrode need not be used.

This structure, as shown in FIG.
In the above, the lower gate electrode is not formed (for example,
The thickness of the lower insulating layer may be increased. ) And the semiconductor layer 3
Except for increasing the phosphorus concentration of the channel forming region 4 at the center of the (SOI layer) to, for example, 5 × 10 ¹⁸ cm ⁻³ or more,
The structure is the same as that of the first embodiment.

In this case, the electric field applied to the upper gate electrode depletes the SOI layer and turns phosphorus into ions having a positive charge, so that an electric field is formed such that the lower part of the SOI layer is higher than the surface. Is done.

[Embodiment 5] FIG. 6 shows still another embodiment of the present invention, in which a positive charge 10 is buried in an insulating film. The channel is formed by forming an electric field that is higher than that of the above.

The positive charge 10 in the insulating film forms an electric field similar to that of the lower gate electrode to which a positive voltage is applied, and has a function of forming a channel. It is possible to reduce or omit the positive applied voltage of the lower gate electrode required for formation and doping to the channel formation region.

When a positive applied voltage is not required for the lower gate electrode, the lower gate electrode can be omitted. As a specific method of omitting the lower electrode, a method of thickening the lower insulating layer,
A method in which a substrate having a semiconductor layer over an insulator such as sapphire or glass is used.

FIG. 6 is an embodiment in which the lower gate is omitted, and can be formed in the same manner as in the first embodiment except that the lower gate electrode is omitted and the positive charge 10 is buried.

The electric charge in the lower insulating layer is realized by, for example, introducing a defect into the oxide film by silicon ion implantation, or forming a part or all of the buried oxide film by a CVD oxide film having a high defect density. can do.

The charge in the insulating film may be due to the polarization of the dielectric. For example, instead of the buried oxide film having the structure of FIG.
20 nm thick second buried oxide film 52, thickness 500
A ferroelectric layer 51 of nm and a buried oxide film 22 of thickness 20 nm are laminated in this order. This is shown in FIG. The ferroelectric layer is made of, for example, BaTiO ₃ , SrTiO ₃ ,
PbTiO ₃ , LiTaO ₃ , LiNbO ₃ , or a material obtained by adding other elements to them is used.

Once a positive voltage is applied to the lower gate electrode,
Thereafter, when the voltage is returned to 0 V, a positive charge is induced at the interface between the ferroelectric layer 51 and the buried oxide film 22, so that it is not necessary to continuously apply a positive voltage to the lower gate electrode.

The polarization (electret) induced by the heat treatment at the dielectric interface may be used as the charge in the insulating film.

In the fourth and fifth embodiments, the case of the n-channel is described. However, in the p-channel transistor, an electric field is formed such that the lower part of the SOI layer is lower than the surface. Therefore, the concentration of boron in the channel formation region is increased. In order to introduce a negative charge into the oxide film, for example, aluminum may be ion-implanted into the oxide film.

In a p-channel transistor having p-type silicon source / drain regions, if the channel forming region is Ge, Ge has a small band gap and a high hole concentration. As in the case where the channel formation is performed, a channel is easily formed, and a negative applied voltage of the lower gate electrode necessary for channel formation and doping to a channel formation region can be reduced or omitted.

The FETs described in Embodiments 1 to 5 are CM
It can be used in place of a normal MOSFET in an OS circuit. Alternatively, if the amplitude of the input signal is M
In a circuit constituted by an OSFET, a MOSFET can be replaced by this transistor to constitute a circuit.

[Embodiment 6] Further, an embodiment including a manufacturing method will be described.

As shown in FIG. 7, an SOI layer 23 made of single-crystal silicon and having a thickness of 10 nm is formed on a silicon substrate 21 via an embedded oxide film 22 having a thickness of 80 nm.
Phosphorus is implanted into the I substrate at 120 keV at a dose of 1 × 10 ¹³ cm ⁻² , and the silicon substrate 21 below the buried oxide film 22 is made n-type.

In an oxygen atmosphere, the surface of the SOI layer 23 is heated by a lamp for a few seconds, and a thickness of 1.5 n
m gate oxide films 24 are provided.

Patterning with Photoresist and RI
An opening 25 is provided in the gate oxide film by E or wet etching.

Next, as shown in FIG. 8, single crystal silicon 26 is grown on the gate oxide film by selective epitaxial growth using dichlorosilane or the like as a seed for SOI layer 23 exposed in opening 25. .

After the steps up to FIG.
A 50-nm-thick CVD oxide film 41 is deposited on the upper surface by CVD.

At a position distant from the seed opening,
By usual lithography and etching by RIE,
The single crystal silicon 26 is patterned as a gate electrode. Next, a second CVD oxide film 27 is deposited, and
The second CVD oxide film 27 is etched on the side surface of the gate electrode by etching back by anisotropic etching by E.
Forming sidewalls.

At this time, the gate electrode and the gate oxide film located outside the side wall thereof are removed by the etch back, and the steps up to FIG. 9 are completed.

Next, as shown in FIG. 10, a PSG (phosphorus glass) 30 is deposited to a thickness of 100 nm by CVD, and
Phosphorus is diffused from the PSG to the silicon layer located outside the gate side wall by a heat treatment at 0 ° C. for 10 seconds to provide source / drain regions in which phosphorus is diffused at a high concentration, thereby completing the FET of the present invention.

The doping of the gate is performed during or after the growth of single crystal silicon.

In the description of the first embodiment, the source
Formation of the drain, as in FIG. 11, n ⁺ -type silicon 2
8 may be formed by selective growth.

The source / drain regions may be formed by other methods such as diffusion of impurities from a gas phase, ion implantation, deposition of n ⁺ polysilicon or diffusion from the same. In a p-channel transistor, BSG (boron glass) or the like is used instead of PSG.

The method of forming single-crystal silicon as the upper gate electrode is not limited to the above description, but can be performed by the following methods (a) to (b).

(A) As shown in FIG. 12, after the seed opening is provided, amorphous silicon 31 is deposited on the entire surface by the CVD method, covered with the CVD oxide film 42, and the second opening is formed in the CVD oxide film 42. The second opening 32 is provided.
Then, by introducing a gas such as HCl or Cl ₂ , the amorphous silicon 31 may be removed, and single crystal silicon may be selectively grown in the obtained space. According to this method, the thickness of the single crystal silicon can be kept constant, and the single crystal silicon can be extended in the lateral direction.

(B) As in the first embodiment, after an opening as shown in FIG. 7 is provided in the gate oxide film, amorphous silicon is formed, and a heat treatment is performed at about 600 ° C. to remove the amorphous silicon from the opening. Single crystal may be formed by solid phase growth in the lateral direction. In this case, impurities such as phosphorus necessary for the gate electrode may be introduced in advance into the amorphous silicon.

(C) As shown in FIG. 13, after depositing amorphous silicon 31 on the gate insulating film, FIG.
As shown in FIG.
An opening 25 is provided in the second amorphous silicon 32.
, The opening may be filled, and the single crystal semiconductor 26 may be laterally grown from the opening by solid phase epitaxial growth as shown in FIG. In this case, it is possible to prevent the gate insulating film from being exposed when the opening is formed.

(D) Amorphous germanium or an amorphous silicon-germanium mixed crystal is used instead of amorphous silicon. Since these materials have a lower melting point than silicon, they can be solid-phase grown at low temperatures.

(E) A single-crystal gate electrode can be formed not on the SOI layer but on the bulk substrate in the same manner as in each of the above methods. In an FET on a normal bulk substrate, the first, second, and third problems remain, but by making the gate electrode a single crystal, the parasitic resistance of the gate electrode can be reduced,
Interface levels can be reduced. In a FET or the like on a bulk substrate, when the source / drain region ends are not offset from the gate electrode ends and the source / drain regions are formed by ion implantation, the step of providing a sidewall on the gate electrode can be omitted.

[0110]

According to the present invention, it is possible to provide a field effect transistor which prevents the accumulation of excess carriers while preventing the characteristic deterioration due to the short channel effect, and has a small leak current.

[Brief description of the drawings]

FIG. 1 is a diagram showing one example of a field-effect transistor of the present invention.

FIG. 2 is a diagram showing one example of a field-effect transistor of the present invention.

FIG. 3 is a diagram showing one example of a field-effect transistor of the present invention.

FIG. 4 is a diagram showing one example of a field-effect transistor of the present invention.

FIG. 5 is a diagram showing one example of a field-effect transistor of the present invention.

FIG. 6 is a diagram showing one example of a field-effect transistor of the present invention.

FIG. 7 is a sectional process view showing one example of a manufacturing process of the field-effect transistor of the present invention.

FIG. 8 is a sectional process view showing one example of a manufacturing process of the field-effect transistor of the present invention.

FIG. 9 is a sectional process view showing an example of the manufacturing process of the field-effect transistor of the present invention.

FIG. 10 is a sectional process view showing an example of the manufacturing process of the field-effect transistor of the present invention.

FIG. 11 is a sectional process view showing an example of the manufacturing process of the field-effect transistor of the present invention.

FIG. 12 is a sectional process view showing an example of the manufacturing process of the field-effect transistor of the present invention.

FIG. 13 is a sectional process view showing an example of the manufacturing process of the field-effect transistor of the present invention.

FIG. 14 is a sectional process view showing an example of the manufacturing process of the field-effect transistor of the present invention.

FIG. 15 is a sectional process view showing an example of the manufacturing process of the field-effect transistor of the present invention.

FIG. 16 is a diagram illustrating an example of a conventional field-effect transistor.

FIG. 17 is a diagram illustrating an example of a conventional field-effect transistor.

FIG. 18 is a diagram illustrating an example of a conventional field-effect transistor.

FIG. 19 is a diagram illustrating a leak current in a conventional field-effect transistor.

FIG. 20 is a diagram illustrating a leakage current in a conventional field-effect transistor.

FIG. 21 is a diagram illustrating parasitic resistance in a conventional field-effect transistor.

FIG. 22 is a band structure diagram for explaining the operation principle of the field-effect transistor of the present invention.

FIG. 23 is a band structure diagram for explaining the operation principle of the field-effect transistor of the present invention.

FIG. 24 is a band structure diagram of a conventional field-effect transistor.

FIG. 25 is a band structure diagram illustrating an operation of a conventional field-effect transistor.

FIG. 26 is a band structure diagram illustrating an operation of a conventional field-effect transistor.

FIG. 27 is a diagram showing one example of a field-effect transistor of the present invention.

[Explanation of symbols]

Reference Signs List 1 lower gate electrode 2 lower insulating layer 3 SOI layer 4 channel formation region 5 source / drain region 6 upper insulating layer 7 upper gate electrode 21 silicon substrate 22 buried oxide film 23 SOI layer 24 gate oxide film 25 opening 26 single crystal silicon 27 Second CVD oxide film 28 n ⁺ type silicon 30 PSG (phosphorus glass) 31 amorphous silicon 32 second opening 40 polysilicon layer 41 CVD oxide film 42 CVD oxide film 101 p ⁻ type substrate 102 gate oxide film 103 n ⁺ Type gate electrode 104 channel formation region 105 source / drain region 106 oxide film 107 offset region 111 SOI layer 112 lower gate oxide film 113 upper gate electrode 116 buried oxide film 117 lower gate electrode 118 n ⁺ type gate electrode 119 p ⁺ type Game G electrode

Claims (25)

[Claims] 1. A lower insulating layer; a semiconductor layer provided on the insulating layer; and a first conductive type channel forming region provided in the semiconductor layer and having a low impurity concentration. A source / drain region of the first conductivity type having a high impurity concentration provided on the channel forming region; and an upper insulating film having a lower film thickness on the channel forming region than a portion of the lower insulating layer located below the channel forming region. An upper gate electrode provided with a layer, both ends of which are inside the end of the channel formation region; and
A field-effect transistor having, on a substrate, a lower gate electrode whose both ends are the same as or outside the position of the end of the channel formation region. 2. The semiconductor device according to claim 1, wherein the channel forming region is made of an n-type semiconductor or an intrinsic semiconductor having a low impurity concentration, the source / drain region is made of an n-type semiconductor having a high impurity concentration, 2. The field effect transistor according to claim 1, wherein the field effect transistor is made of a material having a higher work function than any of the lower gates. 3. The channel formation region is made of a p-type semiconductor or an intrinsic semiconductor having a low impurity concentration, the source / drain region is made of a p-type semiconductor having a high impurity concentration, and the upper gate electrode is connected to the source / drain region. 2. The field effect transistor according to claim 1, wherein the field effect transistor is made of a material having a lower work function than any of the lower gates. 4. The method according to claim 1, wherein the lower gate is made of an n-type semiconductor, the channel forming region is made of an n-type semiconductor having a low impurity concentration or an intrinsic semiconductor, the source / drain region is made of an n-type semiconductor having a high impurity concentration, 3. The field effect transistor according to claim 2, wherein the upper gate electrode is made of a p-type semiconductor. 5. The semiconductor device according to claim 1, wherein the lower gate is made of a p-type semiconductor, the channel formation region is made of a p-type semiconductor having a low impurity concentration or an intrinsic semiconductor, and the source / drain region is made of a p-type semiconductor having a high impurity concentration. 4. The field effect transistor according to claim 3, wherein the upper gate electrode is made of an n-type semiconductor. 6. The field effect transistor according to claim 1, wherein said upper gate electrode is made of a single crystal semiconductor. 7. The field effect transistor according to claim 1, wherein said semiconductor layer is made of a single crystal semiconductor. 8. The apparatus according to claim 1, further comprising: means for inputting an input signal to said upper gate electrode; and means for applying a fixed voltage or a voltage that changes at a longer cycle than said input signal to said lower gate electrode. Field effect transistor. 9. The channel forming region is made of an n-type semiconductor or an intrinsic semiconductor having a low impurity concentration, the source / drain region is made of an n-type semiconductor having a high impurity concentration, and the upper gate electrode is connected to the source / drain region. 9. A voltage applying means comprising a material having a higher work function than any of the lower gates, wherein voltage applying means is provided so that the potential of the lower gate electrode is higher than the maximum potential provided to the upper gate electrode by an input signal. Field-effect transistor. 10. The channel formation region is made of a p-type semiconductor or an intrinsic semiconductor with a low impurity concentration, the source / drain region is made of a p-type semiconductor with a high impurity concentration, and the upper gate electrode is connected to the source / drain region. 9. A voltage applying means comprising a material having a lower work function than any of the lower gates, wherein the voltage applying means has a potential of the lower gate electrode lower than a lowest potential provided to the upper gate electrode by an input signal. Field-effect transistor. 11. The lower gate comprises an n-type semiconductor; the channel forming region comprises an n-type semiconductor having a low impurity concentration or an intrinsic semiconductor; the source / drain region comprises an n-type semiconductor having a high impurity concentration; 9. The field effect transistor according to claim 8, wherein the upper gate electrode is made of a p-type semiconductor, and further comprising voltage applying means for making the potential of the lower gate electrode higher than a maximum potential applied to the upper gate electrode by an input signal. 12. The lower gate is made of a p-type semiconductor, the channel formation region is made of a p-type semiconductor or an intrinsic semiconductor with a low impurity concentration, the source / drain region is made of a p-type semiconductor with a high impurity concentration, 9. The field effect transistor according to claim 8, wherein the upper gate electrode is made of an n-type semiconductor, and further comprising voltage applying means for setting a potential of the lower gate electrode lower than a lowest potential applied to the upper gate electrode by an input signal. 13. A lower insulating layer; a semiconductor layer provided on the insulating layer; a channel forming region provided in the semiconductor layer into which an n-type impurity is introduced; An n-type source / drain region having a high impurity concentration provided, and an upper insulating layer having a smaller thickness than a portion of the lower insulating layer located below the channel forming region over the channel forming region. And an upper gate electrode having both ends inside the end of the channel forming region, wherein the upper gate electrode is made of a material having a larger work function than the source / drain regions. Field effect transistor included in the semiconductor device. 14. A lower insulating layer, a semiconductor layer provided on the insulating layer, a channel forming region provided in the semiconductor layer into which a p-type impurity has been introduced, and both sides of the channel forming region. A p-type source / drain region having a high impurity concentration provided, and an upper insulating layer having a smaller thickness than a portion of the lower insulating layer located below the channel forming region over the channel forming region. And an upper gate electrode having both ends inside the end of the channel forming region, wherein the upper gate electrode is formed of a material having a smaller work function than the source / drain region. Field effect transistor included in the semiconductor device. 15. A lower insulating layer, a semiconductor layer provided on the insulating layer, two source / drain regions having a high impurity concentration provided in the semiconductor layer, and a source / drain region. A channel forming region made of a material having a band gap smaller than that of the source / drain region; and an upper portion having a lower film thickness than a portion of the lower insulating layer located below the channel forming region on the channel forming region. A field-effect transistor having an upper gate electrode provided on a substrate, the upper gate electrode being provided with an insulating layer therebetween and having both ends inside the end of a channel formation region. 16. A semiconductor layer, a lower insulating layer below the semiconductor layer and having charges embedded near an interface with the semiconductor layer, and a channel with a low impurity concentration provided in the semiconductor layer. A formation region or a channel formation region made of an intrinsic semiconductor; a first conductivity type source / drain region having a high impurity concentration provided on both sides of the channel formation region; and a lower insulating layer on the channel formation region A field effect type having, on a substrate, an upper gate electrode provided with an upper insulating layer thinner than a portion located below the channel formation region and having both ends inside the channel formation region. Transistor. 17. A semiconductor layer, a lower insulating layer below and at least part of which is made of a ferroelectric material, a lower electrode provided below the lower insulating layer, A channel formation region having a low impurity concentration or a channel formation region made of an intrinsic semiconductor, a first conductivity type source / drain region having a high impurity concentration provided on both sides of the channel formation region; An upper gate electrode provided on the region via an upper insulating layer having a smaller thickness than a portion of the lower insulating layer located below the channel forming region, and having both ends inside the channel forming region; A field-effect transistor having a substrate and a substrate. 18. A step of forming a gate insulating layer on a single crystal semiconductor, forming an opening in the gate insulating layer, and growing the single crystal semiconductor in a lateral direction on the gate insulating layer by selective epitaxial growth from the opening. Patterning the grown single-crystal semiconductor to form a gate electrode made of the single-crystal semiconductor at a position away from the opening; using the obtained gate electrode as a mask, a source / drain electrode Forming a source / drain region by ion-implanting or diffusing an impurity at a formation position. 19. A step of forming a gate insulating layer on a single crystal semiconductor, providing an opening in the gate insulating layer, and growing the single crystal semiconductor in a lateral direction on the gate insulating layer by selective epitaxial growth from the opening. A step of patterning the grown single-crystal semiconductor to form a gate electrode made of the single-crystal semiconductor at a position distant from the opening; and depositing an insulating film over the whole and etching back the same. Providing a side wall made of an insulating film on the side surface of the gate electrode, using the obtained gate electrode and side wall as a mask, ion-implanting or diffusing impurities, or epitaxially growing a semiconductor layer containing the impurity, or Forming a source / drain region by depositing the same. 20. A step of forming a gate insulating layer on a single crystal semiconductor, a step of providing an opening in the gate insulating layer, depositing an amorphous semiconductor on the gate insulating layer, and performing solid phase epitaxial growth from the opening. Growing a single crystal semiconductor in a lateral direction, patterning the grown single crystal semiconductor, and forming a gate electrode made of the single crystal semiconductor at a position away from the opening; Or forming a source / drain region by epitaxially growing or depositing a semiconductor layer containing impurities. 21. A step of forming a gate insulating layer on a single crystal semiconductor; a step of depositing an amorphous semiconductor on the gate insulating film; and a step of providing an opening in the gate insulating film and the amorphous semiconductor. A step of filling a second amorphous semiconductor by depositing the same, a step of laterally growing a single crystal semiconductor by solid phase epitaxial growth from the opening, and a step of patterning the grown single crystal silicon, and A step of forming a gate electrode made of a single crystal semiconductor at a remote position; and a step of forming source / drain regions by ion-implanting and diffusing impurities or by epitaxially growing or depositing a semiconductor layer containing impurities. A method for manufacturing a field-effect transistor, comprising: 22. A semiconductor substrate or a lower gate electrode of a predetermined shape formed on the semiconductor substrate, a lower insulating layer made of an insulating film formed on the lower gate electrode, and formed on the lower insulating layer. S consisting of a single crystal semiconductor
Forming an upper gate insulating layer on the OI layer; providing an opening in the upper gate insulating layer; and selectively growing epitaxially from the opening to grow a single crystal semiconductor in a lateral direction on the upper gate insulating layer. Patterning the grown single crystal semiconductor to form an upper gate electrode made of the single crystal semiconductor at a position away from the opening; forming source / drain electrodes using the obtained upper gate electrode as a mask Forming a source / drain region by ion-implanting or diffusing an impurity into a position. 23. A semiconductor substrate or a lower gate electrode of a predetermined shape formed on the semiconductor substrate, a lower insulating layer made of an insulating film formed on the lower gate electrode, and formed on the lower insulating layer. S consisting of a single crystal semiconductor
Forming an upper gate insulating layer on the OI layer; providing an opening in the upper gate insulating layer; and selectively growing epitaxially from the opening to grow a single crystal semiconductor in a lateral direction on the upper gate insulating layer. Patterning the grown single-crystal semiconductor to form an upper gate electrode made of the single-crystal semiconductor at a position away from the opening; depositing an insulating film over the entire surface and etching back the same to form an upper portion; Providing a side wall made of an insulating film on the side surface of the gate electrode, and ion-implanting impurities using the obtained upper gate electrode and side wall as a mask, or using the obtained upper gate electrode as a mask,
Forming source / drain regions by diffusing or epitaxially growing or depositing a semiconductor layer containing impurities. 24. A semiconductor substrate or a lower gate electrode having a predetermined shape formed on the semiconductor substrate, a lower insulating layer formed of an insulating film formed on the lower gate electrode, and formed on the lower insulating layer. S consisting of a single crystal semiconductor
Forming an upper gate insulating layer on the OI layer; providing an opening in the upper gate insulating layer; depositing an amorphous semiconductor on the upper gate insulating layer; Laterally growing, patterning the grown single crystal semiconductor to form an upper gate electrode made of a single crystal semiconductor at a position away from the opening, and ion-implanting and diffusing impurities or Forming a source / drain region by epitaxially growing or depositing a semiconductor layer containing: 25. A semiconductor substrate or a lower gate electrode of a predetermined shape formed on the semiconductor substrate, a lower insulating layer made of an insulating film formed on the lower gate electrode, and formed on the lower insulating layer. S consisting of a single crystal semiconductor
Forming an upper gate insulating layer on the OI layer; depositing an amorphous semiconductor on the upper gate insulating film; providing an opening in the upper gate insulating film and the amorphous semiconductor; A step of filling the second amorphous semiconductor by depositing it, a step of growing a single crystal semiconductor in a lateral direction from the opening by solid phase epitaxial growth, and a step of patterning the grown single crystal silicon to a position away from the opening. Forming an upper gate electrode made of a single crystal semiconductor, and implanting and diffusing impurities, or epitaxially growing or depositing a semiconductor layer containing impurities to form source / drain regions. Method for manufacturing a field-effect transistor having the same.