JPH11146196A - Device and method for processing image data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process image data with a small capacity memory by deviating an address of a filter-processed second image data with respect to a first image stored in a frame memory in writing. SOLUTION: A frame memory is a DRAM and its address is specified by a column address CA and a low address RA. Original image data 15R is read out from a frame memory 3 to be filter-processed and processed data 15W is written in the same frame memory. At this time, processed data 15W is deviated to left by the amount of one pixel (by reducing a column address by one address) compared with original image data and written. Thereby, processed data 15W can be written in the frame memory without erasing original image data required for filter processing. Compared with the case of preparing two frame memories for first/second image data, only one frame memory and a buffer of a small capacity are required to be prepared.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to image processing.
Particularly, the present invention relates to a technique for processing digital image data.

[0002]

2. Description of the Related Art FIG. 2A shows a memory in which two-dimensional digital image data is stored. The two-dimensional image is composed of two-dimensionally arranged pixels. FIG.
(A) shows pixel values arranged two-dimensionally. For example, in order to remove noise from an image, the image may be low-pass filtered using a 3 × 3 filter 11.
The pixel b2 is located at the center of the filter 11 and is a target pixel of the low-pass filter processing. The pixel b2 is filtered, for example, by the following equation, and is converted into a new pixel b2 '.

B2 '= (1/2) .times.b2 + (1/8) .times.
a2 + (1/8) × b1 + (1/8) × c2 + (1 /
8) × b3

[0004] As shown in FIG. 2B, it is assumed that the original pixel b2 is replaced with a new pixel b2 'and written into the memory.
Next, as shown in FIG.
It is assumed that the pixel b3 is shifted by the amount of the pixel and subjected to the filtering process. The pixel b3 is filtered by the following equation, and is converted into a new pixel b3 '.

B3 '= (1/2) × b3 + (1/8) ×
a3 + (1/8) × b2 + (1/8) × c3 + (1 /
8) × b4

However, since the pixel b2 is replaced by b2 ', a new pixel b3' cannot be obtained by the above equation. When the filter processing is performed with b2 'as b2, the original weight of b2 is reduced to 1/2 in the above equation, and the effects of a2, b1, and c2 that should not be considered are taken in. That is, the intended filtering cannot be performed.
In order to determine the correct pixel b3 ', it is necessary to leave the original pixel b2.

If a memory for storing the filtered image is prepared separately from the memory for storing the original image,
The above problems can be solved. If two frame memories are prepared to store two images before and after the filtering process, a large-capacity memory is required. Providing a large-capacity memory increases costs and increases the size of the image data processing device.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image data processing apparatus or an image data processing method capable of processing image data with a small-capacity memory.

Another object of the present invention is to provide an image data processing apparatus or an image data processing method capable of processing image data at a high speed with a small-capacity memory.

[0010]

According to one aspect of the present invention, a frame memory capable of storing one frame of image data composed of a plurality of pixels by specifying an address, and a buffer for buffering the image data Filtering means for filtering the image data in the buffer, reading the first image data stored in the frame memory, buffering the first image data in the buffer, and filtering the first image data in the buffer. A memory controller that writes the second image data into the frame memory with a shifted address for a corresponding pixel of the first image data.

The first image data is stored in the frame memory. The memory controller reads the first image data from the frame memory and buffers the first image data in a buffer. The filter processing means includes:
Is subjected to a filtering process to generate second image data. The memory controller writes the second image data to the frame memory while shifting the address with respect to the corresponding pixel of the first image data. By writing the second image data while shifting the address, the first image data required for the filtering process does not need to be erased.

According to another aspect of the present invention, (a) reading out the first image data stored in the frame memory; and (b) filtering the first image data to obtain a second image data. Generating image data; and (c) generating the second image data.
And writing the image data in the frame memory to the corresponding pixels of the first image data at shifted addresses.

[0013]

FIG. 1 is a block diagram showing a configuration of an image data processing apparatus according to an embodiment of the present invention.

The video source 1 is, for example, a solid-state image sensor (CCD camera) or a semiconductor memory (DRAM or the like). The video source 1 supplies the image data DT1 to the control unit 2. The control unit 2 has a memory controller 2a and a filter processing unit 2b.

The memory controller 2a can read from and write to both the frame memory 3 and the buffer 4. The frame memory 3 is, for example, a DR
AM, which can store one frame of image. The buffer 4 is, for example, an SRAM and can store image data of 10 × 3 pixels.

The mode signal MD will be described. Mode signal M
When D enters the original image writing mode, the memory controller 2 a receives the original image data DT 1 from the video source 1 and writes it to the frame memory 3.

The following mode is a mode in which an image is divided into a plurality of blocks, and processing is performed in block units.

When the mode signal MD enters the original image reading mode, the memory controller 2a
1 block of original image data from the buffer 4
Write to.

Next, when the mode signal MD is set to the filter processing mode, the filter processing unit 2b performs filter processing such as a low-pass filter and contour enhancement on the original image data stored in the buffer 4.

Next, when the mode signal MD is set to the processing data write mode, the filtered processing data is written back to the frame memory 3. At this time, erasure of necessary original image data is prevented by writing the processing data with the address shifted to the upstream side in the reading order with respect to the original image data. Details will be described later.

The above series of processing is processing for one block. By performing the above processing for all the blocks, the processing of the image of one frame is completed.

When the mode signal MD is set to the processing data read mode, the memory controller 2a reads one frame of processing data from the frame memory 3 and outputs it as image data DT2 to the outside. The image data DT2 is
For example, it is displayed on a monitor.

FIG. 3 shows the address positions of the original image data 15R and the processing data 15W stored in the frame memory 3. The frame memory 3 is a DRAM, and an address is specified by a column address CA and a row address RA. The original image data 15R is read from the frame memory 3 and subjected to a filtering process, so that the processed data 15W
Is generated. The processing data 15W is stored in the frame memory 3
Is written to. At this time, the processing data 15W is written by shifting one pixel to the left (reducing the column address by one address) compared to the original image data 15R. As a result, the processed data 15W can be written to the frame memory 3 without erasing the original image data necessary for the filter processing. Next, the details will be described.

FIG. 4 shows the frame memory 3 in which original image data is stored. The original image is, for example, 640 × 48
It has 0 pixels. The original image data is read from the frame memory 3 with 10 × 1 pixel as one unit.

The first to tenth pixels from the left end of the original image data (column addresses 0 to 9) are defined as the first column. The first column includes 10 pixels a1 to a10 (A1) in the first row (row address 0), 10 pixels b1 to b10 (B1) in the second row (row address 1), and the third row. 10 pixels c1 to c10 (C1), 10 pixels d1 to d10 (D1) in the fourth row, 10 pixels e1 to e1 in the fifth row
0 (E1).

The ninth to eighteenth leftmost pixels (column addresses 8 to 17) of the original image data are defined as the second column. The second column is composed of 10 pixels a9 to a1 in the first row.
8 (A2), 10 pixels b9 to b18 (B
2), 10 pixels c9 to c18 (C2) in the third row, fourth pixel
10 pixels d9 to d18 (D2) in the row, 10 pixels d5 to d18 in the fifth row
It has pixels e9 to e18 (E2).

FIG. 5 is a timing chart showing the processing of the first column of image data. At time t1, the image data A1 in the first row is read from the frame memory 3, and
At time t2, the image data A1 is written into the buffer 4 (FIG. 6A). Next, at time t3, the image data B1 of the second row is read from the frame memory 3, and at time t4, the image data B1 is written into the buffer 4 (FIG. 6A). Next, at time t5, the third line of image data C1 is read from the frame memory 3, and at time t6, the image data C1 is written into the buffer 4 (FIG. 6A). As shown in FIG. 6A, the buffer 4 has a capacity of 10 × 3 and stores image data A1, B1, and C1.

As described above, the image data A1, B1, C
1 are sequentially read from the frame memory 3. Each of the image data A1, B1, and C1 is 10 × 1 pixel, and is stored over 10 column addresses at the same row address. Since each of the image data A1, B1, and C1 is stored at the same row address, each image data can be read from the frame memory (DRAM) 3 in the high-speed page mode. That is, image data can be read at high speed by fixing the row address of the DRAM and designating only the column address.

Next, at time t7 in FIG. 5, processing data B1 'is obtained as follows. As shown in FIG. 6B, filter processing is performed using a 3 × 3 filter 11. The filter 11 corresponds to the leftmost 3 × 3 pixels of the image data stored in the buffer 4.

Using the filter 11, filter processing such as a low-pass filter and contour enhancement can be performed. For example, low-pass filtering is performed to remove noise from the image. The pixel b2 is located at the center of the filter 11,
This is the target pixel of the low-pass filter processing. Pixel b2 is
For example, a filtering process is performed by the following equation, and the pixel is converted into a new pixel b2 ′ shown in FIG.

B2 '= (1/2) × b2 + (1/8) ×
a2 + (1/8) × b1 + (1/8) × c2 + (1 /
8) × b3

The same filter processing is performed, and pixels b3 to b3
New pixels b3 ′ to b9 ′ corresponding to 9 are obtained. FIG.
As shown in (D), processing data b2 'to b of eight pixels
9 ′ (B1 ′) is obtained. The processing data B1 'is temporarily stored in a register or a buffer.

Next, as shown in FIG. 5, at time t8, the processing data B1 'is written into the frame memory 3. As shown in FIG. 7, the processing data B1 ′ in the second row
Are written one pixel to the left compared to the original image data b2 to b9 (with the column address reduced by one address). The processing data B1 ′ is written in units of 8 × 1 pixels.

By writing the processing data B1 'shifted to the left, the original image data required for the subsequent filtering process does not need to be erased. For example, if the processing data B1 'is written without shifting, the new pixel b9' is overwritten on the original pixel b9, and the original pixel b9 is erased. However, since the original pixel b9 is a pixel necessary for obtaining the new pixel b10 ', it must be left. As described above, the original data b
9 can be left.

The processing data B1 'has 8 × 1 pixels and is written over eight column addresses at the same row address. Process data B1 'of 8 pixels
Is written to the same row address, and can be written to the frame memory (DRAM) 3 in the high-speed page mode. That is, processing data can be written at high speed by fixing the row address of the DRAM and designating only the column address.

Next, as shown in FIG. 5, at time t9, the fourth row of the original image data D1 is read from the frame memory 3.
And at time t10, the image data D1
Is written into the buffer 4 (FIG. 8A). The buffer 4 stores original image data B1, C1, and D1.

Next, at time t11 in FIG. 5, processing data C1 'is obtained as follows. Filtering is performed using a 3 × 3 filter 11 shown in FIG.
A new pixel c2 'shown in FIG. 8C is obtained. Pixel c
2 ′ is obtained by the following equation using the filter 11.

C2 '= (1/2) .times.c2 + (1/8) .times.
b2 + (1/8) × c1 + (1/8) × d2 + (1 /
8) xc3

The same filter processing is performed, and pixels c3 to c3
9, new pixels c3 ′ to c9 ′ are obtained. FIG.
As shown in (D), the processing data c2 ′ to c of eight pixels
9 ′ (C1 ′) is obtained.

Next, as shown in FIG. 5, at time t12, the processing data C1 'in the third row is written into the frame memory 3. As shown in FIG. 9, the processing data C1 'in the third row is written one pixel to the left (with the column address reduced by one address) compared to the original image data c2 to c9.

Next, as shown in FIG. 5, at time t13, the fifth row of image data E1 from the frame memory 3 is read.
And at time t14, the image data E1
Is written to the buffer 4. The buffer 4 stores the original image data C1, D1, and E1.

Next, at time t15, the processing data D1 'in the fourth row is obtained using a 3 × 3 filter. Next, at time t16, the processing data D1 ′ of the fourth row is written in the frame memory 3 (FIG. 9). Similarly, the processing data E1 'of the fifth row and the processing data of the subsequent rows are written into the frame memory 3 (FIG. 9). All of the processed data in the first column is written to the frame memory 3 with a shift of one pixel to the left (with the column address reduced by one address) compared to the original image data.

Thus, the processing of the image data in the first column is completed. Next, the image data of the second column is processed.

FIG. 10 is a timing chart showing the processing of the image data in the second column. At time t1, the first line of image data A2 is read from the frame memory 3, and at time t2, the image data A2 is written to the buffer 4 (FIG. 11A). Next, at time t3, the image data B2 in the second row is read from the frame memory 3, and at time t4, the image data B2 is written into the buffer 4 (FIG. 11A). Next, at time t5
, The third line of image data C2 is read from the frame memory 3 and at time t6,
2 is written into the buffer 4 (FIG. 11A).

Each of the image data A2, B2 and C2 is 10 ×
Since one pixel is stored at the same row address, the frame memory (DRA) is set in the high-speed page mode.
M) Each image data can be read from 3.

Next, at time t7, filter processing is performed to obtain processing data B2 '. The processing of the 3 × 3 filter 11 shown in FIG. 11B is performed to obtain a new pixel b10 ′ shown in FIG. 11C. The pixel b10 'is obtained by the following equation using the filter 11.

B10 '= (1/2) × b10 + (1 /
8) x a10 + (1/8) x b9 + (1/8) x c10
+ (1/8) × b11

The same filtering process is performed to obtain the pixels b11 to b11.
New pixels b11 'to b17' are obtained based on b17. As shown in FIG. 11D, the processing data b of eight pixels
10 ′ to b17 ′ (B2 ′) are obtained.

Next, as shown in FIG. 10, at time t8, the processing data B2 'is written into the frame memory 3. As shown in FIG. 12, the processing data B in the second row
2 ′ is written one pixel to the left as compared to the original image data b10 to b17 (with the column address reduced by one address).

The processing data B 2 ′ is 8 × 1 pixels and is written to the same row address, so that it can be written to the frame memory (DRAM) 3 in the high-speed page mode.

Next, as shown in FIG. 10, at time t9, the fourth row of the original image data D
2 and at time t10, the image data D
Write 2 to buffer 4. The buffer 4 stores the original image data B2, C2, D2.

Next, at time t11, the processing data C2 'in the third row is obtained using a 3 × 3 filter. Next, at time t12, the processing data C2 ′ in the third row is written in the frame memory 3 (FIG. 12).

Similarly, the processing data D2 'in the fourth row
Then, the processing data of the subsequent rows are written in the frame memory 3 (FIG. 12). All of the processed data is shifted to the left by one pixel compared to the original image data (the column address is set to 1
The data is written into the frame memory 3 (only the address is reduced).

Thus, the processing of the image data in the second column is completed. Subsequently, the processing of the image data from the third column to the last column is performed, and the processing of the image data for one frame is completed. The frame memory 3 stores the processed data for one frame subjected to the filter processing.

In the above embodiment, the image data A1, A2
The case where the image data of the frame periphery such as is not filtered is described. Original image data of 642 × 482 pixels is prepared in advance, and the filter processing is performed.
Only processing data of 40 × 480 pixels can be output to the outside.

FIGS. 13A and 13B are diagrams for explaining an example of a method of performing a filtering process on image data at the frame periphery.

FIG. 13A is a diagram showing the buffer 4. The buffer 4 stores original image data 22 and copy data 21. The original image data 22 corresponds to the data A1 and B1 in FIG. 4 and is data read from the frame memory 3. The copy data 21 is the original image data 2
2 is a copy of the data.

FIG. 13B shows processing data A1 'obtained based on the buffer 4 shown in FIG. 13A. By performing a filtering process based on the buffer 4, processing data A1 'at the frame periphery is obtained. The processing data A1 'has eight pixels a1' to a8 '. Then, process data A
1 'may be written to the frame memory 3 with the address shifted. For example, pixels a1 to a8 have column addresses 1 to 9
The pixels a1 'to a8' are stored at column addresses 0 to 7, respectively.

According to the present embodiment, the original image data is subjected to the filter processing to generate the processed data. By writing the processed data to the frame memory by shifting it to the left by one pixel with respect to the original image data, it is possible to write the processed data to the same frame memory as the original image data without erasing necessary original image data. .

In this embodiment, one frame of image data is divided into a plurality of overlapping column address areas and sequentially read from left to right. In that case, the above-described processed data is written to the frame memory while being shifted one pixel to the left with respect to the original image data. That is, writing is performed by shifting one pixel upstream in the reading order.

When the original image data and the processed data are stored in different frame memories, two frame memories are required and a large memory capacity is required. According to the present embodiment, since only one frame memory and a small-capacity buffer need be prepared, the memory capacity can be reduced. The cost and the size of the image data processing device can be reduced.

In this embodiment, the case where the processing data is written to the frame memory by shifting by one pixel has been described.
It may be written by shifting by more than a pixel. The number of pixels to be shifted is
Depends on filter size. In the case of performing 3 × 3 filter processing, it is only necessary to shift by one pixel or more. In the case of performing nxn filter processing, it is sufficient to shift by (n-1) / 2 pixels or more. The filtering process is not limited to the two-dimensional filter, but is effective when a two-dimensional filter is used.

The capacity of the buffer 4 is not limited to 3 × 10. When performing 3 × 3 filtering, a buffer having a capacity of 3 × 3 or more may be prepared. When performing n × n filtering, a buffer having a capacity of n × n or more may be prepared.

The capacity of the buffer is determined depending on whether importance is placed on cost, size of the apparatus, or speeding up. If the buffer capacity is reduced, cost reduction and downsizing of the image data processing device can be realized. However,
When the buffer capacity is reduced, the number of accesses to the frame memory 3 and the buffer 4 increases. As shown in FIG. 4, data A1 and data A2 have an overlap of two pixels. The two pixels are read from the frame memory 4 twice. If the buffer capacity becomes small, the number of accesses to the frame memory 3 and the buffer 4 increases, and the processing time becomes slow.

If low cost or downsizing of the apparatus is emphasized, the buffer capacity may be reduced. If emphasis is placed on high-speed processing, the buffer capacity may be increased. As in the present embodiment, setting the buffer capacity to 8 × 3 is appropriate in consideration of all of the cost, the size of the device, and the speeding up.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0067]

As described above, according to the present invention,
Since the memory controller writes the filtered second image data to the frame memory while shifting the address with respect to the corresponding pixel of the first image data, the memory controller does not erase the first image data necessary for the filter processing. I'm sorry.

According to the present invention, only one frame memory and a small-capacity buffer are prepared, as compared with the case where two frame memories are prepared for separately storing the first and second image data. Therefore, the memory capacity can be reduced. By reducing the memory capacity, the cost and size of the image data processing device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image data processing device according to an embodiment of the present invention.

FIGS. 2A to 2C are diagrams showing problems when filtering image data. FIG.

FIG. 3 is a diagram showing address positions of original image data and processing data stored in a frame memory.

FIG. 4 is a diagram showing a frame memory in which original image data is stored.

FIG. 5 is a timing chart illustrating processing of image data in a first column.

6A shows a buffer, FIGS. 6B and 6C show filters, and FIG. 6D shows processing data.

FIG. 7 is a diagram showing a frame memory in which processing data of a second row is written.

8A shows a buffer, FIGS. 8B and 8C show a filter, and FIG. 8D shows processed data.

FIG. 9 is a diagram showing a frame memory in which all processing data in a first column is written.

FIG. 10 is a timing chart illustrating processing of image data in a second column.

FIG. 11A shows a buffer, and FIG.
FIGS. 11B and 11C show filters, and FIG. 11D shows processing data.

FIG. 12 is a diagram showing a frame memory in which all processing data in the first and second columns are written.

FIG. 13A shows a buffer, and FIG.
(B) is a diagram showing processing data.

[Explanation of symbols]

 Reference Signs List 1 video source 2 control unit 2a memory controller 2b filter processing unit 3 frame memory 4 buffer 11 filter 15R original image data 15W processed data 21 copy data 22 original image data MD mode signal DT image data

Claims (8)

[Claims] 1. An image processing system comprising a plurality of pixels by addressing.
A frame memory capable of storing image data of a frame, a buffer for buffering the image data, a filter processing unit for filtering the image data in the buffer, and stored in the frame memory. The first image data is read out, buffered in the buffer, and the address of the second image data filtered by the filter processing means is shifted to the frame memory with respect to a corresponding pixel of the first image data. An image data processing device having a memory controller for writing data. 2. The frame memory is a DRAM addressed by a row address and a column address.
2. The image data processing device according to claim 1, wherein the memory controller writes the second image data with a column address shifted from the first image data. 3. The image data processing apparatus according to claim 2, wherein said memory controller reads out said first image data in a plurality of overlapping column address areas. 4. The memory controller according to claim 1, wherein said memory controller reads said first image data separately for each row address in said column address area and writes said second image data for each row address in said column address area. 3. The image data processing device according to 3. 5. A step of reading out the first image data stored in the frame memory, and a step of generating a second image data by filtering the first image data. (C) writing the second image data to the frame memory with a shifted address for a corresponding pixel of the first image data. 6. The frame memory is a DRAM addressed by a row address and a column address. In the step (c), the second image data is written with the column address shifted from the first image data. Claim 5
The image data processing method described in the above. 7. The image data processing method according to claim 6, wherein in said step (a), said first image data is read out in a plurality of overlapping column address areas. 8. In the step (a), the first image data is read out for each row address in each of the column address areas, and in the step (c), the second image data is read out of each of the column addresses. 8. The image data processing method according to claim 7, wherein writing is performed for each row address in the area.