JP2006195134A - Device and method for processing video signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and method for processing a video signal capable of performing right-left inversion processing of the video signal with a single line memory. <P>SOLUTION: The video signal processing device is provided with a line memory 1 and a memory control means 2 which controls the line memory 1 so as to invert the video signal right-left by alternately switching line by line between the ascending order and the descending order of addresses written in the line memory 1 in performing right-left inversion processing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video signal processing apparatus and a video signal processing method for performing left / right inversion processing of a video signal using a line memory.

  Conventionally, in order to perform left / right inversion processing of a video signal, writing and reading are alternately performed using two line memories (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 10-322571

By the way, in the above conventional technique, since writing and reading are alternately performed using two line memories, at least two line memories are necessary to perform the left / right inversion processing of one system of video signals. There is room for further improvement in the case where the video signal is horizontally reversed by one line memory.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a video signal processing apparatus and a video signal processing method capable of performing left-right inversion processing of a video signal with one line memory.

  In order to achieve the above object, a video signal processing apparatus according to the present invention stores a video signal for each line and receives a line memory capable of writing and reading data and a write address for the line memory. For each line of the video signal, the first order and the second order, which is the reverse order of the first order, are alternately switched, and after the writing for each line, to the line memory. And a memory control means for controlling the line memory so that the read addresses are in the order opposite to the order of the write addresses.

  With this configuration, writing and reading can be performed at the same time in the same line memory.

  In the video signal processing apparatus, the memory control means performs the write operation of the line memory when the sampling frequency of the input and output of the video signal is designated as the first sampling frequency and the second sampling frequency, respectively. It is preferable that the line memory is controlled to perform at the first sampling frequency and perform the read operation of the line memory at the second sampling frequency.

  In addition, the present invention can provide a camera device including the video signal processing device. According to such a camera device, a horizontally reversed image can be output.

  In addition, the present invention can provide a vehicle surrounding monitoring apparatus including the video signal processing apparatus. According to such a vehicle surrounding monitoring apparatus, it is possible to execute the left / right reversal processing of the video signal by one line memory, for example, a camera is installed at the rear of the vehicle, and the same direction as the video reflected in the room mirror on the display Can be displayed.

  In order to achieve the above object, a video signal processing method according to the present invention is a video signal processing method in which a video signal is stored in a line memory line by line, and data can be written and read simultaneously. For each line of the input video signal, the write address to the line memory is alternately switched between the first order and the second order, which is the reverse order of the first order, and the one line After each writing, the line memory is controlled by setting the read address to the line memory as the reverse order of the write address.

  According to this video signal processing method, the video signal can be written and read by the same line memory.

  In the video signal processing method, when the sampling frequency of the input and output of the video signal is designated as the first sampling frequency and the second sampling frequency, respectively, the write operation of the line memory is performed as the first sampling frequency. Preferably, the line memory is controlled so that the read operation of the line memory is performed at the second sampling frequency.

  ADVANTAGE OF THE INVENTION According to this invention, the video signal processing apparatus and video signal processing method which can perform the horizontal inversion process of a video signal with one line memory can be provided.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a video signal processing apparatus according to the present invention.
In FIG. 1, a line memory 1 is a memory having a capacity for storing one line of a video signal, and is a dual port memory capable of independently performing write control and read control.

  The memory control unit 2 generates control signals such as a write address, a read address, and a write enable signal for the line memory 1.

  The line counter 3 counts the number of lines of the video signal from the top line using the horizontal synchronization signal and the vertical synchronization signal synchronized with the video input, and notifies the memory control means 2 of the counted value.

  Next, operations of the video signal processing apparatus and the video signal processing method of the present embodiment will be described. FIG. 2 is a timing chart showing the operation of the video signal processing apparatus according to the embodiment of the present invention.

  In FIG. 2, the horizontal synchronization signal S1 indicates the horizontal timing of video input. Here, a period of L (Low) level represents an effective pixel period.

  The write enable S2 indicates a period during which writing to the line memory 1 is performed. Here, writing is performed during a period of H (High) level.

  The write address S3 indicates an address for writing to the line memory 1.

  The read address S4 indicates an address for reading from the line memory 1.

  The memory control means 2 makes the write enable signal valid (here, H level) during the period when the horizontal synchronization signal S1 is at L level, that is, the effective pixel period of video input, and sets the write address S3 from the head address for each pixel. Increase or decrease from the last address. In the present invention, an array in which the write address S3 is increased from the head address for each pixel is referred to as ascending order, and an array in which the write address S3 is decreased from the head address for each pixel is referred to as descending order. Note that the memory control unit 2 may control a period for reading the read address S4 based on the read enable signal using a read enable signal (not shown).

  After writing the write address S3, the memory control means 2 disables the write enable signal (here, L level) outside the period when the horizontal synchronizing signal S1 is at H level, that is, outside the effective pixel period of the video input, and also reads out the read address S4. Is decreased from the last address or increased from the top address for each pixel.

  In order to invert the video horizontally, it is only necessary to store the video signal in each line memory in the line memory, and to read out from the line memory by alternately switching the order of writing for each line in reverse order.

Next, an example in which an image of 768 pixels per line is reversed horizontally will be described.
First, in writing for the first line, the video signal for one line is stored in the line memory by increasing the write address S3 in ascending order from 0 to 767.

  Thereafter, the read address S4 is decreased from the final address 767 in descending order to perform read-out to 0 in order to perform left-right reversal. Here, the reading from the line memory 1 is not completed during the period when the horizontal synchronization signal S1 is at the H level, that is, the horizontal blank period of the video input, and extends over the effective period of the video input of the next line. When performing left / right reversal processing with one line memory, it is necessary to read the first line and write the second line in parallel.

  Assuming that the write address S3 for the second line is written from 0 to 767 in ascending order as in the first line, the second line video is overwritten on the first line video that has not yet been read. Results in inconvenience. In order to avoid this, in this embodiment, if the write address S3 of the first line is in ascending order, the write address S3 of the second line is decreased from the final address 767 of the line memory 1 in descending order to 0. Write.

  Then, even when only one line memory is used, among the video signals of the first line stored in the line memory 1, the video signal of the second line is not overwritten with the video signal of the address that has not yet been read. Can write. By controlling the read address S4 of the second line after the completion of writing of the second line in the ascending order that is the reverse order of the writing, the left-right inversion process is performed without any problem. The processing after the third line is repeated in the same manner.

  Summarizing the above operations, the memory control unit 2 receives information on the number of lines in the current process from the line counter 3, and increases the write address S3 and the read address S4 in ascending order from the top address depending on whether it is an even number or an odd number. Alternatively, control is performed alternately to decrease in descending order from the last address. The line counter 3 initializes the counter value in synchronization with the rising edge or falling edge of the vertical synchronization signal.

  In the above description, the write address S3 of the first line is controlled to be in ascending order. However, the write address S3 can be controlled to be in descending order by the same operation procedure.

  Further, the memory control means 2 can simultaneously perform left-right reversal and rate conversion by changing the change cycle of the write address S3 and the read address S4. If the read speed is faster, the above description applies as it is. Can be implemented. Further, even when the read speed is slower than the write speed, the above explanation is applicable if the read address S4 of one line does not catch up with the write address S3 of the next line. It is. For example, as shown in FIG. 2, if the read speed is set too low than the write speed, the final address of the read address becomes the first address of the write address to be written on the next line (two lines in FIG. 2). Duplicate and overwritten. For this reason, the memory control unit 2 converts the speed difference between the writing speed and the reading speed so that overwriting does not occur.

  The video signal processing apparatus according to the present invention can perform the left / right inversion processing of the video signal with one line memory, which is useful for reducing the circuit scale of an integrated circuit.

It is a block diagram which shows embodiment of the video signal processing apparatus which concerns on this invention. It is a timing diagram which shows operation | movement of the video signal processing apparatus and video signal processing method concerning this invention.

Explanation of symbols

1 line memory 2 memory control means 3 line counter S1 horizontal synchronization signal S2 write enable S3 write address S4 read address

Claims (6)

A line memory for storing video signals for each line and writing and reading data;
The write address to the line memory is alternately switched between a first order and a second order that is the reverse order of the first order for each line of the input video signal, A video signal processing apparatus comprising: a memory control unit configured to control the line memory by setting a read address to the line memory in an order opposite to the order of the write address after writing for each line. The video signal processing apparatus according to claim 1,
The memory control means performs the write operation of the line memory at the first sampling frequency when the sampling frequency of the input and output of the video signal is designated as the first sampling frequency and the second sampling frequency, respectively. And a video signal processing device that controls the line memory so that the read operation of the line memory is performed at the second sampling frequency.   A camera apparatus comprising the video signal processing apparatus according to claim 1.   A vehicle surroundings monitoring device comprising the video signal processing device according to claim 1. A video signal processing method in which video signals are stored in a line memory for each line, and data can be written and read.
The write address to the line memory is alternately switched between a first order and a second order that is the reverse order of the first order for each line of the input video signal, A video signal processing method of controlling the line memory by setting a read address to the line memory as an order opposite to the order of the write address after writing for each line. The video signal processing method according to claim 5,
When the sampling frequency of the input and output of the video signal is designated as the first sampling frequency and the second sampling frequency, respectively, the write operation of the line memory is performed at the first sampling frequency, and the line memory A video signal processing method for controlling the line memory so that the read operation is performed at the second sampling frequency.

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