JP2008192038A - Image-preprocessing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an image-preprocessing device which can be made to prevent repetition in readout from a frame memory, even when vertical scanning is carried out by each m×n block, when vertical filtering processing is carried out, and reduces the data transmission amount from the frame memory. <P>SOLUTION: The image-preprocessing device is provided with a frame memory 2, which accumulates input portion corresponding to one screen of pixel data; an (r-1) line memory 4 which accumulates pixel data for (r(a natural number larger than 1)-1) lines; a writing pixel control part 3, which determines whether the pixel data read out from the frame memory are to be written to the (r-1) line memory; a selector 5 which selects the pixel data read out from the frame memory 2 or the pixel data read out from the (r-1) line memory 4; and an r-tap vertical filtering part 6, which executes r-tap vertical filtering processing on the pixel data output from the selector 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image preprocessing apparatus capable of performing vertical filter processing without changing the transfer band of a frame memory by providing a temporary memory when performing vertical scan processing for the purpose of reducing delay of vertical filter processing. Is.

  In conventional image processing devices, a buffer memory, tap determination circuit, vertical filter, horizontal filter, etc. are provided, and the number of taps is changed when performing filter processing, and high processing speed is achieved when performing that processing. (For example, refer to Patent Document 1).

JP 2002-300197 A

  When performing vertical filter processing on pixel data of one screen on the assumption that pixel data is processed in units of m × n (m and n are natural numbers) pixel blocks in the subsequent stage of image processing, for each m × n pixel block If the vertical scanning is performed, the subsequent processing can be performed with a delay in units of pixels, so that the delay can be reduced. However, the processing of the first m × n pixel block is completed and the second processing is completed. When performing vertical filter processing of m × n blocks, there is a problem in that the reading from the frame memory overlaps with the reading of the first stage according to the number of filter taps, and the amount of data from the frame memory increases. It was.

  The present invention has been made to solve the above-described problems, and its object is to provide a temporary memory for (r-1) lines when the number of filter taps is r (natural number greater than 1). As a result, it is possible to prevent duplication in the reading of the frame memory even when the vertical filter processing is performed in the vertical scan for each m × n block, and the data transfer amount from the frame memory is reduced. An image pre-processing device that can be obtained is obtained.

  The image preprocessing device according to the present invention includes a frame memory for storing input pixel data for one screen, and a (r-1) line memory for storing pixel data for (r (natural number greater than 1) -1) lines. A write pixel control unit that controls whether or not pixel data read from the frame memory is written to the (r−1) line memory, and pixel data read from the frame memory, or the (r−1) ) A selector that selects pixel data read out from the line memory, and an r-tap vertical filter unit that performs r-tap vertical filter processing on the pixel data output from the selector.

  The image preprocessing device according to the present invention can prevent duplication in the reading of the frame memory even when the vertical filter processing is performed in the vertical scan for each m × n block. There is an effect that the amount of data transfer from can be reduced.

Embodiment 1 FIG.
An image preprocessing apparatus according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of an image preprocessing apparatus according to Embodiment 1 of the present invention. In the following, in each figure, the same reference numerals indicate the same or corresponding parts.

  1, the image preprocessing apparatus according to the first embodiment includes an input terminal 1 for inputting a pixel signal, a frame memory 2 for storing pixel data for one screen, and pixel data read from the frame memory 2 (for example, Write pixel control unit 3 for controlling whether or not to write to a line memory to be described later for each pixel), (r-1) line memory 4 for storing a part of the pixel data read from the frame memory 2, A selector 5 that selects pixel data read from the frame memory 2 or pixel data read from the (r-1) line memory 4, an r-tap vertical filter unit 6 that performs r-tap vertical filter processing, and an r-tap vertical filter unit 6 and an output terminal 7 for outputting a vertical filter pixel.

  Next, the operation of the image preprocessing apparatus according to the first embodiment will be described with reference to the drawings.

  FIG. 2 is a diagram illustrating an m × n pixel block that is a processing target of the image preprocessing device according to the first embodiment of the present invention.

  In the present embodiment, vertical filter processing is performed on the data of the m × n pixel block shown in FIG. 2 in the scan order in the vertical direction.

  FIG. 3 is a diagram showing the processing order of m × n pixel blocks in one screen of the image preprocessing device according to Embodiment 1 of the present invention.

  In FIG. 3, one screen is composed of m × n blocks of horizontal p blocks and vertical q blocks, and processing of m × n blocks is performed in the horizontal scan order from (1,1) blocks. That is, the (2, 1) block is processed after the (1, 1) block.

  In the following description, a 4 × 4 pixel block with m = n = 4 and a 3-tap vertical filter with r = 3 will be described.

  4 to 6 are diagrams for explaining the filter processing of the image preprocessing apparatus according to the first embodiment of the present invention. 4 to 6, circles represent pixels, and the numbers in the circles represent the readout order of the pixels from the memory. FIG. 4 shows the filter processing from the (1,1) block to the (p, 1) block in the first stage in FIG.

  The processing of the first (1,1) block will be described. It is necessary to pay attention to the following points when filtering the (1,1) block. First, in FIG. 4, since 4 × 4 = 16 pixels surrounded by a square are pixels in the block, the filter target pixels are 16 pixels in the square. Further, since the (1, 1) block is at the upper end of the screen, there is no pixel above this block. For this reason, for example, the filtering process is not performed on the pixels of the reading number 1, the reading number 6, the reading number 11, and the reading number 16. Further, since the r-tap vertical filter unit 6 is a 3-tap filter, three pixels centering on the target pixel are required for the filter process. In addition, pixels that are used internally are assumed to be held in the 3-tap vertical filter unit 6 and are not newly read out from the frame memory 2.

  Next, details of the filtering process will be described. First, the pixel of readout number 1 is not subjected to filter processing because it is the upper end of the screen. Next, the pixel of readout number 2 is subjected to filter processing by the r-tap vertical filter unit 6 using the pixels of readout number 1, readout number 2, and readout number 3. Subsequent pixels are processed in the same manner as the pixel with readout number 2. In the (1, 2) block in the second stage, the write pixel control unit 3 writes to the two-line memory 4 in order to use the pixels with the read number 4 and the read number 5 again.

  Subsequently, the process from the pixel with the read number 6 to the filter target pixel with the read number 19 is performed in the vertical scan order. When the processing of the (1, 1) block is finished, the write pixel control unit 3 reads the read number 4 and the read number 5 Read number 9, read number 10, read number 14, read number 15, read number 19, and read number 20 pixels are stored in the two-line memory 4.

  Following the (1,1) block, processing from the (2,1) block to the (p, 1) block is performed. At the end of processing of the (p, 1) block, the pixels of the second and fourth lines are stored in the two-line memory 4.

  Next, the processing of the second (1,2) block will be described. FIG. 5 shows the filter processing from the (1,2) block at the second stage to the (p, q-1) block at the q-1 stage in FIG.

  It is necessary to pay attention to the following points in the filter processing of (1, 2) blocks. First, in FIG. 5, 4 × 4 = 16 pixels surrounded by a square are pixels in the block, and thus the pixel to be filtered is 16 pixels in the square. Further, since the r-tap vertical filter unit 6 is a 3-tap filter, 3 pixels centered on the target pixel are required for the filter process. Also, pixels that are used internally are assumed to be held in the 3-tap vertical filter unit 6 and are not newly read from the memory.

  In FIG. 5, the pixels of read number 1, read number 2, read number 7, read number 8, read number 13, read number 14, read number 19, and read number 20 are 2 when the upper block processing is performed. The data stored in the line memory 4 is read out, and the other pixels are read out from the frame memory 2.

  Next, details of the filtering process will be described. First, the pixel of read number 2 is read by the r-tap vertical filter unit 6 using the pixels of read number 1 and read number 2 read from the two-line memory 4 and the read number 3 pixel read from the frame memory 2. Perform filtering. Next, the pixel of the reading number 3 performs the filtering process using the pixel of the reading number 2 read from the two-line memory 4 and the pixels of the reading number 3 and the reading number 4 read from the frame memory 2. In this way, the pixel read out from the 2-line memory 4 and the pixel read out from the frame memory 2 are subjected to filter processing while being selected by the selector 5. The same processing is performed for the subsequent pixels.

  In the third (1, 3) block, the pixels of read number 5 and read number 6 are used again, so that the write pixel control unit 3 writes to the two-line memory 4. At this time, since the pixels of read number 1 and read number 2 are not used again, the pixels of read number 5 and read number 6 overwrite the addresses where read number 1 and read number 2 were stored.

  Subsequently, the process from the pixel with the read number 8 to the filter target pixel with the read number 23 is performed in the vertical scan order. When the process of the (1, 2) block in the second stage is completed, the write pixel control unit 3 reads the read number 5 The pixels of read number 6, read number 11, read number 12, read number 17, read number 18, read number 23, and read number 24 are stored in the two-line memory 4.

  Following the (1,2) block, processing from the (2,2) block to the (p, 2) block is performed. At the end of processing of the (p, 2) block, the pixels of the second line of the eighth line and the ninth line are stored in the two-line memory 4. Similar to the above, processing from the (1,3) block to the (p, q-1) block is performed.

  Next, processing of the (1, q) block at the q-th stage that is the final stage will be described. FIG. 6 shows filter processing from the (1, q) block to the (p, q) block at the q-th stage in FIG.

  It is necessary to pay attention to the following points when filtering the (1, q) block. First, in FIG. 6, since 4 × 4 = 16 pixels surrounded by a square are pixels in the block, the filter target pixels are 16 pixels in the square. Further, since the r-tap vertical filter unit 6 is a 3-tap filter, three pixels centering on the target pixel are required for the filter process. In addition, pixels that are used internally are assumed to be held in the 3-tap vertical filter unit 6 and are not newly read out from the memory.

  In FIG. 6, pixels of readout number 1, readout number 2, readout number 6, readout number 7, readout number 11, readout number 12, readout number 16, and readout number 17 are 2 when the upper block processing is performed. The data stored in the line memory 4 is read out, and the other pixels are read out from the frame memory 2.

  Next, details of the filtering process will be described. First, the pixel of read number 2 is read by the r-tap vertical filter unit 6 using the pixels of read number 1 and read number 2 read from the two-line memory 4 and the read number 3 pixel read from the frame memory 2. Perform filtering. Next, the pixel of the reading number 3 performs the filtering process using the pixel of the reading number 2 read from the two-line memory 4 and the pixels of the reading number 3 and the reading number 4 read from the frame memory 2. In this way, the pixel read out from the 2-line memory 4 and the pixel read out from the frame memory 2 are subjected to filter processing while being selected by the selector 5. The same processing is performed for the subsequent pixels.

  Subsequently, the process from the pixel with the readout number 7 to the filter target pixel with the readout number 20 is performed in the vertical scan order. Subsequent to the (1, q) block, the processes from the (2, q) block to the (p, q) block are performed, and the processes for all the blocks are completed.

  Thus, by having the (r−1) line memory 4, it is not necessary to perform redundant reading from the frame memory 2.

  In addition, although 4x4 pixel block was demonstrated, the process of mxn pixel blocks, such as a 5x5 pixel block and a 10x10 pixel block, is possible similarly.

It is a block diagram which shows the structure of the image preprocessing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the mxn pixel block which is a process target of the image preprocessing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the process order of the mxn pixel block in 1 screen of the image pre-processing apparatus which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the filter process of the image pre-processing apparatus which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the filter process of the image pre-processing apparatus which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the filter process of the image pre-processing apparatus which concerns on Embodiment 1 of this invention.

Explanation of symbols

  1 input terminal, 2 frame memory, 3 writing pixel control unit, 4 (r-1) line memory, 5 selector, 6 r tap vertical filter unit, 7 output terminal.

Claims (2)

A frame memory for storing input pixel data for one screen;
(R (natural number greater than 1) -1) (r-1) line memory for storing pixel data for lines;
A write pixel control unit that controls whether or not pixel data read from the frame memory is written to the (r-1) line memory;
A selector for selecting pixel data read from the frame memory or pixel data read from the (r-1) line memory;
An image preprocessing apparatus comprising: an r-tap vertical filter unit that performs r-tap vertical filter processing on the pixel data output from the selector. The image preprocessing device according to claim 1, wherein the r-tap vertical filter unit processes the image data in units of m × n pixel blocks in a vertical scan order.

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