JPH11145232A - Manufacturing-process evaluating method of compound semiconductor device, and process evaluating pattern - Google Patents

Manufacturing-process evaluating method of compound semiconductor device, and process evaluating pattern

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Publication number
JPH11145232A
JPH11145232A JP30623597A JP30623597A JPH11145232A JP H11145232 A JPH11145232 A JP H11145232A JP 30623597 A JP30623597 A JP 30623597A JP 30623597 A JP30623597 A JP 30623597A JP H11145232 A JPH11145232 A JP H11145232A
Authority
JP
Japan
Prior art keywords
oxidation
manufacturing process
compound semiconductor
alas
oxidation rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30623597A
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Japanese (ja)
Other versions
JP3223865B2 (en
Inventor
Yosuke Miyoshi
陽介 三好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
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Priority to JP30623597A priority Critical patent/JP3223865B2/en
Publication of JPH11145232A publication Critical patent/JPH11145232A/en
Application granted granted Critical
Publication of JP3223865B2 publication Critical patent/JP3223865B2/en
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Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To measure simply and accurately the oxidation quantity of a compound semiconductor material, by applying the process with the same condition as its manufacturing process to a material with a faster oxidation speed than it, and by measuring the variation of the electric resistance of the material. SOLUTION: Growing epitaxially on a semi-insulating GaAs substrate 1 by an MBE method, etc., an n-type AlAs layer 2 using AlAs with a larger oxidation rate than GaAs, a protective film 3 is formed thereafter. Removing one-portions of the protective film 3 and an oxidation layer 4 by etching them, electrodes 5, 6 are formed by a lift-off method to complete a manufacture evaluating pattern. Hereupon, when denoting the thickness of the n-type AlAs layer 2 by d, the thickness of the oxidation layer 4 by X, the widths of the electrodes 5, 6 by W, and the distance between the electrodes 5, 6 by L, the value of a resistance R therebetween is represented by R=ρL/W(d-X). Measuring for AlAs previously the correlation of its electric resistance to its oxidation quantity, the electric resistance measured for an arbitrary manufacturing process is compared with the correlation to make measurable the oxidation quantity of AlAs.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
プロセスの評価方法および評価を簡便に行うための評価
パタンに関し、特に化合物半導体材料を用いた半導体装
置の製造プロセスの評価方法および評価を簡便に行うた
めの評価パタンに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a semiconductor device manufacturing process and an evaluation pattern for easily performing the evaluation, and more particularly to a method for evaluating a semiconductor device manufacturing process using a compound semiconductor material. This is related to the evaluation pattern to be performed.

【0002】[0002]

【従来の技術】ガリウムヒ素(GaAs)、及びガリウ
ムヒ素とアルミニウムヒ素(AlAs)、インジウムヒ
素(InAs)との混晶系のアルミニウムガリウムヒ素
(AlxGa1−xAs)やインジウムガリウムヒ素
(InxGa1−xAs)などの化合物半導体材料は、
シリコン(Si)に比べて電子の移動度が高いことか
ら、これらの材料を用いた電界効果型トランジスタ(F
ET)やヘテロ接合型バイポーラトランジスタ(HB
T)によるマイクロ波、ミリ波帯の高出力素子や集積回
路の研究開発が盛んである。図10(b)にはこのよう
な化合物半導体デバイスの一例として、GaAsFET
の構造を説明するための半導体チップの平面図を、また
図10(a)には図10(b)のA−A’線の断面図を
示す。図にはMESFET(Metal−Semico
nductor Field Effect Tran
sistor)型のFETを示している。図10のよう
に、GaAsFETは、半絶縁性GaAs基板1と、n
型GaAsからなる能動層15と、n型GaAsからな
るオーミックコンタクト層16と、WSiからなるゲー
ト電極17と、AuGe/Niからなるドレイン電極1
8とソース電極19と、Si02からなる保護膜20か
ら構成されている。
2. Description of the Related Art Gallium arsenide (GaAs), aluminum gallium arsenide (AlxGa1-xAs), indium gallium arsenide (InxGa1-xAs), a mixed crystal system of gallium arsenide and aluminum arsenide (AlAs), indium arsenide (InAs), etc. The compound semiconductor material of
Since the mobility of electrons is higher than that of silicon (Si), a field-effect transistor (F
ET) and heterojunction bipolar transistors (HB
Research and development of high-output devices and integrated circuits in the microwave and millimeter wave bands according to T) have been actively conducted. FIG. 10B shows a GaAs FET as an example of such a compound semiconductor device.
10A is a plan view of a semiconductor chip for explaining the structure of FIG. 10, and FIG. 10A is a cross-sectional view taken along the line AA ′ of FIG. The figure shows MESFET (Metal-Semico)
nductor Field Effect Tran
2 shows a (sistor) type FET. As shown in FIG. 10, the GaAs FET includes a semi-insulating GaAs substrate 1 and n
Active layer 15 of n-type GaAs, ohmic contact layer 16 of n-type GaAs, gate electrode 17 of WSi, and drain electrode 1 of AuGe / Ni
8, a source electrode 19, and a protective film 20 made of Si02.

【0003】これらの化合物半導体デバイスでは、半導
体表面の保護膜として、Si02やSiNxやポリイミ
ドなどの絶縁膜が用いられており、素子能動部において
絶縁膜/半導体界面を形成している。このような保護膜
界面では半導体の自然酸化膜や絶縁膜と半導体との相互
拡散によりこれらが混合した遷移層が形成されているこ
とが知られている。このような遷移層内の結晶欠陥など
が電荷トラップとしてはたらくために、デバイス特性が
不安定性になると考えられている。特にGaAs系化合
物半導体では、半導体表面が酸化した際、Ga酸化物と
As酸化物の蒸気圧が異なるため、遷移層部分にてGa
/As組成比が変化し、これに伴い図11に示すように
素子耐圧が変化する。このため、ウェハ面内やロット間
での素子耐圧を高均一化するためには、保護膜を成膜し
た時の半導体表面の酸化の程度を厳密に制御する必要が
ある。半導体表面の酸化は、保護膜の成膜初期段階に
て、成膜装装置内の酸素ガスや水と半導体が反応して起
こるが、その程度は成膜前のウェハ表面に残存する自然
酸化膜の状態や成膜装置内の到達真空度などの複雑な要
因と相関がある。このためプロセス条件から半導体表面
の酸化の程度を予測することは極めて困難であり、一般
にはデバイス作製プロセスと同一条件で保護膜を成膜し
た後に、保護膜/半導体界面付近の断面をTEM等で観
察して、半導体表面の酸化によって形成された遷移層
(酸化層)の厚さを測定する方法が用いられている。
[0003] In these compound semiconductor devices, an insulating film such as Si02, SiNx or polyimide is used as a protective film on the semiconductor surface, and an insulating film / semiconductor interface is formed in an active part of the element. It is known that at the interface of such a protective film, a transition layer in which a natural oxide film of a semiconductor or an insulating film and a semiconductor are mixed by mutual diffusion is formed. It is considered that such a crystal defect in the transition layer acts as a charge trap, so that device characteristics become unstable. In particular, in a GaAs-based compound semiconductor, when the semiconductor surface is oxidized, the vapor pressures of Ga oxide and As oxide are different.
The / As composition ratio changes, and accordingly, the element breakdown voltage changes as shown in FIG. Therefore, in order to make the device breakdown voltage uniform within the wafer surface or between lots, it is necessary to strictly control the degree of oxidation of the semiconductor surface when the protective film is formed. Oxidation of the semiconductor surface occurs when the semiconductor reacts with oxygen gas or water in the film forming equipment at the initial stage of film formation of the protective film, but to the extent that a natural oxide film remains on the wafer surface before film formation. There is a correlation with complicated factors such as the state of the film and the ultimate vacuum in the film forming apparatus. For this reason, it is extremely difficult to predict the degree of oxidation of the semiconductor surface from the process conditions. In general, after forming a protective film under the same conditions as in the device fabrication process, the cross section near the protective film / semiconductor interface is observed by TEM or the like. A method of observing and measuring the thickness of a transition layer (oxide layer) formed by oxidation of a semiconductor surface is used.

【0004】[0004]

【発明が解決しようとする課題】しかし、前述のような
方法で酸化層厚を測定する場合には以下のような問題が
生ずる。まず、測定対象となる保護膜/半導体界面の酸
化層厚はGaAsの場合には高々1〜2nm程度である
ので、測定にはTEMなどの高倍率の電子顕微鏡を用い
る必要があるが、これらの電子顕微鏡による観察では、
試料厚を0.1μm程度にせねばならず、観察試料の作
成にはイオンミリングなど複雑な工程を要する。また、
イオンミリングにより観察対象である保護膜/半導体界
面部分にもダメージが導入され、これにより酸化層の厚
さや組成が変化してしまうため、正確な測定ができない
という間題がある。更に、前述のような半導体表面酸化
による素子耐圧の変化は極めて敏感であるため、保護膜
界面の酸化層厚さの測定は0.1nm程度の精度で行わ
ねばならず、測定精度の点でも問題である。
However, when the thickness of the oxide layer is measured by the above-described method, the following problems occur. First, the thickness of the oxide layer at the protective film / semiconductor interface to be measured is at most about 1 to 2 nm in the case of GaAs. Therefore, it is necessary to use a high-magnification electron microscope such as a TEM for the measurement. In observation with an electron microscope,
The sample thickness must be set to about 0.1 μm, and a complicated process such as ion milling is required to prepare an observation sample. Also,
Damage is also introduced into the protective film / semiconductor interface portion to be observed by ion milling, which changes the thickness and composition of the oxide layer, thus making it impossible to perform accurate measurement. Further, since the change in the element breakdown voltage due to the oxidation of the semiconductor surface as described above is extremely sensitive, the thickness of the oxide layer at the interface of the protective film must be measured with an accuracy of about 0.1 nm. It is.

【0005】本発明は上記問題点に鑑みてなされたもの
であって、本発明の目的は、化合物半導体材料を用いた
半導体装置の製造プロセスの評価方法に関して、簡便か
つ高精度に半導体表面の酸化量を測定する評価方法を提
供することにある。また、本発明の第2の目的は、上記
の半導体装置の製造プロセスの評価方法に関して、評価
を簡便に行うための評価パタンを提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a simple and highly accurate method for oxidizing a semiconductor surface using a compound semiconductor material. An object of the present invention is to provide an evaluation method for measuring an amount. A second object of the present invention is to provide an evaluation pattern for easily evaluating the above-described method for evaluating a semiconductor device manufacturing process.

【0006】[0006]

【課題を解決するための手段】前記課題を解決するた
め、本出願の請求項1に記載の化合物半導体装置の製造
プロセス評価方法は、前記化合物半導体材料よりも酸化
速度の速い材料に対して前記製造プロセスと同一の条件
の製造プロセスを施し、前記製造プロセスを終了した前
記酸化速度の速い材料の電気抵抗変化を測定することを
特徴とする。また、本出願請求項2に記載の化合物半導
体装置の製造プロセス評価方法は、前記化合物半導体材
料よりも酸化速度の速い材料を含む積層構造をエピタキ
シャル成長する工程と、エッチングにより前記酸化速度
の速い材料が側面に露出するようなメサパタンを作製す
る工程と、前記製造プロセスを終了した前記酸化速度の
速い材料を含むメサパタンの電気抵抗変化を測定するこ
とを特徴とする。
In order to solve the above-mentioned problems, a method for evaluating a manufacturing process of a compound semiconductor device according to claim 1 of the present application uses the method for evaluating a material having a higher oxidation rate than the compound semiconductor material. A manufacturing process is performed under the same conditions as the manufacturing process, and a change in electric resistance of the material having a high oxidation rate after the completion of the manufacturing process is measured. Further, the method for evaluating a manufacturing process of a compound semiconductor device according to claim 2 of the present application includes a step of epitaxially growing a stacked structure including a material having a higher oxidation rate than the compound semiconductor material, and the step of etching the material having a higher oxidation rate by etching. The method is characterized in that a mesa pattern is formed so as to be exposed on the side surface, and a change in electric resistance of the mesa pattern containing the material having a high oxidation rate after the production process is measured.

【0007】また、本出願の請求項3に記載の化合物半
導体装置の製造プロセス評価方法は、前記半導体材料よ
りも酸化速度の速い材料を含む積層構造をエピタキシャ
ル成長する工程と、エッチングにより前記酸化速度の速
い材料が側面に露出するようなメサパタンを作製する工
程と、前記製造プロセスと同一の条件で保護膜を成膜す
る工程を含む製造プロセスを終了した、前記酸化速度の
速い材料を含むメサパタンの電気抵抗変化を測定するこ
とを特徴とする。また、本出願の請求項4に記載の化合
物半導体装置の製造プロセス評価方法は、請求項1から
3の化合物半導体装置の製造プロセス評価方法に加え、
化合物半導体材料のIII族元素がGaで、酸化速度の速
い物質がIII族元素にAlを用いた化合物半導体材料で
あることを特徴とする。また、本出願の請求項5に記載
の発明は、化合物半導体装置の製造プロセス評価に用い
られるプロセス評価パタンであって、製造プロセスによ
る化合物半導体材料の酸化量を測定するために、前記半
導体材料よりも酸化速度の速い材料を含む積層からな
り、前記酸化速度の速い材料が側面に露出しているよう
なメサ型の構造を有し、幅の異なる複数のストライプ状
のパタンから構成されることを特徴としている。
According to a third aspect of the present invention, there is provided a method of evaluating a manufacturing process of a compound semiconductor device, comprising the steps of: epitaxially growing a laminated structure containing a material having an oxidation rate higher than that of the semiconductor material; A mesa pattern including a material having a high oxidation rate is completed after a manufacturing process including a step of forming a mesa pattern in which a fast material is exposed on a side surface and a step of forming a protective film under the same conditions as the manufacturing process. It is characterized by measuring a resistance change. The method for evaluating a manufacturing process of a compound semiconductor device according to claim 4 of the present application is the same as the method for evaluating a manufacturing process for a compound semiconductor device according to claims 1 to 3,
It is characterized in that the group III element of the compound semiconductor material is Ga and the substance having a high oxidation rate is a compound semiconductor material using Al as the group III element. Further, an invention according to claim 5 of the present application is a process evaluation pattern used for evaluating a manufacturing process of a compound semiconductor device, wherein the semiconductor material is used for measuring an oxidation amount of the compound semiconductor material by the manufacturing process. Also has a mesa-type structure such that the material having a high oxidation rate is exposed on the side surface, and is constituted by a plurality of stripe-shaped patterns having different widths. Features.

【0008】本発明のプロセス評価方法によれば、まず
酸化速度の速い材料の抵抗を測定し、その変化量から、
酸化速度の速い材料の酸化量を求める。このため、測定
量は電気抵抗であり、TEM等の複雑な高倍率形態観察
は必要なくなるので評価工程が簡略化できる。また、半
導体材料の酸化量を拡大して測定することができる。次
に、得られた酸化速度の速い材料の酸化量から、半導体
材料の酸化量を求める。表面酸化速度は、酸化量を求め
たい半導体材料と前記酸化速度の速い材料とで比率が一
定であるから、抵抗変化量から得られた酸化速度の速い
材料の酸化量を定数倍することで、半導体の酸化量を精
度良く求めることができる。また、本発明のプロセス評
価パタンは、幅の異なる複数のストライプ状のパタンか
ら構成されているので、これらの導通の有無を測定する
だけでメサ側面からの酸化量を簡便に評価することがで
きる。
According to the process evaluation method of the present invention, first, the resistance of a material having a high oxidation rate is measured, and based on the amount of change,
Obtain the oxidation amount of the material having a high oxidation rate. For this reason, the measured amount is an electric resistance, and a complicated high-magnification morphological observation such as a TEM is not required, so that the evaluation process can be simplified. Further, the amount of oxidation of the semiconductor material can be measured while being enlarged. Next, the oxidation amount of the semiconductor material is determined from the oxidation amount of the obtained material having a high oxidation rate. Since the ratio of the surface oxidation rate is constant between the semiconductor material whose oxidation amount is desired to be determined and the material having a high oxidation rate, the oxidation amount of the material having a high oxidation rate obtained from the resistance change amount is multiplied by a constant, The oxidation amount of the semiconductor can be obtained with high accuracy. Further, since the process evaluation pattern of the present invention is composed of a plurality of stripe-shaped patterns having different widths, the amount of oxidation from the side of the mesa can be easily evaluated simply by measuring the presence or absence of conduction. .

【0009】[0009]

【発明の実施の形態】本発明の一実施の形態について、
図面を参照して説明する。図1(a)〜(c)は、本発
明の一実施の形態である化合物半導体の製造プロセスの
評価方法の製造プロセス評価パタン作成方法を示す工程
順断面図である。製造プロセス評価パタン作成は、まず
半絶縁性GaAs基板1上に、GaAsより酸化速度の
速いAlAsを用いたn型AlAs層2をMBE法など
でエピタキシャル成長した後に、保護膜3を成膜して行
う。保護膜3の成膜条件は製造プロセス評価を行う、G
aAsFET作製プロセスと同一の条件を用いる。これ
によりAlAs層2と保護膜3の界面には、酸化層4が
形成される。次に、図1(b)、(c)に示すように、
フォトレジスト等を用いて所定のマスクパタンを形成し
た後に、保護膜3、酸化層4の一部をエッチングにより
除去し、リフトオフ法などによって電極5、6を形成し
て製造評価パタンが完成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
This will be described with reference to the drawings. FIGS. 1A to 1C are cross-sectional views in the order of steps showing a manufacturing process evaluation pattern creation method of a compound semiconductor manufacturing process evaluation method according to an embodiment of the present invention. The production process evaluation pattern is prepared by first forming an n-type AlAs layer 2 using AlAs having a higher oxidation rate than GaAs by epitaxial growth on a semi-insulating GaAs substrate 1 by MBE or the like, and then forming a protective film 3. . The conditions for forming the protective film 3 are evaluated by manufacturing process evaluation.
The same conditions as in the aAsFET fabrication process are used. Thus, an oxide layer 4 is formed at the interface between the AlAs layer 2 and the protective film 3. Next, as shown in FIGS. 1B and 1C,
After a predetermined mask pattern is formed using a photoresist or the like, a part of the protective film 3 and the oxide layer 4 are removed by etching, and the electrodes 5 and 6 are formed by a lift-off method or the like, thereby completing a manufacturing evaluation pattern.

【0010】前記製造評価パタンの電極5、6間の電気
抵抗を測定すると、図2の結果が得られる。図1に示し
たように、AlAs層2の厚さをd、酸化層4の厚さを
X、電極5、6の電極幅をW、電極5と6の電極間距離
をLとすると、抵抗値Rは次のように表される。R=ρ
L/W(dーX)以上のように、あらかじめ図2のよう
なAlAsに対する参加料と抵抗値の相関を測定してお
けば、任意の製造プロセスに対して求められた電気抵抗
を図2と比較することによりAlAsの酸化量を得るこ
とができる。
When the electric resistance between the electrodes 5 and 6 of the production evaluation pattern is measured, the result shown in FIG. 2 is obtained. As shown in FIG. 1, when the thickness of the AlAs layer 2 is d, the thickness of the oxide layer 4 is X, the width of the electrodes 5 and 6 is W, and the distance between the electrodes 5 and 6 is L, the resistance is The value R is expressed as follows. R = ρ
L / W (dX) As described above, if the correlation between the participation fee and the resistance value for AlAs as shown in FIG. 2 is measured in advance, the electric resistance obtained for an arbitrary manufacturing process can be calculated as shown in FIG. By comparing with, the oxidation amount of AlAs can be obtained.

【0011】次に、前述のように電極5、6間の電気抵
抗値を測定することにより得られたAlAsの酸化量か
らGaAsの酸化量を算出する。図3に示すようにAl
Asの酸化量が50μm程度以下であれば、AlAsの
酸化量d[AlAs]とGaAsの酸化量d[GaA
s]の比は常に一定である。従って、あらかじめ図3の
ような酸化時間に対するAlAsの酸化量とGaAsの
酸化量の相関を測定しておけば、任意のプロセスに対し
てAlAsの酸化量からGaAsの酸化量が算出でき
る。
Next, the oxidation amount of GaAs is calculated from the oxidation amount of AlAs obtained by measuring the electric resistance between the electrodes 5 and 6 as described above. As shown in FIG.
If the oxidation amount of As is about 50 μm or less, the oxidation amount of AlAs d [AlAs] and the oxidation amount of GaAs d [GaAs
s] is always constant. Therefore, if the correlation between the oxidation amount of AlAs and the oxidation amount of GaAs with respect to the oxidation time as shown in FIG. 3 is measured in advance, the oxidation amount of GaAs can be calculated from the oxidation amount of AlAs for an arbitrary process.

【0012】[0012]

【実施例】次に、本発明の実施例について図面を参照し
て詳細に説明する。 (実施例1)図1(d)および図1(c)は、それぞれ
本発明のプロセス評価方法を説明するためのプロセス評
価パタンの平面図およびA−A’線断面図である。また
図1(a)〜(c)は、プロセス評価パタンの作成方法
を説明するための工程順断面図である。図1(a)を参
照すると、第1の実施例によりプロセス評価を行うに
は、まず半絶縁性GaAs基板1上に厚さdのn型Al
As層2をMBE法などでエピタキシャル成長した後
に、保護膜3を成膜する。保護膜の成膜条件はプロセス
評価を行うGaAsFET作製プロセスと同一の条件を
用いる。これによりAlAs層2と保護膜3の界面には
厚さXの酸化層4が形成される。酸化層はAl2O3で
あり、電気的には絶縁物である。AlAs層2の厚さd
は100〜500nm程度が適当である。AlAsの酸
化速度は保護膜形成時の基板温度に強く依存するが、通
常GaAsFET作製プロセスでの保護膜形成条件に用
いられている300℃前後では、100nm/min程
度であり、成膜初期過程でAlAsの表面が酸化される
時間は高々1min程度である。このため、AlAs層
厚が薄すぎる場合には、AlAs層が全て酸化してしま
い抵抗変化を見ることができなくなってしまう。逆に厚
すぎる場合にはAlAs表面の酸化による抵抗変化が僅
かになるために測定精度が低下する。
Next, embodiments of the present invention will be described in detail with reference to the drawings. (Embodiment 1) FIGS. 1D and 1C are a plan view and a cross-sectional view taken along line AA 'of a process evaluation pattern for explaining a process evaluation method of the present invention, respectively. FIGS. 1A to 1C are cross-sectional views in a process order for explaining a method of creating a process evaluation pattern. Referring to FIG. 1A, in order to perform a process evaluation according to the first embodiment, first, an n-type Al having a thickness d is formed on a semi-insulating GaAs substrate 1.
After the As layer 2 is epitaxially grown by MBE or the like, the protective film 3 is formed. The conditions for forming the protective film are the same as those for the GaAs FET manufacturing process for performing the process evaluation. As a result, an oxide layer 4 having a thickness X is formed at the interface between the AlAs layer 2 and the protective film 3. The oxide layer is Al2O3 and is electrically an insulator. The thickness d of the AlAs layer 2
Is suitably about 100 to 500 nm. The oxidation rate of AlAs strongly depends on the substrate temperature at the time of forming the protective film, but is about 100 nm / min at around 300 ° C. which is usually used for forming the protective film in the GaAsFET fabrication process. The time during which the surface of AlAs is oxidized is at most about 1 minute. For this reason, if the thickness of the AlAs layer is too small, the AlAs layer is entirely oxidized, and the change in resistance cannot be seen. Conversely, if the thickness is too large, the change in resistance due to oxidation of the AlAs surface becomes small, and the measurement accuracy is reduced.

【0013】次に、図1(b)、(c)に示すように、
フォトレジスト等を用いて所定のマスクパタンを形成し
た後に保護膜3、酸化層4の一部をエッチングにより除
去し、リフトオフ法などによって電極5、6を形成して
評価パタンが完成する。以上のようにして作製した評価
パタンの電極間の電気抵抗を測定すると、図2のよう
に、酸化状態を変化させたときX=dを漸近線とする双
曲線状の変化を示す。ここで、図2中に示したL、d、
W、X等の記号の意味は図1(c)、(d)と同じであ
る。電極間距離Lや電極幅Wは任意であるが、評価パタ
ン周辺部からのリーク電流の影響を低減し、また酸化量
Xに対する抵抗変化を線形に近づけ、僅かな酸化量に対
する抵抗変化を測定するためにはW/Lは大きいほうが
良い。以上のようにして、あらかじめ図2のようなAl
Asに対する酸化量と抵抗値の相関を測定しておき、任
意のプロセスに対して求められた電気抵抗を図2と比較
することによりAlAsの酸化量を得ることができる。
Next, as shown in FIGS. 1B and 1C,
After a predetermined mask pattern is formed using a photoresist or the like, a part of the protective film 3 and the oxide layer 4 are removed by etching, and electrodes 5 and 6 are formed by a lift-off method or the like to complete an evaluation pattern. When the electrical resistance between the electrodes of the evaluation pattern manufactured as described above is measured, as shown in FIG. 2, when the oxidation state is changed, a hyperbolic change with X = d asymptote is shown. Here, L, d, shown in FIG.
The meanings of symbols such as W and X are the same as in FIGS. 1 (c) and 1 (d). The distance L between the electrodes and the width W of the electrode are arbitrary, but the influence of the leak current from the periphery of the evaluation pattern is reduced, the resistance change with respect to the oxidation amount X is made linear, and the resistance change with respect to a slight oxidation amount is measured. Therefore, it is better that W / L is large. As described above, Al as shown in FIG.
By measuring the correlation between the oxidation amount with respect to As and the resistance value, and comparing the electrical resistance obtained for an arbitrary process with FIG. 2, the oxidation amount of AlAs can be obtained.

【0014】次に、AlAsの酸化量からGaAsの酸
化量を算出する。図3に示すようにAlAsの酸化量が
50μm程度以下であれば、AlAsの酸化量d[Al
As]とGaAsの酸化量d[GaAs]の比は常に一
定で、d[AlAs]/d[GaAs]=1000程度
である。従って、あらかじめ図3のような、酸化時間に
対するd[AlAs]とd[GaAs]の相関を測定し
ておけば、任意のプロセスに対してAlAsの酸化量か
らGaAsの酸化量を拡大した形で評価することができ
る。このように、本発明のプロセス評価方法によればA
lAs層の抵抗変化を測定することにより簡便にGaA
s表面の酸化量を得ることができる。この方法によれ
ば、GaAs基板上にAlAsが堆積されたエピ基板を
用いて、保護膜堆積と電極形成を行うだけでFET作製
プロセスによるGaAs表面の酸化量を知ることができ
る。
Next, the oxidation amount of GaAs is calculated from the oxidation amount of AlAs. As shown in FIG. 3, when the oxidation amount of AlAs is about 50 μm or less, the oxidation amount d [Al
The ratio of the amount of oxidation of As] to the amount of oxidation d [GaAs] of GaAs is always constant, and d [AlAs] / d [GaAs] = about 1000. Therefore, if the correlation between d [AlAs] and d [GaAs] with respect to the oxidation time is measured in advance as shown in FIG. 3, the oxidation amount of GaAs is enlarged from the oxidation amount of AlAs for an arbitrary process. Can be evaluated. Thus, according to the process evaluation method of the present invention, A
GaAs can be easily obtained by measuring the resistance change of the lAs layer.
The amount of oxidation of the s surface can be obtained. According to this method, the amount of oxidation of the GaAs surface by the FET manufacturing process can be known only by depositing a protective film and forming electrodes using an epi-substrate in which AlAs is deposited on a GaAs substrate.

【0015】(実施例2)次に、本発明の第2の実施例
について詳細に説明する。図4(b)、(a)は、それ
ぞれ第2の実施例に用いるプロセス評価パタンの平面図
およびA−A’線断面図である。この第2の実施例の構
成が第1の実施例のそれと大きく異なるところは、周囲
からのリーク電流の影響をなくすために、2つの電極を
同心円上に配置している点である。この第2の実施例の
プロセス評価方法においては、第1の実施例と同様の方
法により、図4のような評価パタンを作製する。作製プ
ロセスの条件等は第1の実施例と同じである。次に2つ
の電極間の電気抵抗を測定すると、抵抗値は、AlAs
層の酸化量xに対して、第1の実施例と同様x=dを漸
近線とする双曲線状に変化するが、電極の一方が他方を
囲む同心円状の電極配置となっているために、評価パタ
ンの周辺部からのリーク電流の影響が無くなり、より精
密に抵抗値の変化を測定できるようになる。その後、第
1の実施例と同じ手続きによりGaAs表面の酸化量を
得ることができる。
(Embodiment 2) Next, a second embodiment of the present invention will be described in detail. FIGS. 4B and 4A are a plan view and a cross-sectional view taken along line AA ′ of a process evaluation pattern used in the second embodiment, respectively. The configuration of the second embodiment is significantly different from that of the first embodiment in that two electrodes are arranged concentrically in order to eliminate the influence of leakage current from the surroundings. In the process evaluation method of the second embodiment, an evaluation pattern as shown in FIG. 4 is produced by the same method as in the first embodiment. The conditions of the fabrication process are the same as in the first embodiment. Next, when the electric resistance between the two electrodes is measured, the resistance value is AlAs
The oxidation amount x of the layer changes in a hyperbolic shape with x = d asymptote as in the first embodiment, but since one of the electrodes has a concentric electrode arrangement surrounding the other, The influence of the leak current from the periphery of the evaluation pattern is eliminated, and the change in the resistance value can be measured more precisely. Thereafter, the amount of oxidation of the GaAs surface can be obtained by the same procedure as in the first embodiment.

【0016】(実施例3)次に、本発明の第3の実施例
について詳細に説明する。図5(e)は、第3の実施例
に用いるプロセス評価パタンの平面図、また図5(a)
〜(d)は、工程順のA−A’線断面図である。この第
3の実施例では、まず半絶縁性GaAs基板1上にn型
GaAs層7、厚さdのn型AlAs層2、n型GaA
s層8を順次MBE法などでエピタキシャル成長する。
なお、半絶縁性基板の代わりにn型GaAs基板を用い
てもよい。この場合にはn型GaAs層7は成長しなく
てもよい。また、n−GaAs層は抵抗率が充分に低く
なるよう1x1018cm−3程度の高濃度にドーピン
グしておく。次に図5(a)に示すように、フォトレジ
スト等で所定のマスクパタンを形成し、図5(b)のよ
うにn型AlAs層2、n型GaAs層8をエッチング
してメサ構造を形成する。その後、図5(c)のように
保護膜3を成膜する。保護膜の成膜条件はプロセス評価
を行うGaAsFET作製プロセスと同一の条件を用い
る。これによりAlAs層2と保護膜3の界面には厚さ
xの酸化層4が形成される。
(Embodiment 3) Next, a third embodiment of the present invention will be described in detail. FIG. 5E is a plan view of a process evaluation pattern used in the third embodiment, and FIG.
(D) is sectional drawing of the AA 'line | wire of a process order. In the third embodiment, first, an n-type GaAs layer 7, an n-type AlAs layer 2 having a thickness d, and an n-type GaAs are formed on a semi-insulating GaAs substrate 1.
The s layer 8 is sequentially grown epitaxially by MBE or the like.
Note that an n-type GaAs substrate may be used instead of the semi-insulating substrate. In this case, the n-type GaAs layer 7 need not be grown. The n-GaAs layer is doped at a high concentration of about 1 × 10 18 cm −3 so that the resistivity is sufficiently low. Next, as shown in FIG. 5A, a predetermined mask pattern is formed with a photoresist or the like, and the n-type AlAs layer 2 and the n-type GaAs layer 8 are etched as shown in FIG. Form. After that, the protective film 3 is formed as shown in FIG. The conditions for forming the protective film are the same as those for the GaAs FET manufacturing process for performing the process evaluation. As a result, an oxide layer 4 having a thickness x is formed at the interface between the AlAs layer 2 and the protective film 3.

【0017】次に、図5(d)に示すように、異方性ド
ライエッチングにより保護膜3をエッチングすることに
より、側壁9を形成する。図6のように、この結果露出
したメサ上部のn型GaAs層8とn型GaAs層7と
をプローブ等で接触して、2端子A、A’間の電気抵抗
を測定すると、n型GaAs層の抵抗率が充分に低いた
め測定される電気抵抗はメサ部分のAlAs層2の抵抗
で、図7のように、酸化状態を変化させたときX=L/
2を漸近線とする双曲線状の変化を示し、その変化の仕
方はR=R0+ρd/4(X−L/2)2となる。ここ
で、Rは測定される抵抗値、Lはメサの断面(正方形)
の一辺の長さ、ρはAlAs層の抵抗率である。また、
R0は接触抵抗などの寄生抵抗であるが小さい値であり
無視してもよい。なお、プローブとn型GaAs層の接
触抵抗のばらつきによる抵抗値のばらつきを避け、より
厳密な評価を行う場合には、側壁形成後にn型GaAs
層上に電極を形成すればよい。AlAs層2の厚さdの
最適値はドーピング濃度とメサの断面積により変わる
が、100〜500nm程度が適当である。厚すぎる場
合にはAlAs表面の酸化による抵抗変化が僅かになる
ために測定精度が低下する。わずかな抵抗変化を測定す
る場合にはL/dを大きくなるように設定すると良い。
以上のようにして、あらかじめ図7のようなAlAsに
対する酸化量と抵抗値の相関を測定しておき、任意のプ
ロセスに対して求められた電気抵抗を図7と比較するこ
とによりAlAsの酸化量を得ることができる。その
後、第1の実施例と同じ手続きによりGaAs表面の酸
化量を得ることができる。
Next, as shown in FIG. 5D, the side wall 9 is formed by etching the protective film 3 by anisotropic dry etching. As shown in FIG. 6, the n-type GaAs layer 8 and the n-type GaAs layer 7 above the mesa exposed as a result are contacted with a probe or the like, and the electrical resistance between the two terminals A and A ′ is measured. Since the resistivity of the layer is sufficiently low, the measured electric resistance is the resistance of the AlAs layer 2 in the mesa portion. As shown in FIG. 7, when the oxidation state is changed, X = L /
A hyperbolic change with 2 asymptote is shown, and the manner of change is R = R0 + ρd / 4 (XL / 2) 2. Here, R is the resistance value to be measured, and L is the cross section (square) of the mesa.
Ρ is the resistivity of the AlAs layer. Also,
R0 is a parasitic resistance such as a contact resistance, but is a small value and may be ignored. In order to avoid a variation in the resistance value due to a variation in the contact resistance between the probe and the n-type GaAs layer and perform a more strict evaluation, it is necessary to form the n-type GaAs after forming the side wall.
An electrode may be formed over the layer. The optimum value of the thickness d of the AlAs layer 2 varies depending on the doping concentration and the cross-sectional area of the mesa, but is suitably about 100 to 500 nm. If the thickness is too large, the change in resistance due to oxidation of the AlAs surface will be small, and the measurement accuracy will decrease. When a slight change in resistance is measured, L / d is preferably set to be large.
As described above, the correlation between the oxidation amount and the resistance value with respect to AlAs as shown in FIG. 7 is measured in advance, and the electrical resistance obtained for an arbitrary process is compared with FIG. Can be obtained. Thereafter, the amount of oxidation of the GaAs surface can be obtained by the same procedure as in the first embodiment.

【0018】この第3の実施例のプロセス評価方法で
は、第1、第2の実施例とは異なり、AlAs層のメサ
を形成し、これを酸化するので、同一の基板を用いて断
面積の異なるメサ構造を作成することができる。このた
め、第1、第2の実施例では電極とAlAs層との接触
抵抗のぱらつきによる抵抗測定精度の低下が避けられな
かったのに対し、本実施例では断面積の異なる複数のメ
サの抵抗値を測定して断面積で規格化することで接触抵
抗を除去して抵抗を測定できるという効果がある。
In the process evaluation method of the third embodiment, unlike the first and second embodiments, the mesa of the AlAs layer is formed and oxidized, so that the same substrate is used to reduce the cross-sectional area. Different mesa structures can be created. For this reason, in the first and second embodiments, a decrease in the resistance measurement accuracy due to the fluctuation of the contact resistance between the electrode and the AlAs layer was unavoidable. In the present embodiment, the resistance of a plurality of mesas having different cross-sectional areas was inevitable. By measuring the value and normalizing it by the cross-sectional area, there is an effect that the contact resistance can be removed and the resistance can be measured.

【0019】(実施例4)次に、本発明の第4の実施例
について詳細に説明する。図8(b)は、第4の実施例
に用いるプロセス評価パタンの平面図、また図8(a)
は、A−A’線断面図である。この第4の実施例では、
メサの断面を円形にしているのが実施例3とは異なる点
である。それ以外のメサの形成方法や評価方法は実施例
3と全く同じである。本実施例ではメサの断面を円形に
したため、測定される電気抵抗は、酸化状態を変化させ
たときX=rを漸近線とする双曲線状の変化を示し、そ
の変化の仕方はR=R0+ρd/π(X−r)2とな
る。ここで、Rは測定される抵抗値、rはメサの断面の
半径、ρはAlAs層の抵抗率である。また、R0は接
触抵抗などの寄生抵抗であるが小さい値であり無視して
もよい。このように、本実施例では実施例3よりも酸化
量に対する抵抗変化が4/πだけ緩やかになっている。
このため、わずかな酸化量を測定するのに適している。
(Embodiment 4) Next, a fourth embodiment of the present invention will be described in detail. FIG. 8B is a plan view of a process evaluation pattern used in the fourth embodiment, and FIG.
Is a sectional view taken along line AA ′. In this fourth embodiment,
The difference from the third embodiment is that the cross section of the mesa is circular. Other mesa formation methods and evaluation methods are exactly the same as those of the third embodiment. In this embodiment, since the cross section of the mesa is circular, the measured electric resistance shows a hyperbolic change with X = r asymptote when the oxidation state is changed, and the way of change is R = R0 + ρd / π (X−r) 2. Here, R is the measured resistance value, r is the radius of the cross section of the mesa, and ρ is the resistivity of the AlAs layer. R0 is a parasitic resistance such as a contact resistance, but is a small value and may be ignored. As described above, in this embodiment, the resistance change with respect to the oxidation amount is smaller by 4 / π than in the third embodiment.
Therefore, it is suitable for measuring a slight oxidation amount.

【0020】(実施例5)次に、本発明の第5の実施例
について詳細に説明する。図9(d)は、第3の実施例
に用いるプロセス評価パタンの平面図、また図9(a)
〜(c)は、工程順のA−A’線断面図、図9(e)は
B−B’線断面図である。この第4の実施例では、メサ
の形状をストライプ状にしているのが実施例3や実施例
4とは異なる点である。まず、図9(a)に示すよう
に、実施例3および実施例4と同様にしてストライプ状
のメサを形成する。ただし、結晶構造は実施例3や実施
例4とは異なり、半絶縁性GaAs基板1上にじかにn
型AlAs層を成長するか、または図9(a)のように
半絶縁性GaAs基板上に高抵抗のノンドープGaAs
10を成長した後にn型AlAs層2を成長し、その後
高抵抗のノンドープGaAs11を成長する。次に、図
9(b)に示すように、フォトレジスト等のマスクパタ
ンを用いて、メサを切断する形で開口部12を形成す
る。その後、図9(c)に示すように電極13、14を
形成して評価パタンが完成する。電極の形成にはリフト
オフ法を用いるのが簡便で適当である。このようにして
形成された電極13、14は、メサ側面に露出したAl
As層とは横方向に接触するいわゆるラテラル型のコン
タクトとなっているが、AlAs層がすべて酸化されて
絶縁物であるAl2O3になるまでは電極間には電流が
流れる。
(Embodiment 5) Next, a fifth embodiment of the present invention will be described in detail. FIG. 9D is a plan view of a process evaluation pattern used in the third embodiment, and FIG.
9C are cross-sectional views taken along line AA ′ in the order of steps, and FIG. 9E is a cross-sectional view taken along line BB ′. The fourth embodiment is different from the third and fourth embodiments in that the mesa is formed in a stripe shape. First, as shown in FIG. 9A, a stripe-shaped mesa is formed in the same manner as in the third and fourth embodiments. However, the crystal structure is different from those of the third and fourth embodiments, and n is directly formed on the semi-insulating GaAs substrate 1.
A type AlAs layer is grown, or a high-resistance non-doped GaAs is formed on a semi-insulating GaAs substrate as shown in FIG.
After growing the n-type AlAs layer 10, the n-type AlAs layer 2 is grown, and then the non-doped GaAs 11 with high resistance is grown. Next, as shown in FIG. 9B, an opening 12 is formed by cutting a mesa using a mask pattern such as a photoresist. Thereafter, as shown in FIG. 9C, electrodes 13 and 14 are formed to complete the evaluation pattern. It is convenient and appropriate to use a lift-off method for forming the electrodes. The electrodes 13 and 14 formed in this way are exposed to Al exposed on the side surfaces of the mesa.
A so-called lateral contact is made in lateral contact with the As layer, but a current flows between the electrodes until the AlAs layer is completely oxidized to Al2O3 which is an insulator.

【0021】このようなストライプ状のメサを、ストラ
イプの幅を変えて複数作成しておき、電極間の導通を測
定することにより、酸化量をより厳密に測定することが
できる。すなわち、ストライプ幅Aのパタンでは導通が
あり、幅Bのパタンでは導通が無いとき、酸化量Xは、
A>2X>Bの関係を満たす。このため、ストライプ幅
を僅かずつ変化させた多数のパタンを作成しておけば、
酸化量Xを厳密に測定することができる。上記のように
してAlAs層の酸化量を測定した後に、第1の実施例
と同じ手続きによりGaAs表面の酸化量を得ることが
できる。本実施例では、実施例1〜4とは異なり、酸化
量の測定に抵抗変化ではなく導通の有無を測定する点で
ある。このため、接触抵抗などの変化による測定精度の
低下を避けることができるという効果がある。
A plurality of such stripe-shaped mesas are prepared by changing the width of the stripe, and the conduction between the electrodes is measured, whereby the oxidation amount can be measured more precisely. That is, when there is conduction in the pattern with the stripe width A and there is no conduction in the pattern with the width B, the oxidation amount X becomes
The relationship of A>2X> B is satisfied. For this reason, if you create a large number of patterns with slightly different stripe widths,
The oxidation amount X can be measured exactly. After measuring the oxidation amount of the AlAs layer as described above, the oxidation amount of the GaAs surface can be obtained by the same procedure as in the first embodiment. This embodiment is different from the first to fourth embodiments in that the measurement of the amount of oxidation is performed not by a resistance change but by the presence or absence of conduction. Therefore, there is an effect that a decrease in measurement accuracy due to a change in contact resistance or the like can be avoided.

【0022】以上、この発明の実施例を図面により詳述
してきたが、具体的な構成はこの実施例に限られるもの
ではなく、この発明の要旨を逸脱しない範囲の設計の変
更等があってもこの発明に含まれる。例えば、上述の第
1実施例では、GaAs層の酸化量を得るために、抵抗
測定によりAlAs層の酸化量を求めたが、これに限ら
ず、AlGaAs層の抵抗測定を行って、その酸化量を
求めても同様の効果が得られる。また、AlAs層の酸
化量からInGaAs層の酸化量を得ることもできる。
このほか、V族元素にリンやアンチモン等他の材料を用
いても同様の効果が得られる。また、実施例では、評価
の対象となる製造プロセスとしてCVD法によるSi0
2保護膜成膜について述べたが、これに限らずSiNx
成膜プロセスや熱酸化プロセス、プラズマ処理、ウェッ
ト処理など半導体表面を酸化させるプロセスであれば同
様に酸化量を簡便かつ高精度に求めることができる。
Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like that do not depart from the gist of the present invention. Is also included in the present invention. For example, in the above-described first embodiment, in order to obtain the oxidation amount of the GaAs layer, the oxidation amount of the AlAs layer was obtained by measuring the resistance. However, the present invention is not limited to this. , The same effect can be obtained. Also, the oxidation amount of the InGaAs layer can be obtained from the oxidation amount of the AlAs layer.
In addition, the same effect can be obtained by using another material such as phosphorus or antimony as the group V element. Further, in the embodiment, as a manufacturing process to be evaluated, Si0
2 The formation of the protective film has been described, but not limited thereto.
Similarly, any process that oxidizes the semiconductor surface, such as a film forming process, a thermal oxidation process, a plasma process, or a wet process, can easily and accurately determine the amount of oxidation.

【0023】[0023]

【発明の効果】以上説明したように本発明の請求項1お
よび4記載の構成によれば、化合物半導体装置の製造プ
ロセスによる化合物半導体の酸化量を測定するために、
半導体材料よりも酸化速度の速い材料に対して、酸化量
を測定する対象である製造プロセスと同一の条件のプロ
セスを施し、酸化速度の速い材料の電気抵抗変化を測定
するので、従来のような高倍率の顕微鏡観察を用いる方
法と比べて簡便かつ高精度に化合物半導体の酸化量を測
定することができる。
As described above, according to the first and fourth aspects of the present invention, in order to measure the amount of oxidation of a compound semiconductor in a manufacturing process of a compound semiconductor device,
A material with a higher oxidation rate than a semiconductor material is subjected to a process under the same conditions as the manufacturing process for which the amount of oxidation is to be measured, and the electrical resistance change of the material with a higher oxidation rate is measured. Compared with the method using high-power microscope observation, the amount of oxidation of the compound semiconductor can be measured simply and with high accuracy.

【0024】また、請求項2および3、4記載の構成に
よれば、化合物半導体装置の製造プロセスによる化合物
半導体材料の酸化量を測定するために、半導体材料より
も酸化速度の速い材料を含む積層構造により構成され、
かつ酸化速度の速い材料が側面に露出するようなメサパ
タンを用いて、酸化量を測定する対象である製造プロセ
スと同一の条件のプロセスを含む製造プロセスを施し、
酸化速度の速い材料を含むメサパタンの電気抵抗変化を
測定するので、請求項1記載構成で得られる効果に加え
て、断面積の異なる複数のメサの抵抗値を測定して断面
積で規格化することができる。このため、接触抵抗を除
去してさらに厳密に抵抗を測定できるので、より高精度
に化合物半導体の酸化量を測定できる。
According to the second, third, and fourth aspects of the present invention, in order to measure the amount of oxidation of the compound semiconductor material in the manufacturing process of the compound semiconductor device, a stack including a material having a higher oxidation rate than the semiconductor material is used. It is composed of a structure,
By using a mesa pattern in which a material having a high oxidation rate is exposed on the side surface, a manufacturing process including a process under the same conditions as a manufacturing process whose oxidation amount is to be measured is performed.
Since the electrical resistance change of a mesa pattern containing a material having a high oxidation rate is measured, in addition to the effect obtained by the configuration according to claim 1, the resistance values of a plurality of mesas having different cross-sectional areas are measured and normalized by the cross-sectional area. be able to. Therefore, the contact resistance can be removed and the resistance can be measured more strictly, so that the oxidation amount of the compound semiconductor can be measured with higher accuracy.

【0025】また、請求項5記載の構成によれば、請求
項2および3、4記載の構成に関して、半導体材料より
も酸化速度の速い材料を含む積層からなり、前記酸化速
度の速い材料が側面に露出しているようなメサ型の構造
を有し、幅の異なる複数のストライプ状のパタンから構
成されるプロセス評価パタンを用いると、複数のパタン
での導通の有無を測定することにより、さらに簡便に化
合物半導体の酸化量を測定できる。
According to a fifth aspect of the present invention, in the configuration of the second, third, or fourth aspect, the laminated structure includes a material having a higher oxidation rate than the semiconductor material. With a mesa-type structure such as exposed to the process evaluation pattern composed of a plurality of stripe-shaped patterns having different widths, by measuring the presence or absence of conduction in a plurality of patterns, The amount of oxidation of the compound semiconductor can be easily measured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明の第1実施例であるプロセス評価方
法に用いる評価パタンの構造を示す図であり、(c)は
断面図、(a)、(b)は評価パタンの製造途中の工程
順断面図、(d)は平面図である。
FIGS. 1A and 1B are diagrams showing a structure of an evaluation pattern used in a process evaluation method according to a first embodiment of the present invention, wherein FIG. 1C is a cross-sectional view, and FIGS. (D) is a plan view.

【図2】 この発明の第1実施例であるプロセス評価方
法に用いる評価パタンの、酸化量Xと電気抵抗Rの関係
を表す図である。
FIG. 2 is a diagram showing a relationship between an oxidation amount X and an electric resistance R of an evaluation pattern used in a process evaluation method according to a first embodiment of the present invention.

【図3】 GaAsとAlAsに対する酸化時間と酸化
量Xの関係を表す図である。
FIG. 3 is a diagram showing a relationship between an oxidation time and an oxidation amount X for GaAs and AlAs.

【図4】 この発明の第2実施例であるプロセス評価方
法に用いる評価パタンの構造を示す図であり、(a)は
断面図、(b)は平面図である。
FIGS. 4A and 4B are diagrams showing a structure of an evaluation pattern used in a process evaluation method according to a second embodiment of the present invention, wherein FIG. 4A is a cross-sectional view and FIG.

【図5】 この発明の第3実施例であるプロセス評価方
法に用いる評価パタンの構造を示す図であり、(d)は
断面図、(a)、(b)、(c)は評価パタンの製造途
中の工程順断面図、(e)は平面図である。
5A and 5B are diagrams showing a structure of an evaluation pattern used in a process evaluation method according to a third embodiment of the present invention, wherein FIG. 5D is a cross-sectional view, and FIGS. FIG. 4E is a sectional view in the order of processes during manufacturing, and FIG.

【図6】 この発明の第3実施例であるプロセス評価方
法での抵抗測定の方法を示す図である。
FIG. 6 is a diagram showing a method of measuring resistance in a process evaluation method according to a third embodiment of the present invention.

【図7】 この発明の第3実施例であるプロセス評価方
法に用いる評価パタンの、酸化量Xと電気抵抗Rの関係
を表す図である。
FIG. 7 is a diagram showing a relationship between an oxidation amount X and an electric resistance R of an evaluation pattern used in a process evaluation method according to a third embodiment of the present invention.

【図8】 この発明の第4実施例であるプロセス評価方
法に用いる評価パタンの構造を示す図であり、(a)は
断面図、(b)は平面図である。
8A and 8B are diagrams showing a structure of an evaluation pattern used in a process evaluation method according to a fourth embodiment of the present invention, wherein FIG. 8A is a sectional view and FIG. 8B is a plan view.

【図9】 この発明の第5実施例であるプロセス評価方
法に用いる評価パタンの構造を示す図であり、(d)は
断面図、(a)、(b)、(c)は評価パタンの製造途
中の工程順断面図、(e)は平面図である。
FIG. 9 is a view showing a structure of an evaluation pattern used in a process evaluation method according to a fifth embodiment of the present invention, wherein (d) is a cross-sectional view, and (a), (b) and (c) are evaluation patterns. FIG. 4E is a sectional view in the order of processes during manufacturing, and FIG.

【図10】 従来のMESFETの半導体チッブ構造を
示す図であり、(a)は断面図、(b)は平面図であ
る。
10A and 10B are diagrams showing a semiconductor chip structure of a conventional MESFET, where FIG. 10A is a cross-sectional view and FIG. 10B is a plan view.

【図11】 従来のMESFETの保護膜界面の表面酸
化量と耐圧の関係を示す図である。
FIG. 11 is a diagram showing the relationship between the amount of surface oxidation at the protective film interface and the breakdown voltage of a conventional MESFET.

【符号の説明】[Explanation of symbols]

1 半絶縁性GaAs基板 2 n型GaAs層 3 SiO2保護膜 4 酸化層 5 電極 6 電極 7 n型GaAs腰 8 n型GaAs層 9 側壁 10 ノンドープGaAs層 11 ノンドープGaAs層 12 開口部 13 電極 14 電極 15 n型GaAs能動層 16 n型GaAsオーミックコンタクト層 17 ゲート電極 18 ドレイン電極 19 ソース電極 20 保護膜 Reference Signs List 1 semi-insulating GaAs substrate 2 n-type GaAs layer 3 SiO2 protective film 4 oxide layer 5 electrode 6 electrode 7 n-type GaAs waist 8 n-type GaAs layer 9 sidewall 10 non-doped GaAs layer 11 non-doped GaAs layer 12 opening 13 electrode 14 electrode 15 n-type GaAs active layer 16 n-type GaAs ohmic contact layer 17 gate electrode 18 drain electrode 19 source electrode 20 protective film

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 化合物半導体装置の製造プロセス評価方
法であって、前記化合物半導体材料よりも酸化速度の速
い材料に対して前記製造プロセスと同一の条件の製造プ
ロセスを施し、前記製造プロセスを終了した前記酸化速
度の速い材料の電気抵抗変化を測定することを特徴とす
る化合物半導体装置の製造プロセス評価方法。
1. A method for evaluating a manufacturing process of a compound semiconductor device, wherein a manufacturing process under the same conditions as the manufacturing process is performed on a material having an oxidation rate higher than that of the compound semiconductor material, and the manufacturing process is terminated. A method for evaluating a manufacturing process of a compound semiconductor device, comprising: measuring a change in electric resistance of the material having a high oxidation rate.
【請求項2】 化合物半導体装置の製造プロセス評価方
法であって、前記化合物半導体材料よりも酸化速度の速
い材料を含む積層構造をエピタキシャル成長する工程
と、エッチングにより前記酸化速度の速い材料が側面に
露出するようなメサパタンを作製する工程と、前記製造
プロセスを終了した前記酸化速度の速い材料を含むメサ
パタンの電気抵抗変化を測定することを特徴とする化合
物半導体装置の製造プロセス評価方法。
2. A method for evaluating a manufacturing process of a compound semiconductor device, comprising the steps of: epitaxially growing a laminated structure containing a material having a higher oxidation rate than the compound semiconductor material; and exposing the material having a higher oxidation rate to a side surface by etching. A method of manufacturing a compound semiconductor device, the method comprising: measuring a change in electric resistance of a mesapatan containing a material having a high oxidation rate after the completion of the manufacturing process.
【請求項3】 化合物半導体装置の製造プロセス評価方
法であって、前記半導体材料よりも酸化速度の速い材料
を含む積層構造をエピタキシャル成長する工程と、エッ
チングにより前記酸化速度の速い材料が側面に露出する
ようなメサパタンを作製する工程と、前記製造プロセス
と同一の条件で保護膜を成膜する工程を含む製造プロセ
スを終了した、前記酸化速度の速い材料を含むメサパタ
ンの電気抵抗変化を測定することを特徴とする化合物半
導体装置の製造プロセス評価方法。
3. A method for evaluating a manufacturing process of a compound semiconductor device, comprising the steps of: epitaxially growing a laminated structure including a material having a higher oxidation rate than the semiconductor material; and exposing the material having a higher oxidation rate to a side surface by etching. A step of manufacturing such a mesapattern, and a manufacturing process including a step of forming a protective film under the same conditions as the manufacturing process are completed, and measuring a change in electrical resistance of the mesapatan including the material having a high oxidation rate. A method for evaluating a manufacturing process of a compound semiconductor device.
【請求項4】 化合物半導体材料のIII族元素がGa
で、酸化速度の速い物質がIII族元素にAlを用いた化
合物半導体材料であることを特徴とする請求項1乃至請
求項3記載の化合物半導体装置の製造プロセス評価方
法。
4. The compound III element of the compound semiconductor material is Ga
4. The method according to claim 1, wherein the substance having a high oxidation rate is a compound semiconductor material using Al as a group III element.
【請求項5】 化合物半導体装置の製造プロセス評価に
用いられるプロセス評価パタンであって、製造プロセス
による化合物半導体材料の酸化量を測定するために、前
記半導体材料よりも酸化速度の速い材料を含む積層から
なり、前記酸化速度の速い材料が側面に露出しているよ
うなメサ型の構造を有し、幅の異なる複数のストライプ
状のパタンから構成されることを特徴とするプロセス評
価パタン。
5. A process evaluation pattern used for evaluating a manufacturing process of a compound semiconductor device, wherein the stack includes a material having an oxidation rate higher than that of the semiconductor material in order to measure an oxidation amount of the compound semiconductor material in the manufacturing process. A process evaluation pattern comprising a plurality of stripe-shaped patterns having a mesa structure in which the material having a high oxidation rate is exposed on a side surface thereof and having different widths.
JP30623597A 1997-11-07 1997-11-07 Manufacturing process evaluation method and process evaluation pattern for compound semiconductor device Expired - Fee Related JP3223865B2 (en)

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Application Number Priority Date Filing Date Title
JP30623597A JP3223865B2 (en) 1997-11-07 1997-11-07 Manufacturing process evaluation method and process evaluation pattern for compound semiconductor device

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JPH11145232A true JPH11145232A (en) 1999-05-28
JP3223865B2 JP3223865B2 (en) 2001-10-29

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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006343587A (en) * 2005-06-09 2006-12-21 Toshiba Corp Method for creating evaluation pattern, and program

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW502133B (en) 1999-06-10 2002-09-11 Wako Pure Chem Ind Ltd Resist composition, agent and method for reducing substrate dependence thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006343587A (en) * 2005-06-09 2006-12-21 Toshiba Corp Method for creating evaluation pattern, and program

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