JPH11145019A - Structure of semiconductor substrate and method for manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a partial SOI substrate, together with its manufacturing method, wherein no void takes place at a joint surface of a vertical power element formation region, which affects on device characteristics of a power IC, while a good joint interface is provided across the entire substrate surface. SOLUTION: Related to the structure of a semiconductor substrate wherein secular polish surfaces of a pair of two semiconductor substrates are tightly jointed each other, an insulating layer 3 is formed at a part of a main surface which is to be a joint surface of one semiconductor substrate, at least one notch 6 acting as a tight-joint end point is formed at a peripheral part of at least one semiconductor substrate, and related to the shape of the notch 6, the length in substrate's radius direction is preferred to be equal to that in substrate's circumferential direction or longer, with a wedge-like notch also preferred.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor substrate formed by closely bonding mirror-polished surfaces of two pairs of semiconductor substrates to each other and a method of manufacturing the same.

[0002]

3 (a), 3 (b), 3 (c), 3 (d) and 3 (e) are cross-sectional views showing the manufacturing steps of a first conventional example, and FIG. 4 is a second conventional example. It is sectional drawing which shows the state just before joining of the board | substrate of an example.

[0003] The substrate bonding method has recently attracted attention as a method for manufacturing a multilayer film structure substrate, particularly an SOI substrate, and is being developed. SOI (Silicon On Insulator) substrates have been put to practical use in high-voltage devices for power control, and research and development have been active as substrates for next-generation CMOS operating at low voltage. Among them, based on the track record of high-voltage devices in the field of power devices, we have developed substrates for intelligent power devices (IPDs) aiming for higher functionality, higher integration, and higher reliability. The application of the bonded SOI substrate has been activated.

In the IPD, it is necessary to mix a high-voltage power device for controlling a large current and a peripheral circuit device for controlling the power device on the same chip. A partial SOI substrate is used to form the power device and the device of the peripheral circuit portion on the same chip and electrically insulate them completely.

A first conventional example shown in FIGS. 3 (a) to 3 (e) will now be described.
The method will be described with reference to the cross-sectional views in the order of steps showing the method of manufacturing the I-board.

First, an oxide film and then a nitride film are formed on one main surface of an n ⁺ -type single crystal silicon substrate 21, a photoresist having a predetermined pattern is formed by photolithography, and a predetermined location is opened. . Next, a shallow step is formed by ion etching or the like using the photoresist as a mask. Thermal oxidation or CVD (Chemical Vapor Depositio
A plurality of SiO ₂ insulating films 23 are partially formed in the shallow step region by the n) method or the like (FIG. 3A). next,
For example, mechanical and chemical polishing (CMP) so that the exposed surface of the single crystal silicon of the substrate 21 and the surface of the insulating film 23 become flat.
Or the insulating film 23 is removed by hydrofluoric acid chemical etching (FIG. 3B).

The flat surface including the single-crystal silicon obtained as described above and the insulating film 23 partially formed is opposed to one main surface of the other n ⁻ -type single-crystal silicon substrate 22. Hold and glue gently in a clean atmosphere at room temperature. Thereafter, a heat treatment at 800 to 1100 ° C. is performed to obtain one strongly bonded composite substrate (FIG. 3).
(C)).

Next, the substrate 2 is moved to the YY ′ plane in FIG.
2 is thinned by grinding and polishing to make the silicon substrate 22 a desired thickness and flatten the surface thereof, thereby forming a device active layer 22a made of a single crystal silicon thin film.
Is formed (FIG. 3D).

Separation grooves 26 for element isolation are formed on the device active layer 22a by alkali etching to separate a vertical power element formation region and a control circuit element formation region, and a single crystal of the control circuit element formation region. The silicon active layer is divided into single crystal silicon islands (FIG. 3E).

Next, an insulating film made of SiO ₂ or the like is formed on the surfaces of the device active layer 22a and the isolation groove 26 by thermal oxidation or CVD, and then a polycrystalline silicon layer is formed by CVD. After that, the polycrystalline silicon layer and the insulating film on the substrate surface are removed by grinding / polishing or etching, and the isolation groove 26 is filled with polycrystalline silicon to obtain an SOI substrate in which the element formation regions are insulated and separated. Thereafter, a region surrounded by the insulating film 23 and the isolation groove 26 is formed with a low breakdown voltage CMOS circuit or the like, and a region where the device active layer 22a and the silicon substrate 21 are directly bonded is formed with a high breakdown voltage vertical MOSFET element. Is done.

As for a method of bonding two single-crystal Si substrates, there is, for example, a method disclosed in Japanese Patent Application Laid-Open No. 5-152549, which is a second conventional example shown in FIG. Hereinafter, the manufacturing method will be described with reference to FIG.

An oxide film 43 is formed on the entire surface of each of the first silicon substrate 41 and the second silicon substrate 42 by thermal oxidation. Next, in a clean atmosphere at room temperature, the first substrate 41 is suction-fixed substantially horizontally on a vacuum suction table (not shown). OF (Orientation Flat) of the second substrate 42
A portion in the vicinity of the portion 44 is sucked by vacuum tweezers 47. The operation of the vacuum tweezers 47 causes the second substrate 4
The second substrate 42 is tilted and held such that the second OF section 44 is slightly lowered. In this state, the second substrate 42 is gradually lowered from the position above the first substrate 41,
The edges of the joint surfaces of the OF portions 44 of both substrates are lightly contacted.

Next, the two substrates are brought close to each other until the distance between the ends 45 opposite to the OF portion 44 becomes about 1 mm.
After that, the suction of the second substrate 42 by the vacuum tweezers is stopped. The second substrate 42 rotates by its own weight with the edge of the joint surface of the OF section 44 in contact with the first substrate 41 as a fulcrum, and the entire surface of the first substrate 41 and the entire surface of the second substrate 42 Are brought into contact with each other, and the joining proceeds gradually from the side of the OF section 44 toward the end 45 opposite to the OF.

In this manner, the first substrate 21 (or 41) and the second substrate 22 (or 42) are tightly joined to obtain an integrated substrate.

[0015]

The above-mentioned first conventional example,
In the partial SOI substrate disclosed in JP-A-3-29353, one of the single-crystal silicon surface and the insulating film surface is excessively polished by polishing the mixed surface including the pattern of the insulating film 23 on the single-crystal silicon substrate 21. It is inevitable that a minute step is formed. Therefore, the flatness of the mixed surface is insufficient, so that a void (unbonded portion) is generated on the bonded surface of the two substrates. As a result, peeling occurs from the void portion at the time of subsequent device fabrication, and for example, there occurs a disadvantage that the vertical power element does not function.

The reason is that, when planarizing a mixed surface of single-crystal silicon and a partially formed insulating film, a step between the single-crystal silicon surface and the insulating film surface is reduced by today's polishing technique or etching technique. This is because it is extremely difficult to planarize so as not to leave any.

Also, from experiments conducted by the inventors, when the method of bonding from the substrate end as described in the prior art is applied to the bonding of the substrates, an oxide film is uniformly formed on the entire surface of the substrate. In the case of a substrate on which an oxide film pattern is formed, the progress of adhesion due to the weight of the substrate is slower than in the case
There is a tendency that voids tend to remain at the opposite end. The present inventors have proposed a method in which a rectangular oxide film having a length of about 1 mm and a width of about 2 mm is periodically patterned on the entire surface of a substrate, and the O.D.
An experiment of bonding using F as an adhesion starting point was performed. The method for manufacturing the substrate and the method for bonding are the same as in the conventional example. The voids were observed using ultrasonic flaw detection. as a result,
Peripheral edge of substrate (adhesion end point) opposite to OF section (adhesion start point)
It was found that voids having a size of 1 mm to several mm remained.

The reason why voids are generated is that the oxide film pattern acts to prevent the air layer sandwiched between the substrates from being discharged, as compared with the case where an ordinary oxide film is formed on the entire surface, and particularly the end point of the adhesion. In the vicinity, it is difficult for the layer of air swept out of the bonded area to be smoothly discharged in the direction of the unbonded area,
This is because it is considered that voids finally remain near the bonding end point.

Accordingly, an object of the present invention is to provide a partial SOI substrate which has no voids on the bonding surface of the vertical power element forming region which affects the device characteristics of the intelligent power IC and has a good bonding interface over the entire surface of the substrate. The structure of the
And a method for producing the same.

[0020]

According to the structure of the semiconductor substrate of the present invention, in the structure of a semiconductor substrate in which mirror-polished surfaces of two paired semiconductor substrates are closely bonded to each other, one of the paired semiconductor substrates is formed. An insulating layer is formed on a part of the main surface serving as a bonding surface of the substrate, and a close bonding start point and a close bonding end point are defined on the periphery of the pair of two semiconductor substrates. The semiconductor device is characterized in that at least one notch is formed in the peripheral portion of the semiconductor substrate to serve as an end point of close bonding.

The shape of the notch is preferably such that the length in the radial direction of the substrate is equal to or greater than the length in the circumferential direction of the substrate, and the notch is also preferably wedge-shaped.

The method of manufacturing a semiconductor substrate according to the present invention is a method of manufacturing a semiconductor substrate in which mirror-polished surfaces of two semiconductor substrates forming a pair are closely bonded to each other, in a clean atmosphere at room temperature. Fixing the semiconductor substrate so that the OFs, which are the starting points of the close bonding of the semiconductor substrate, coincide with each other;
The method is characterized by including a step of contacting from a portion F, a step of gradually bonding the semiconductor substrates toward the notch while holding each semiconductor substrate, and a step of terminating the bonding at the notch.

Preferably, the bonding of the semiconductor substrates is performed in the air, in an oxidizing atmosphere, or in a vacuum. In a method of manufacturing a semiconductor substrate in which mirror-polished surfaces are closely bonded to each other, an insulating layer forming step of partially forming a plurality of insulating films on one main surface of one of the paired semiconductor substrates; Is an insulating film retreating process in which processing is performed so as to be lower than the surface without the insulating layer, and one main surface of one semiconductor substrate in which the insulating layer is embedded and a mirror-polished surface of another semiconductor substrate are joined. An adhesive bonding step, a heat treatment step of heat-treating the bonded semiconductor substrate at a temperature of 1000 ° C. or more, a substrate outer peripheral chamfering step of removing an outer peripheral portion of the bonded semiconductor substrate, By thinning the main surface which are not joined in one semiconductor substrate by grinding and polishing, it is characterized by having a grinding and polishing process for forming the device active layer.

[0024]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing the position of a notch on a bonding surface of a substrate used in an embodiment of the structure of a semiconductor substrate according to the present invention, and FIG. Schematic perspective views of two semiconductor substrates to be formed, (b) and (c)
4A to 4C are cross-sectional views sequentially showing manufacturing steps of the embodiment.

The semiconductor substrate of this embodiment is a semiconductor substrate formed by closely bonding two mirror-polished surfaces of two semiconductor substrates forming a pair with each other as a bonding surface. The substrate has an insulating layer on a part of the main surface serving as the bonding surface, and the insulating layer is provided at a position recessed from the main surface of the semiconductor substrate.

The method of manufacturing a semiconductor substrate according to the present invention comprises, as a basic configuration, an insulating film forming step, an insulating film retreating process, a bonding step, a heat treatment step, a chamfering step on the outer periphery of the substrate, and a grinding and polishing step. doing. The processing content of each step is as described above.

Next, a bonding portion SO optimal for monolithically integrating the vertical power element and the control circuit element.
First, the manufacturing method of the present invention will be described in the order of steps with reference to the plan view of FIG. 1 and the cross-sectional view of FIG.

First, an n ⁻ -type single crystal silicon substrate 2 having a diameter of about 125 mm (5 inches) and a resistivity of about 1 Ωcm is prepared. FIG. 1 is a plan view showing a main surface to be a bonding surface of the silicon substrate 2 in a table. The silicon substrate 2 is about 45 m
m orientation flat (hereinafter referred to as OF)
A notch 6 having a length in the circumferential direction of about 2 mm and a length in the radial direction of about 5 mm is formed in the end 5 opposite to the OF. The cut surface of the notch 6 and the boundary between the cut surface and the main surface of the substrate are subjected to a rounding process, for example, by immersion in a hydrofluoric acid-based etching solution, so that a smooth surface is obtained. The main surface of the silicon substrate 2 is selectively oxidized (L
A plurality of insulating films 2 each having a short side of about 1 mm, a long side of about 2 mm, and a thickness of about 2 μm are formed by OCOS. It should be noted that the insulating film 3 in the figure is partially omitted for the sake of explanation, and the size and number of patterns on the substrate are not accurate. Next, the insulating film 3 is thinned to a thickness of 900 nanometers with a hydrofluoric acid-based etching solution so that the surface of the insulating film 3 is lower than the single crystal silicon surface of the silicon substrate 2.

Next, a diameter of about 125 mm and a thickness of about 600 μm
An n ⁺ -type single-crystal silicon substrate 1 having m and a resistivity of about 0.01 to 0.02 Ωcm is prepared. The silicon substrate 1 has an OF having the same length as the silicon substrate 2. The main surface of the silicon substrate 1 and the main surface of the silicon substrate 2 on which the insulating film 3 is partially formed are held facing each other in the atmosphere at room temperature. At this time, both OFs are matched. FIG. 2A shows the relative positional relationship between the two substrates at this time. FIG.
(B) is a cross-sectional view seen from the side for explaining a specific holding method. The silicon substrate 1 is gently set on a horizontally mounted vacuum suction table 8, and is fixed by suction using a vacuum pump or the like. Further, the silicon substrate 2 sucks and holds the vicinity of the OF section 4 with vacuum tweezers 7.

Next, the silicon substrate 2 is brought closer from above the silicon substrate 1 so that the OF portions of the two substrates coincide with each other. The end portions of the OF portion are gently brought into contact so as to match, and then the vacuum tweezers 7 are separated from the silicon substrate 2 so that the adhesion proceeds by its own weight. In this way, the adhesion of the two substrates proceeds in the direction of the notch 6 starting from the OF portion. At this time, the boundary line between the bonded region and the non-bonded region (hereinafter referred to as a bonding wavefront) advances in parallel with the row of the insulating films 3, and the air sandwiched between the substrates is swept out to the non-bonded region. For example, the progress of the adhesion can be confirmed by observing the substance with infrared rays having a wavelength transmitted through the silicon substrate. When the adhesive wavefront is applied to the notch 6, the adhesive wavefront is bonded so as to surround the notch portion, and the air swept out to the non-adhered area is discharged outside the substrate through the notch 6. In this manner, the two substrates are bonded with the notch 6 as the bonding end point.

After the bonding of the substrates is completed, heat treatment is performed at 1000 to 1200 ° C. for about 2 hours to strengthen the bonding.

Next, the peripheral portion of the silicon substrate 2 is removed by grinding or an alkaline etching solution or the like, and an unbonded region at the peripheral portion of the substrate is removed. Finally, as shown in FIG. 2 (c), the silicon substrate 2 is ground to a desired thickness by grinding and polishing from the side of the unbonded main surface, and the surface is flattened. A silicon device active layer 2a is formed.

This bonding step is desirably performed in a sufficiently clean environment in which particles do not float. Further, the bonding atmosphere is not particularly limited to the air, and may be performed in an oxygen atmosphere or in a vacuum, for example.

The length of the notch 6 formed on the side opposite to the OF serving as the bonding starting point in the radial direction of the substrate is equal to or greater than the length of the notch in the tangential direction of the substrate. This is for the purpose of efficiently sweeping out the air sandwiched between the substrates near the end point of the adhesion. In the present embodiment, a rectangular notch having a long side in the substrate radial direction is shown. However, if there is room in the chip design or the like of the device, for example, a wedge-shaped (V-shaped) or trapezoidal notch is used. Has the same effect.

[0036]

As described above, according to the present invention, a notch is formed in the peripheral portion of a substrate, and air interposed between the substrates is swept through the notch at the end point of adhesion of the two substrates, thereby forming a void. Can be bonded without leaving
A semiconductor suitable for intelligent power ICs with high reliability without generation of voids on the bonding surface of the substrate, no cracking or peeling of the device active layer in the device manufacturing process, and no deterioration of device characteristics due to voids There is an effect that the structure and manufacturing method of the device can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view showing the position of a notch in a bonding surface of a substrate used in an embodiment of the structure of a semiconductor substrate of the present invention.

FIG. 2A is a schematic perspective view of two semiconductor substrates to be joined according to the embodiment, and FIGS. 2B and 2C are cross-sectional views sequentially illustrating manufacturing steps of the embodiment. is there.

FIG. 3 (a), (b), (c), (d) and (e)
3A to 3C are cross-sectional views sequentially showing manufacturing steps of a first conventional example.

FIG. 4 is a cross-sectional view showing a state immediately before bonding of a substrate of a second conventional example.

[Explanation of symbols]

1,21,41 n ⁺ -type single-crystal silicon substrate 2,22,42 n ^-- type single-crystal silicon substrate 2a, 22a Device active layer 3,23,43 Insulating film 4,24,44 OF section 5,45 OF section Opposite end 6 Notch 7,47 Vacuum tweezers 8,48 Suction table 26 Separation groove

Claims (6)

[Claims] In a semiconductor substrate structure in which mirror-polished surfaces of two semiconductor substrates forming a pair are closely bonded to each other, a part of a main surface to be a bonding surface of one of the paired semiconductor substrates is provided. An insulating layer is formed, and a bonding start point and a bonding end point are defined at the peripheral edge of the pair of two semiconductor substrates, and at least one of the peripheral edges of the semiconductor substrate is A structure of a semiconductor substrate, wherein at least one notch for forming a close bonding end point is formed. 2. The structure of a semiconductor substrate according to claim 1, wherein the shape of the notch is such that a length in a radial direction of the substrate is longer than a length in a circumferential direction of the substrate. 3. The structure of a semiconductor substrate according to claim 1, wherein said notch has a wedge shape. 4. A method of manufacturing a semiconductor substrate, comprising bonding two mirror-polished surfaces of two paired semiconductor substrates in close contact with each other, comprising: starting said close bonding of said semiconductor substrates in a clean atmosphere at room temperature. Fixing a point orientation flat so as to match; contacting from the orientation flat portion; gradually bonding the semiconductor substrate toward the notch while holding each semiconductor substrate; A method for manufacturing a semiconductor substrate, comprising a step of terminating bonding at a portion. 5. The method according to claim 4, wherein the bonding of the semiconductor substrate is performed in the air, in an oxidizing atmosphere, or in a vacuum. 6. A method of manufacturing a semiconductor substrate comprising two mirror-polished surfaces of two semiconductor substrates forming a pair, the plurality of insulating films being formed on one main surface of one of the paired semiconductor substrates. An insulating layer forming step of partially forming, an insulating film retreating step of processing the surface of the insulating layer to be lower than a surface without the insulating layer, and one of the insulating layers embedded therein. An adhesion bonding step of bonding one main surface of the semiconductor substrate to a mirror-polished surface of another semiconductor substrate; a heat treatment step of heat-treating the bonded semiconductor substrate at a temperature of 1000 ° C. or higher; A substrate outer peripheral chamfering step of removing an outer peripheral portion of the substrate; and forming a device active layer by grinding and polishing a non-bonded main surface of one of the bonded semiconductor substrates to form a thin film. And a grinding and polishing step.